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This may be a homework problem, but it is summer school, so why not? I'm bored. In article <7b390929.0308100714.550cc60a@posting.google.com>, Zhen <zhenxu2000@hotmail.com> wrote: >There are two vectors, named V1 and V2, the sizes of which are 1*M and >1*N, respectively. We have known that there is at most one common >element in both vectors. I am looking for the quick algorithm to >search this common element. If the arrays are sortable, you could sort V1 and V2 in O(n lg(n) + m lg(m)) time and once thats complete, compare the two sorted arrays sequentially, moving forward one step at a time, so O(n + m) steps for comparison once the array is sorted. >The general algorithm is to compare every element in V1 with each >element in V2. the comparison complexity will be O(M*N). Is there any >efficient method to complete it? >I hope it can be done in FPGA. If M=N=60, and each element is 20 bit >long,there isn't enough pins for the general search algorithms at one >time. It need some loops to do it. So I am looking for an efficient >algorithm and expect that the common element can be found in around >10ns~50ns. Is it possible? Systolic. The brute force comparison is O(M*N) in TIME * SPACE. Thus if you have 1 comparison cell, it takes O(M*N) time. But if you have N comparison cells, each holding one of the element, it takes O(M) time and O(N) FPGA resources. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 59151
> I hope it can be done in FPGA. If M=N=60, and each element is 20 bit > long,there isn't enough pins for the general search algorithms at one > time. Whether an algorithm is efficient or not, you will still need to feed every single element in the vectors to the FPGA. I don't understand why algorithms have anything to with FPGA not having enough pins. Jim Wu jimwu88NOOOSPAM@yahoo.comArticle: 59152
I need to program an ATF1502AS device with some very simple logic. What can people suggest that would be the simplest and cheapest way to do this? Thanks. Rog.Article: 59153
"Lorenzo Lutti" wrote: > If you really are for economic prosperity everywhere, you must accept > the fact that when the cake needs to be split in more parts, the slices > are smaller. So those who ate almost all of the cake in the past, now > will have less to eat. It's hard to discuss the topic when these sorts of arguments are presented. I think I rather jot this one down as a mistake --something I should have not posted in the newsgroup. For that I apologize. If someone has the genuine ability to engage in a discussion (on adult terms) as to the effect that the "offshore revolution" will have on technology, markets, product development, IP, manufacturing, the FPGA world, etc. I, of course, welcome it. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 59154
"John Bowen" <johnboy@cafes.net> wrote in message news:3f36447d@news.isdn.net... > I've had several courses on Digital Logic, ......but that was in the early > 1980s !! I was very familiar with the 7400 series of integrated circuits, > and could name the gates and truth tables off the top of my head. A lot of > years have passed since I worked with these chips, and I've fallen way > behind in technology. But now I'd like to do some experimenting on my own. > I wanted to build something like a simple Annunciator Panel type project, > so I dug out my old logic books to brush up. What I found out was that I > needed about 50-75 Logic Gates for my particular design, though I'm sure I > could pare that down some, but the thought of mounting and wiring (I used > to wire-wrap a lot) about 25 or more Integrated Circuits just kind of > discouraged me. I was asking a fellow Technician about maybe using some sort > of EEProm, and he told me about Field Programmable Gate Arrays...according > to what I've since learned, it looks like I should be able to program a FPGA > with my logic design(or reprogram it if I make a mistake)....my logic would > be a series of And, Nor, etc. gates, Flip Flops, etc, and use contact > closures for inputs and LEDs for outputs. Am I correct in my interpretation > of what a FPGA is, and how it operates? > I was looking at 10 inputs (contact closures) and 10 simple LEDs for the > outputs on this first project. Since I'm not familiar with the pin > assignments for the I/Os, and what's needed to program these FPGAs, would > any of you have a recommendation on what family and size of FPGA I should > start with? Or is an FPGA really what I need? What about a programmer (or > programming method) and software? I'd be most comfortable using a software > that graphically displays my gates and their connections if there is such a > thing, but since this is just going to be a playtoy for now, I guess cost > needs to be a consideration, so inexpensive developmental would be best. Is > there a Complete Experimenter's Kit available for someone with my interests? > Or would I be better off buying individual components to suit my needs? > I've read some of the posts, and it sounds like you guys are WAAAY up on > the curve....can you help me get started? > Thanks, John. Have a look at CPLD's You could probably a $0.99 Xilinx 9532XL to do this. A Jtag programer is about $10, and the webpack software is free from www.xilinx.com, I think you can get them in PLCC so with a suitable socket you and wirewrap it. There are also kits available with the chip on a PCB and a programming cable. You can use a schematic layout or a HDL like verilog. RalphArticle: 59155
"Martin Euredjian" <0_0_0_0_@pacbell.net> ha scritto nel messaggio news:TGyZa.7$%y7.873641@newssvr14.news.prodigy.com... > > If you really are for economic prosperity everywhere, > > you must accept > > the fact that when the cake needs to be split in more > > parts, the slices > > are smaller. So those who ate almost all of the cake in > > the past, now > > will have less to eat. > > It's hard to discuss the topic when these sorts of > arguments are presented. I was deadly serious, and the concept, though very simple, is also very hard to confute. When you have a working force ten times bigger, that works more hours a day for (a lot) less money, how can you think to compete? In my opinion, the real childish attitude is to blame the piracy rate. Some big countries are growing (at least) ten times faster than the "rich" ones. While in the beginning it was simple for the multinationals to slave entire villages of mid-east asians for making shoes at 30 cents/hour, now (luckily, I might add) their demands are growing. It is still a great deal for multinationals, but the margin is smaller, and someone has to pay. In a smaller scale, there is the same "problem" here in Europe: countries like Germany, France or Italy move more and more frequently the production to east-european countries (Poland, Bulgary and so on), because it costs a lot less. We are just at the point the USA were in the mid-eighties: only the "easy" production (not engineering or other "creative" activities) is moved offshore. But engineering is just the next step. All men are equally smart, if they get an appropriate instruction. By the way: I'm not a supporter of globalization, at least of the kind of globalization we have seen in the last 20 years. This "conquistadores" way of globalizing will become a boomerang for the big corporations. And for us, of course. > If someone has the genuine ability to engage in a > discussion (on adult > terms) as to the effect that the "offshore revolution" > will have on > technology, markets, product development, IP, > manufacturing, the FPGA world, I think there won't be any technical change, the only effect will be the change of economic barycentre. -- LorenzoArticle: 59156
Thanks for the help Bob. I think I know what I have to do. Cheers, Michael. "Bob" <nimby1_not_spmmm@earthlink.net> wrote in message news:xc9Za.1457$Nf3.400@newsread4.news.pas.earthlink.net... > Michael, > > There are two basic ways that DLL's are used to de-skew clocks. For lack of > any other names, they are: > > 1) internal de-skew > 2) external de-skew > > Internal de-skew means that the global clock net, within the FPGA, > transitions at the same time (phase) that the FPGA's input clock > transitions. > > External de-skew means that a clock at an FPGA output pin transitions at the > same time (phase) that the FPGA's input clock transitions. > > Here are some terms you should know: > > IBUF/OBUF -- an FPGA input/output pin (what most of the FPGA pins are). > IBUFG -- really just a standard I/O pin, but physically close to the DLL -- > such that the DLL knows what its routing delay is to it. These are where > clock inputs (and external clock feedback signals) are supposed to connect > to. > DLL -- the phase detector, etc... > BUFG -- a global clock buffer. The output of the BUFG's are the global clock > nets. > > With internal de-skew, the output of the BUFG (global clock net) is fed > directly back to the DLL's clock feedback input -- with the FPGA itself. > With external de-skew, the output of the BUFG feeds an OBUF (output pin). > Then, a trace on your circuit board connects that OBUF to an IBUFG. > > With a synchronous RAM design (like your DDR project), the idea is to first > get a clock to the RAM that has the same phase as one of the FPGA's internal > global clock nets. This is so that the timing of the RAM read data, at the > FPGA IBUF's, has a known time relationship. One of the DLL's in the design > is used to do this -- via external de-skew. > > The other DLL is used (via internal de-skew) to create the "read RAM data" > clock. > > I haven't looked at XAPP200 carefully, but here's how we do our DDR > controllers: > > 1) Use external de-skew to create the RAM's CLK/CLKB, and DQS clocks. Note > that the DQS clocks (strobes) are tristated during RAM reads, and are not > used during RAM reads. Additionally, this DLL's 90deg output is used to feed > the OBUF's that create the RAM DQ lines -- but only for RAM writes. > > 2) Use internal de-skew to create a separate clock net for RAM reads (and > other FPGA functions). > > Having said all this, I must say that it's amazing to me that a Virtex-E > device can be used for this type of application. I say this because the data > from the RAM is valid during the time "between" the RAM's DQS clock (strobe) > edges. So, when the RAM read data gets back to the FPGA pins, its valid data > position is not ideal (i.e., suitable setup and hold time). It is much > easier to use a Virtex-II device, wherein a third internal de-skew clock net > can be generated (which has phase shift via the DCM) in order to properly > capture the RAM read data. > > Either way, you'll learn a lot with this project. > > Regards, > Bob > > > "Michael Chan" <s354025@student.uq.edu.au> wrote in message > news:bh2scl$kop$1@bunyip.cc.uq.edu.au... > > Hi, > > > > I'm working on a University project that requires ddr-ram interfaced to a > > Vertex-EM device. I am basing my design off xapp200 from xilinx. The > > design uses DLLs to deskew the system clock and ddr-ram clock. The signal > > fed back to the DLLs (sys_clk_fb) is apparently the ddr clk. What I don't > > understand is where I take this signal from. Should I have tracks on my > PCB > > comming back from the ddr-ram chips to inputs on the fpga? Or can the > > feedback signal come from inside the fpga? > > > > I am a little lost as to how the DLLs manage to sychronise the two clocks. > > Any help would be appreciated. > > > > Thanks. > > > > Michael. > > > > > >Article: 59157
Hi I am venkat...i am working on FPGA adv 5.3 which has modelsim 5.4-5.6 and LS 2001 version....my design uses Block Ram so i need to use unisim library ....i couldnt add Unisim library to design browser settings...i have added it by means of options --> vhdl--> packages--> shall i have to compile it before simulation i am getting only "uuuuuuuu" as outputs.....i am new to this FPGAadv5.3 pls help me venki ..Article: 59158
"Roger" <rogerwilson@hotmail.com> wrote in message news:<F2wZa.479 > I need to program an ATF1502AS device with some very simple logic. What can > people suggest that would be the simplest and cheapest way to do this? should be all free tools (ASFAIK) 1 Atmel IDS 2 SVF2JAM 3 JAM Player that should do from design fitting to programming anttiArticle: 59159
"Subroto Datta" <sdatta@altera.com> ha scritto nel messaggio news:ca4d800d.0308081334.169fbc89@posting.google.com... > Hi Andrea, > > The clock enable is not supported by the single-port RAM megafunction. > An easy work-around is to use the dual-port megafunction (via the > MegaWizard "memory compiler/RAM: 2-port" or the older > "storage/lpm_ram_dp+"). You can always tie the rdaddress and > wraddress together to get single-port RM behavior. > > - Subroto Datta > Altera Corp. Thank you!!! Which is the difference between "memory compiler/RAM: 2-port and" and "storage/lpm_ram_dp+"? AndreaArticle: 59160
yes, I am aware of other advantages of running W2K, but the major disadvatage is that this also implies buying a new PC and using a lot of time installing all current programs again. If possible, I want to stick to NT until I've got time to install a new OS (which probably means that I will run NT as long as I work here :-)). Although it is not supported, I installed WebPack 5.2i under NT and the example program (traffic light) runs fine. Does anybody foresee where the problems may rise? Thanks, Aart Rob Judd wrote: > > Aart van Beuzekom wrote: > > > > Hei, > > > > I will start developing FPGA applications with WebPack. My problem is > > that my OS is WinNT, which is not supported by WebPack 5.2i. I've got a > > CD laying round here with WebPack version 4.2WP0.0. > > > > Can anybody tell me if the advantages of v. 5.2i are so much that > > upgrading to Win2000 really is necessary? > > > > My application will run on a Spartan-II device. Clock speed wil not be > > an issue, but efficient use of logic cells might be. > > I can tell you why I upgraded from NT to W2K ... no support for USB. > > RobArticle: 59161
"Aart van Beuzekom" <aart@westcontrol.com> wrote in message news:3F374368.2FADD7D0@westcontrol.com... > yes, I am aware of other advantages of running W2K, but the major > disadvatage is that this also implies buying a new PC and using a lot of > time installing all current programs again. If possible, I want to stick > to NT until I've got time to install a new OS (which probably means that > I will run NT as long as I work here :-)). > > Although it is not supported, I installed WebPack 5.2i under NT and the > example program (traffic light) runs fine. Does anybody foresee where > the problems may rise? > At a guess I think you should be fine except for impact via a parallel cable. RalphArticle: 59162
Hi, Thank you for your help, but I can't synthesize the modified code yet, Which synthesis tool you used to syntheseze the modified code? Thank you, - Saeed antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0307280238.27f59250@posting.google.com>... > "Saeed Nari" <saeed@ce.sharif.edu> wrote in message news:<bfr0ni$oa7$1@balder.stud.idb.hist.no>... > > Hi, VHDL friends > > Does anyone have a synthesizable gl85, or i8085 VHDL > > design? I have them, but can't synthesize with leonardo or synopsis. > > Please reply to this address. Thank you a lot! > > the original from hamburg vhdl is probably not fully working at > least there is one modified version that claims severl problems > beeing fixed > > this modified version synthesis OK, see below: > ----------- > Writing NGDBUILD log file "i8085_c.bld"... > NGDBUILD done. > Completed process "Translate". > Started process "Map". > > Using target part "2vp7ff672-6". > Removing unused or disabled logic... > Running cover... > Running directed packing... > Running delay-based LUT packing... > Running related packing... > > Design Summary: > Number of errors: 0 > Number of warnings: 1 > Logic Utilization: > Number of Slice Flip Flops: 317 out of 9,856 3% > Number of 4 input LUTs: 3,614 out of 9,856 36% > Logic Distribution: > Number of occupied Slices: 1,876 out of 4,928 38% > Number of Slices containing only related logic: 1,876 out of 1,876 100% > Number of Slices containing unrelated logic: 0 out of 1,876 0% > *See NOTES below for an explanation of the effects of unrelated logic > Total Number 4 input LUTs: 3,622 out of 9,856 36% > Number used as logic: 3,614 > Number used as a route-thru: 8 > > Number of bonded IOBs: 45 out of 396 11% > IOB Flip Flops: 18 > Number of GCLKs: 3 out of 16 18% > > Total equivalent gate count for design: 25,801 > Additional JTAG gate count for IOBs: 2,160 > ---------------- > > http://simlab.eecs.tufts.edu/simlab/html/8085_mod.html > > the report was for code downloaded from above link > > anttiArticle: 59163
Hi all,
I am thinking of using a VirtexII or VirtexIIPro FPGA for a new
project. I am quite familiar with the DLLs from the previous Xilinx
FPGA-families, but the DCM is new to me. I just put an older project
of mine into a xcv2p4-5 and part of the TRCE-report resulting from
that (concerning an OFFSET OUT BEFORE and an OFFSET IN AFTER
constraint) I put at the end of this post.
My question is concerning the Tdcmino parameter. I know why it is
negative now from a previous post, but why is it not constant in one
and the same TRCE report for one and the same DCM??? Same question for
all the other numbers in the clock path (Tiopi delay, net delay from
the IBUFG to the DCM input, BUFGMUX)
In the first constraint it says :
* Tiopi = 0.909
* net delay = 0.307
* Tdcmino = -3.691
...
In the second :
* Tiopi = 0.728
* net delay = 0.246
* Tdcmino = -3.993
...
Because of the negative DCM-delay I will need to phase-shift the
internal clk for my application, so I get the behaviour as in the
standalone DLLs from e.g. VirtexE (meaning the delay from GCLK-input
pad to IOB-flipflops is as good as zero). In order to do this right I
need to have an idea of the real clk-delay through the whole path.
btw : I use ISE5.2 SP3 with VirtexIIPro speedfiles version = ADVANCED
1.78 2003-05-08
Any thoughts on this ?
Thanks,
Bart
================================================================================
Timing constraint: COMP "sdr_dq_green<3>" OFFSET = OUT 2.500 nS
BEFORE COMP "sdr_clk" ;
2 items analyzed, 0 timing errors detected.
Maximum allowable offset is 5.242ns.
--------------------------------------------------------------------------------
Slack: 2.742ns (requirement - (clock arrival + clock
path + data path))
Source: sdr_clk (PAD)
Destination: sdr_dq_green<3> (PAD)
Source Clock: fpga_clk rising at 0.000ns
Requirement: 5.019ns
Data Path Delay: 2.623ns (Levels of Logic = 0)
Clock Path Delay: -0.346ns (Levels of Logic = 3)
Clock Path: sdr_clk to i_sdr_ctlr_u_data_path_sdr_green_o_3
Location Delay type Delay(ns) Physical
Resource
Logical
Resource(s)
-------------------------------------------------
-------------------
B13.I Tiopi 0.909 sdr_clk
sdr_clk
i_clk_dlls_sdram_ibufg_sys_clk
DCM_X1Y1.CLKIN net (fanout=1) 0.307
i_clk_dlls_sdram_sys_clk
DCM_X1Y1.CLK0 Tdcmino -3.691
i_clk_dlls_sdram_dll_int
i_clk_dlls_sdram_dll_int
BUFGMUX7P.I0 net (fanout=1) 0.769
i_clk_dlls_sdram_fpga_clk_out_o
BUFGMUX7P.O Tgi0o 0.064
i_clk_dlls_sdram_bufg_clk_out
i_clk_dlls_sdram_bufg_clk_out.GCLKMUX
i_clk_dlls_sdram_bufg_clk_out
J3.OTCLK1 net (fanout=611) 1.296 fpga_clk
-------------------------------------------------
---------------------------
Total -0.346ns (-2.718ns
logic, 2.372ns route)
Data Path: i_sdr_ctlr_u_data_path_sdr_green_o_3 to sdr_dq_green<3>
Location Delay type Delay(ns) Physical
Resource
Logical
Resource(s)
-------------------------------------------------
-------------------
J3.PAD Tiockp 2.623 sdr_dq_green<3>
i_sdr_ctlr_u_data_path_sdr_green_o_3
i_sdr_ctlr_u_data_path_sdr_dq_io32/OBUFT
sdr_dq_green<3>
-------------------------------------------------
---------------------------
Total 2.623ns (2.623ns logic,
0.000ns route)
(100.0% logic,
0.0% route)
================================================================================
Timing constraint: COMP "sdr_dq_green<3>" OFFSET = IN 5.770 nS AFTER
COMP "sdr_clk" ;
1 item analyzed, 1 timing error detected.
Maximum allowable offset is 5.370ns.
--------------------------------------------------------------------------------
Slack: -0.400ns (requirement - (data path - clock
path - clock arrival))
Source: sdr_dq_green<3> (PAD)
Destination: i_sdr_ctlr_u_data_path_u_data_green_o_3 (FF)
Destination Clock: fpga_clk rising at 0.000ns
Requirement: 1.749ns
Data Path Delay: 0.901ns (Levels of Logic = 0)
Clock Path Delay: -1.248ns (Levels of Logic = 3)
Data Path: sdr_dq_green<3> to
i_sdr_ctlr_u_data_path_u_data_green_o_3
Location Delay type Delay(ns) Physical
Resource
Logical
Resource(s)
-------------------------------------------------
-------------------
J3.ICLK1 Tiopick 0.901 sdr_dq_green<3>
sdr_dq_green<3>
i_sdr_ctlr_u_data_path_sdr_dq_io32/IBUF
i_sdr_ctlr_u_data_path_u_data_green_o_3
-------------------------------------------------
---------------------------
Total 0.901ns (0.901ns logic,
0.000ns route)
(100.0% logic,
0.0% route)
Clock Path: sdr_clk to i_sdr_ctlr_u_data_path_u_data_green_o_3
Location Delay type Delay(ns) Physical
Resource
Logical
Resource(s)
-------------------------------------------------
-------------------
B13.I Tiopi 0.728 sdr_clk
sdr_clk
i_clk_dlls_sdram_ibufg_sys_clk
DCM_X1Y1.CLKIN net (fanout=1) 0.246
i_clk_dlls_sdram_sys_clk
DCM_X1Y1.CLK0 Tdcmino -3.993
i_clk_dlls_sdram_dll_int
i_clk_dlls_sdram_dll_int
BUFGMUX7P.I0 net (fanout=1) 0.615
i_clk_dlls_sdram_fpga_clk_out_o
BUFGMUX7P.O Tgi0o 0.054
i_clk_dlls_sdram_bufg_clk_out
i_clk_dlls_sdram_bufg_clk_out.GCLKMUX
i_clk_dlls_sdram_bufg_clk_out
J3.ICLK1 net (fanout=611) 1.102 fpga_clk
-------------------------------------------------
---------------------------
Total -1.248ns (-3.211ns
logic, 1.963ns route)
--------------------------------------------------------------------------------
Article: 59164Of course you have to compile it. If you look into the Mentor Support Net you will find a note how to do this. For Compilation look to the Xilinx Website : http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=2561 PeterArticle: 59165
Hi Aart, At the risk of getting a little off topic for this group... I've installed W2K over my NT installation on a few machines and was pleasantly surprised to find that it installed perfectly. Only a few system utilities (norton, etc.) needed to be reinstalled. If I recall correctly, there is even an uninstall feature that will return your box back to NT if things don't work out as planned. As far as system power goes, W2K wasn't much more of a hog than NT4, except for memory, which costs asymptotically close to $0 these days and is quite handy for FPGA compiling anyways. And W2K allowed me to play all the games I wanted to... only at home, of course ;-) Regards, Paul Leventis Altera Corp. "Aart van Beuzekom" <aart@westcontrol.com> wrote in message news:3F374368.2FADD7D0@westcontrol.com... > yes, I am aware of other advantages of running W2K, but the major > disadvatage is that this also implies buying a new PC and using a lot of > time installing all current programs again. If possible, I want to stick > to NT until I've got time to install a new OS (which probably means that > I will run NT as long as I work here :-)). > > Although it is not supported, I installed WebPack 5.2i under NT and the > example program (traffic light) runs fine. Does anybody foresee where > the problems may rise? > > Thanks, > > Aart > > Rob Judd wrote: > > > > Aart van Beuzekom wrote: > > > > > > Hei, > > > > > > I will start developing FPGA applications with WebPack. My problem is > > > that my OS is WinNT, which is not supported by WebPack 5.2i. I've got a > > > CD laying round here with WebPack version 4.2WP0.0. > > > > > > Can anybody tell me if the advantages of v. 5.2i are so much that > > > upgrading to Win2000 really is necessary? > > > > > > My application will run on a Spartan-II device. Clock speed wil not be > > > an issue, but efficient use of logic cells might be. > > > > I can tell you why I upgraded from NT to W2K ... no support for USB. > > > > RobArticle: 59166
FWIW, I just upgraded my computer from WinNT to Win2K several days ago. The upgrade went smoothly (took less than an hour) and it kept all my NT settings (registry, user database, etc). I didn't have to re-install programs that were already on WinNT. I use dual boot (Redhat Linux + Windows) on my machine and I was very surprised that the upgrade didn't even screw up the Linux LILO program in the boot sector. One thing I'd like to point out though, Win2K seems to have much bigger footprint than NT. It should not be a problem if you have a big hard drive. Jim Wu jimwu88NOOOSPAM@yahoo.com Aart van Beuzekom <aart@westcontrol.com> wrote in message news:<3F374368.2FADD7D0@westcontrol.com>... > yes, I am aware of other advantages of running W2K, but the major > disadvatage is that this also implies buying a new PC and using a lot of > time installing all current programs again. If possible, I want to stick > to NT until I've got time to install a new OS (which probably means that > I will run NT as long as I work here :-)). > > Although it is not supported, I installed WebPack 5.2i under NT and the > example program (traffic light) runs fine. Does anybody foresee where > the problems may rise? > > Thanks, > > Aart > > Rob Judd wrote: > > > > Aart van Beuzekom wrote: > > > > > > Hei, > > > > > > I will start developing FPGA applications with WebPack. My problem is > > > that my OS is WinNT, which is not supported by WebPack 5.2i. I've got a > > > CD laying round here with WebPack version 4.2WP0.0. > > > > > > Can anybody tell me if the advantages of v. 5.2i are so much that > > > upgrading to Win2000 really is necessary? > > > > > > My application will run on a Spartan-II device. Clock speed wil not be > > > an issue, but efficient use of logic cells might be. > > > > I can tell you why I upgraded from NT to W2K ... no support for USB. > > > > RobArticle: 59167
Probably stupid question (sorry), but I cannot figure out an answer: Xilinx devices has optional delay element in IOB which causes (when used) that pad-to-pad hold time is zero. Maybe someone could explain me, how to understand this pad-to-pad hold time, and when I should use this optional delay element? Why does it only affects pad-to-pad hold time and not for example pad-register in CLB hold time? Is it because registers in CLBs have significantly shorter hold times? Thanks! -- Robert P.Article: 59168
Following link shows 2001 support on 5.1i ISE and later.
http://toolbox.xilinx.com/docsan/xilinx5/data/docs/xst/xst0083_11.html
This information is extracted from the ISE software manual guide.
http://toolbox.xilinx.com/docsan/xilinx5/manuals.htm
Regards, Wei
===========================================================
Verilog 2001 Support in XST
XST now supports the following Verilog 2001 features. For details on
Verilog 2001, see Verilog-2001: A Guide to the New Features by Stuart
Sutherland, or IEEE Standard Verilog Hardware Description Language
manual, (IEEE Standard 1364-2001).
* Combined port/data type declarations
* ANSI-style port lists
* Module parameter port lists
* ANSI C style task/function declarations
* Comma separated sensitivity list
* Combinatorial logic sensitivity
* Default nets with continuous assigns
* Disable default net declarations
* Arrays of net data types
* Signed reg, net, and port declarations
* Signed based integer numbers
* Signed arithmetic expressions
* Arithmetic shift operators
* Automatic width extension past 32 bits
* Power operator
* n sized parameters
* Explicit in-line parameter passing
* Fixed local parameters
* Enhanced conditional compilation
* File and line compiler directives
=============================================================
dont_reply wrote:
> Does Xilinx Webpack ISE support RTL-synthesis of Verilog-2001? If so, what
> was the first version to support it? I'm mainly looking at support for
> 'signed' number support.
> (Signed regs, wires, inputs/outputs, and '>>>')
>
>
Article: 59169Confluence is a functional programming language for digital logic design (FPGA/ASIC), real-time embedded software development, and DSP modeling. Confluence source code compiles into Verilog, VHDL, C, and Python for synthesis, implementation, and verification. The release of Confluence 0.6 features many language and compiler improvements including simplified syntax, static connection analysis, and increased debugging visibility. Also in the release is a new unit testing framework for assertion based verification of Confluence programs and output code (HDL/C/Python). Test suites, packaged in the distribution, use the framework to verify the Confluence standard libraries and output code generators. Release Notes, Documentation, and Download: http://www.launchbird.com/download.html Online Compiler: http://www.launchbird.com/cgi-bin/compiler.py Confluence Mailing Lists: http://www.launchbird.com/mailinglists.html -- Tom Hawkins Launchbird Design Systems, Inc. 952-200-3790 tom1@launchbird.com http://www.launchbird.com/Article: 59170
I highly recommend the section on Eliminating Clock Skew in XAPP462: Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs. The section begins on the bottom of page 25. http://www.xilinx.com/xapp/xapp462.pdf Although the application note is written for Spartan-3 FPGAs, the DCM is functionally very similar to Virtex-II and Virtex-II Pro. The differences are also described in the application note. --------------------------------- Steven K. Knapp Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Michael Chan" <s354025@student.uq.edu.au> wrote in message news:bh2scl$kop$1@bunyip.cc.uq.edu.au... > Hi, > > I'm working on a University project that requires ddr-ram interfaced to a > Vertex-EM device. I am basing my design off xapp200 from xilinx. The > design uses DLLs to deskew the system clock and ddr-ram clock. The signal > fed back to the DLLs (sys_clk_fb) is apparently the ddr clk. What I don't > understand is where I take this signal from. Should I have tracks on my PCB > comming back from the ddr-ram chips to inputs on the fpga? Or can the > feedback signal come from inside the fpga? > > I am a little lost as to how the DLLs manage to sychronise the two clocks. > Any help would be appreciated. > > Thanks. > > Michael. > >Article: 59171
Hi I am looking to buy or design a vme board that can control the bus as a master and slave. The idea is to use a host pc to send a few commands to the board which will contain an FPGA. The board will then become a master and send these commands to other boards in the vme system. The idea is that this method will be quick at sending commands to boards to aid system syncronisation. So does anyone know of any vme boards that have an FPGA onboard or if I must make my own board up, sutible FPGA cores that I could use to interface to the bus. Cheers Craig removethisbitccward@qinetiq.comArticle: 59172
Aare Tali <atali@cygrp.com> wrote: : I would expect it to fit. Anything you can do in 2 logic blocks of : 36V18 can be done in two 54V18. : I would suggest to place the design into 9536 without XL, save the : fitter report, run the fitter on 9536XL and compare fitter reports. The big difference is that the XC9536 report has the 'wire-AND' option enabled and the XC9536XL has it disabled. My design makes heavy use of the 'wire-AND' facility, and it has been suggested that this is not available on the XC9536XL. Is that correct ? I have raised a Webcase on this issue, but no results so far. Richard. http://www.rtrussell.co.uk/Article: 59173
John, have a look at this: http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "John Bowen" <johnboy@cafes.net> wrote in message news:3f36447d@news.isdn.net... > I've had several courses on Digital Logic, ......but that was in the early > 1980s !! I was very familiar with the 7400 series of integrated circuits, > and could name the gates and truth tables off the top of my head. A lot of > years have passed since I worked with these chips, and I've fallen way > behind in technology. But now I'd like to do some experimenting on my own. > I wanted to build something like a simple Annunciator Panel type project, > so I dug out my old logic books to brush up. What I found out was that I > needed about 50-75 Logic Gates for my particular design, though I'm sure I > could pare that down some, but the thought of mounting and wiring (I used > to wire-wrap a lot) about 25 or more Integrated Circuits just kind of > discouraged me. I was asking a fellow Technician about maybe using some sort > of EEProm, and he told me about Field Programmable Gate Arrays...according > to what I've since learned, it looks like I should be able to program a FPGA > with my logic design(or reprogram it if I make a mistake)....my logic would > be a series of And, Nor, etc. gates, Flip Flops, etc, and use contact > closures for inputs and LEDs for outputs. Am I correct in my interpretation > of what a FPGA is, and how it operates? > I was looking at 10 inputs (contact closures) and 10 simple LEDs for the > outputs on this first project. Since I'm not familiar with the pin > assignments for the I/Os, and what's needed to program these FPGAs, would > any of you have a recommendation on what family and size of FPGA I should > start with? Or is an FPGA really what I need? What about a programmer (or > programming method) and software? I'd be most comfortable using a software > that graphically displays my gates and their connections if there is such a > thing, but since this is just going to be a playtoy for now, I guess cost > needs to be a consideration, so inexpensive developmental would be best. Is > there a Complete Experimenter's Kit available for someone with my interests? > Or would I be better off buying individual components to suit my needs? > I've read some of the posts, and it sounds like you guys are WAAAY up on > the curve....can you help me get started? > Thanks, John. > >Article: 59174
Paul Leventis wrote: > Hi Aart, > > At the risk of getting a little off topic for this group... I've installed > W2K over my NT installation on a few machines and was pleasantly surprised > to find that it installed perfectly. Only a few system utilities (norton, > etc.) needed to be reinstalled. If I recall correctly, there is even an > uninstall feature that will return your box back to NT if things don't work > out as planned. As far as system power goes, W2K wasn't much more of a hog > than NT4, except for memory, which costs asymptotically close to $0 these > days and is quite handy for FPGA compiling anyways. > > And W2K allowed me to play all the games I wanted to... only at home, of > course ;-) I am not generally a Windows user, but when forced by circumstances, I find that NT is a bit moldy, Windows 2000 is OK, and XP is spooky. I would suggest upgrading to Windows 2000 while (if!) you can still get it, then stay away from XP in perpetuity. (I have serious privacy issues with XP. Besides the anecdotal cases of automatic updates silently breaking working systems, the data that is sent over the network is mananged by an organization that has no oversight, a history of abuse, and intent on installing on *your* computer whatever trojans^H^H^H^Hsoftware it sees fit to install.) And this is applicable to this newgroups how? Simple, we would all be much happier if all the vendors would support Linux. The FPGA backend tools are the last holdout. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
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