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"Luiz Carlos" <oen_br@yahoo.com.br> wrote in message news:8471ba54.0309040255.3d79ed94@posting.google.com... > Metastability occurs when we don't respect setup and/or hold times. > But what does happen when the input for the flip-flop is a DC signal > between Vil and Vih? (Or it changes so slowly that looks like a > constant.) > > My guess is there is a voltage, let's say Vth, that: > If Vin < Vth => DOUT = 0 after a delay > If Vin > Vth => DOUT = 1 after a delay > The delay grows as Vin approximates to Vth. > > Am I right? > > Luiz Carlos Hi Luiz, You're right. Things could even be worse: in cmos technology, applying a voltage around Vt at an input consisting of 2 complementary transistors will cause both fets to conduct, resulting in local excessive power dissipation. Depending on the exact design of the input, this may even lead to permanent damage. Assuming that you're using a modern fpga, this is most likely solved by the manufacturer by using an input with hysteresis. As a counter example: I've seen diagrams where a 4000 (or 74HC00) is used as voltage controlled sine oscillator. Regards, Alvin.Article: 60051
we configue apex20k with ppa scheme,the signal nSTATUS came to low when we have sent about 300bytes data,how this phenomena come out? the problem of software or hardware?Article: 60052
arkaitz wrote: > Hi, > > I'm trying to connect a user peripheral to the Microblaze OPB bus. I > have done all as mentioned in the "User Core Template for OPB (Slave > Services Package 0) but without success. > > I have added some code lines in the correponding places to match the > IPIF to my user_core. > > I have routed the Bus2IP_CS, Bus2IP_WrCE and Bus2IP_RdCE to some user > leds in my development board and I haven't noticed any effect, so I > imagine that I'm not accesing to my peripheral. If you are attaching LEDs on these signals you will not see anything (maybe with an osilloscope) these signals are active only for an OPB bus transaction which will match your C_BASEADDRESS, depending on your OPB_Ack latency (transaction acknoledge) this will keep from 2 to 16 OPB_Clk periods so you need a very good eye to see a ~1 us blink. (assuming 100Mhz OPB_Clk) Aurash > > > I have also checked the BASEADDR and the HIGHADDR and I think they're > correct. > > Here you are part of my MPD file > > PARAMETER c_baseaddr = 0xFFFFFFFF, DT = std_logic_vector, MIN_SIZE > = 0xFF > PARAMETER c_highaddr = 0x00000000, DT = std_logic_vector > PARAMETER c_mir_baseaddr = 0xFFFFFFFF, DT = std_logic_vector, MIN_SIZE > = 0xFF > PARAMETER c_mir_highaddr = 0x00000000, DT = std_logic_vector > PARAMETER c_user_id_code = 3, DT = integer > PARAMETER c_include_mir = 0, DT = integer > PARAMETER c_opb_awidth = 32, DT = integer > PARAMETER c_opb_dwidth = 32, DT = integer > PARAMETER c_family = virtex2, DT = string > > Note that I actualize "c_baseaddr" and "c_highaddr" parameters on the > component as well as the "c_mir_baseaddr" and "c_mir_highaddr". > > I'd be very grateful if someone could help me. > > Thanks. > > Arkaitz. -- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324Article: 60053
Luiz, We have done this, and it works. The question is how well? The answer is that we have never actually used this in a system where other things are going on as well, and then measured the S/N of the ADC, resolution, THD, etc. Let us know how it turns out. Better than using Vref and the input would be to use an LVDS input buffer (as was already pointed out) differentially. You will only get a good 1V to 1.5V span (where the comparator works the fastest and best), but the differential input leads to less noise. Austin Luiz Carlos wrote: > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F55FE76.532A72CE@xilinx.com>... > > Luiz, > > > > Last things first, the LVTTL input does not use the comparator(s) (there are > > three different comparators, as well as other ciruits for the various input > > standards). > > > > The comparator is designed to have a relatively high gain, so that it > > switches quickly. > > > > As I said, the offset voltage is due to the Vt mismatch on the pmos and nmos > > diff pairs, and since these are built with .35u (VII) or .25u (VII Pro) > > transistors, they are pretty darn fast diff-amps. There is a classic gain > > stage after the cmos diff-amp (similar to the ones in "CMOS Circuit Design, > > Layout & Simulation" by Baker, Li, and Boyce). The offset voltage is > > typically less than a few 10's of mV (say 10 to 20 mV worst case). I am sure > > that if you vary the voltage difference slowly enough, you could measure the > > gain of the diff-amp. It was designed for HSTL and SSTL IO standards, which > > as someone already pointed out, are pretty sloppy. What I will point out > > here, is that I am not aware of any monolithic separate comparator that is as > > fast as the one that is in the input circuit. This comparator is good for > > 400 Mbs+ speeds, which is a lot faster than most separate IC comparators.... > > > > Austin > > Thankyou Austin. > > I'm thinking of using this internal comparator for a Delta-Sigma ADC. > > Luiz Carlos.Article: 60054
Thomas, The DLL can not be used to extract clock, as the output is just the input, delayed. In Spartan 3 there are "hidden" modes in the DCM that allow us to experiment with things like CDR, so you will have to wait until we have fully characterized the capabilities, and decided if they work well enough to market and support. The exciting thing about the DCM and all of its capabilities is that we can see our way to an all digital DSP implementation of a PLL -- without any of the negatives of a PLL. Including jitter attenuation (something not done in today's DCM). If you are interested in using the S3 unsupported modes, you would have to work through your factory or disti FAE with us. Another option is to oversample the 100Mbs with the MGTs in Virtex II Pro. And finally, there are other designs using logic alone to recover the datastream of such a low bit rate stream in any of the Virtex family FPGAs (Xapp250, Xapp224). Austin Thomas wrote: > Hello, > has anyone already used a Spartan IIe DLL (PLL) to extract the clock > out of a 100MBit/s 8B10B encoded data stream ? > > Will that work with a Spartan III DCM? > > Thank you, > ThomasArticle: 60055
Alvin, One common mis-conception is that you can "hurt" or damage the FPGA by having the input voltage float at exactly the wrong point. Un-true: the IOBs are designed with sufficient metal and device contacts to remain in contention forever without damage. The ~500 uA of contention is hardly noticeable in the overall scheme of things. So, don't let inputs float (bad practice) but don't stress about it, as no damage will result in our FPGA input structures. If you think about it, how can we offer LVDS, HSTL, SSTL, GTL, LVCMOS all on the same pin without taking this into account? Austin Alvin Andries wrote: > "Luiz Carlos" <oen_br@yahoo.com.br> wrote in message > news:8471ba54.0309040255.3d79ed94@posting.google.com... > > Metastability occurs when we don't respect setup and/or hold times. > > But what does happen when the input for the flip-flop is a DC signal > > between Vil and Vih? (Or it changes so slowly that looks like a > > constant.) > > > > My guess is there is a voltage, let's say Vth, that: > > If Vin < Vth => DOUT = 0 after a delay > > If Vin > Vth => DOUT = 1 after a delay > > The delay grows as Vin approximates to Vth. > > > > Am I right? > > > > Luiz Carlos > > Hi Luiz, > > You're right. > > Things could even be worse: in cmos technology, applying a voltage around Vt > at an input consisting of 2 complementary transistors will cause both fets > to conduct, resulting in local excessive power dissipation. Depending on the > exact design of the input, this may even lead to permanent damage. Assuming > that you're using a modern fpga, this is most likely solved by the > manufacturer by using an input with hysteresis. As a counter example: I've > seen diagrams where a 4000 (or 74HC00) is used as voltage controlled sine > oscillator. > > Regards, > Alvin.Article: 60056
Besides the serial configuration PROMs listed at ... http://www.xilinx.com/isp/compfpgatables/prom_spartan.htm, also take a look at the new Xilinx PlatformFlash, which is in-system programmable via JTAG http://www.xilinx.com/platformflash Alternatively, you can use a merchant-market byte-wide Flash devices and a small CPLD, as described in the following application note. http://www.xilinx.com/xapp/xapp079.pdf --------------------------------- Steven K. Knapp Sr. Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC <ram> wrote in message news:ee7f986.-1@WebX.sUN8CHnE... > Hi, > Can anyone recommmend some NVRAM or parallel EEPROM to interface with Spartan2 device. >Article: 60057
"Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0308282129.5f483d78@posting.google.com... <...snip...> > I guess the smallest spartan III and cyclone devices should also come down > below 10$ but then S3-50 does not have BRAM and both Spartan and Cyclone > do require config memory to be present what may add significant amount to > the final price (both money as board estate, etc) > > antti The Xilinx Spartan-3 XC3S50, in its production form, has four 18Kbit block RAMs (BRAM), four 18x18 hardware multipliers, and two digital clock managers. For the correct specifications, see http://www.xilinx.com/bvdocs/publications/ds099-1.pdf. In volume, the XC3S50, the XC3S200, and the XC3S400 are all less than $10 in the smallest packages. To reduce the overall "solution cost", Spartan-3 FPGAs optionally use Xilinx PlatformFlash, which does NOT add a significant amount to the final price. See http://www.xilinx.com/platformflash. Alternatively, configuration data can be stored in just about any non-volatile memory available elsewhere in the system, such as ... * Same Flash that holds the boot code or application code for a processor or microcontroller, * Downloaded from hard disk. --------------------------------- Steven K. Knapp Sr. Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 60058
> I have seen very few references in the literature to the sliding FFT; if anyone is interested I can send the copy > of an IEEE paper about it. What is the IEEE reference (i.e. journal, date & title)? TomArticle: 60059
"Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message news:<bj4sbg$pki$1@sunnews.cern.ch>... > "Tom Seim" <soar2morrow@yahoo.com> wrote in message > news:6c71b322.0309021211.522fed48@posting.google.com... > > > The processes that will go up to 100s will take an average of 8 values > and > > > store that value to the external memory. In that way the data are > minimised > > > by a factor of 8 and the system error is negligible. > > > The SRAM that was found can be used in the architecture of 1M x 72bit, > so 8 > > > accesses in parallel times two in 40 us seems to be more than ok > > > One problem now is how to implement this! my experience do go that far! > > > You've said something about instantiating a processor (I guess something > > > like NIOS), are you sure that this will not complicate things more? > > > Is there something ready to implement a circular buffer to the external > ram? > > > > > > The second problem, and the reason why I asked for help in this group, > is > > > that those SRAMS are quite expensive and having in mind that 2000 of > them > > > will be needed, it increases the cost significantly. So they are > pressing me > > > to find some other way to implement it. (usual stuff: we want the pie > and > > > the dog fed!) > > > > I don't understand why you need 2000 SRAMs. > > > > 25 KHz x 16 x 100 = 40 MB > > > > or 8 SRAMs. > > In the first paragraph I explain that saving the average values of 8 samples > the data are minimised by a factor of 8. So 5 MB have to be stored for this > system (up to 100s) which fit together with the data of the first system (up > to 10ms) in one SRAM. On the card there are 2 more to hold other data. And > 650 of these cards are needed, that gives ~2000 SRAMs. > I guess that you have a lot more channels than I realized. I recommend going to a mass storage device that can hold this amount of data, such as multiple disk drives. Your data rates are relatively slow, giving you the option of streaming interleaved data (don't store a single channel in one place on the disk). You can also look into large DRAMs. Another option is flash memory, but you might wear these devices out. TomArticle: 60060
Dear all, I think I read the application notes from Xilinx FPGA( I downloaded from their website), and I found a mistake(or maybe I have some problems myself), how I can contact the writer of Xilinx application author? ... I searched many options from their website and could not find one... which support team I should contact? Any insider please give me some contacts? Thank you very much, -WalalaArticle: 60061
Christos,
I have read all the previous responses and I have one suggestion. Could
you use a DRAM based memory? For your first pass generate a running sum of
your 250,000 samples. Then add the new value and subtract the old value.
That way you need not do the whole sum for each sample. Use a simple micro
to control the system. It could be as simple as a pico-blaze. You could
even control it with a simple state machine. You really do not need
anything as fast as a SRAM. You can refresh the DRAM between the sample
periods.
Theron Hicks
"Christos" <chris_saturnNOSPAM@hotmail.com> wrote in message
news:bil9f7$4o2$1@sunnews.cern.ch...
> Hi to all,
>
>
>
> The sum or average of a certain number of samples (for ex. the last 100
> values received) have to be checked constantly against a threshold.
>
>
>
> I thought of implementing this by keeping a "Moving Sum" which will work
by
> adding the new value and subtracting the oldest. I think that can be
> implemented by adding to a register the value just arriving and
subtracting
> the value coming out of an 100 word deep shift register.
>
>
>
> Now, if a longer sum has to be checked then there is a memory problem
> because a lot of values have to be stored. In addition more than one
"Moving
> Sums" is needed so if I use the above implementation I will have in
addition
> to store the same data more than once (for ex. the 1000 word Shift
Register
> will include the 100 word S.R. data).
>
>
>
> Any idea of how this could be implemented?
>
>
>
> The final system will have to keep 10 moving sums with the largest being
> 250,000 (8-bit) values for each of the 16 independent input channels.
>
>
>
> Help to the design problem will be appreciated and acknowledged.
>
>
> Christos
>
> __________________________________________________
>
> Christos Zamantzas
> CERN, European Organization for Nuclear Research
> Div. AB/BDI/BL tel: +41 22 767 3409
> CH-1211 Geneva 23 fax: +41 22 767 9560
> Switzerland christos.zamantzas@cern.ch
> __________________________________________________
>
>
Article: 60062antti@case2000.com (Antti Lukats) wrote in message news:<80a3aea5.0309030231.1a98e839@posting.google.com>... > > Thanx for the reply. My question is more likely: Where, in what menu do you > > set an external input to be an interrupt source??? Where do you declare the > > name of the interrupt function??? With a timer you can do that by > > right-clicking the timer and chose a name for the "timer interrupt handler > > function". > > uups, I didnt think > "I usually don't (think), and my wife says its total disaster when I do" > ;) > > I am afraid to get the int line out you need to define a real dummy > peripheral that simple routes the pin to interrupt controller. > then add this peripheral component, place the ports and connect. > in the vhdl of the component you only have one wire-connection > > I should think sometimes sorry, you are right if there is no component > driving interrupt you can not assign int handler either > > antti Hi, To set an external interrupt to be an interrupt source, there is no mechanism available in the GUI currently. But, you could add the following line to the MSS file after the version is declared : PARAMETER VERSION = 2.0.0 PARAMETER HW_SPEC_FILE = system.mhs PARAMETER INT_HANDLER = myint_handler, INT_PORT = myint_pin This will configure microblaze to call "myint_handler" whenever the external interrupt "myint_pin" interrupts microblaze. Also, this is assuming that "myint_pin" is directly connected to the interrupt port of microblaze without an interrupt controller. Hope this helps SathyaArticle: 60063
Walala, You may email it directly to Peter Alfke, or myself. Austin (au s ti n ( a t ) x i l i nx.c o m) (to fool the spam scanners? just remove spaces and replace at with the obvious) walala wrote: > Dear all, > > I think I read the application notes from Xilinx FPGA( I downloaded > from their website), and I found a mistake(or maybe I have some > problems myself), how I can contact the writer of Xilinx application > author? ... I searched many options from their website and could not > find one... which support team I should contact? > > Any insider please give me some contacts? > > Thank you very much, > > -WalalaArticle: 60064
"Rgr" <find@ham.dk> wrote in message news:<bj6ubr$f7$1@news.net.uni-c.dk>... > When I add an interrupt controller to my design I get the following error > when I try to generate libraries: > What does this error mean??? > > > opb_intc (opb_intc_0) - > C:\EDK\hw\iplib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_0_0.mpd:30 - > overriding > C_KIND_OF_EDGE value 11111111111111111111111111111111 to > 00000000000000000000000000000000 > opb_intc (opb_intc_0) - > C:\EDK\hw\iplib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_0_0.mpd:31 - > overriding > C_KIND_OF_LVL value 11111111111111111111111111111111 to > 00000000000000000000000000000001 > lmb_v10 (lmb_v10_0) - > C:\EDK\hw\iplib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_0_0.mpd:21 - > overriding > C_LMB_NUM_SLAVES value 4 to 1 > lmb_v10 (lmb_v10_1) - > C:\EDK\hw\iplib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_0_0.mpd:21 - > overriding > C_LMB_NUM_SLAVES value 4 to 1 > opb_v20 (opb_v20_0) - > C:\EDK\hw\iplib\pcores\opb_v20_v1_10_a\data\opb_v20_v2_0_0.mpd:35 - > overriding > C_NUM_MASTERS value 4 to 1 > opb_v20 (opb_v20_0) - > C:\EDK\hw\iplib\pcores\opb_v20_v1_10_a\data\opb_v20_v2_0_0.mpd:36 - > overriding > C_NUM_SLAVES value 4 to 3 > > Checking platform address map... > > Verifying Bus Interfaces ... > > Checking platform configuration ... > > Building Directory Structure for microblaze_0 > > Checking Processor Rules for microblaze_0 > > Generating platform libraries and device drivers ... > > Copying Library Files ... > > Copying BSP Files ... > > Running CopyFiles ... > > Running DRCs for Drivers and Libraries ... > > Running generate for Drivers and Libraries ... > ERROR:MDT - xget_value : A NULL handle was provided > > > while executing > "xget_value $source_port "NAME"" > (procedure "generate" line 48) > invoked from within > "generate 1490864" > Tcl File cpu_v2_1_0.tcl > ERROR:MDT - Error while running "generate" for processor microblaze_0... > make: *** [microblaze_0/lib/libxil.a] Error 2 > Done. Hi, Looks like the connector name that you have connected to the microblaze interrupt port is not the same as the one connected to your intc's Irq port. All the interruptible sources are connected to the intc's Intr port as "a & b & c" and the Irq port connector of intc is connected to the interrupt port of microblaze. If the above setting is right, do check if the intc is visible from microblaze i.e, intc should be visible on the opb bus connected to microblaze. The above are the possible reasons for the error that you see above. Hope this helps. SathyaArticle: 60065
I'm investigation configuration PROMs for a EPF6010A (FLEX 6K). It looks like the default choice is the EPC1441 which is not ISP or Flash. Altera makes the EPC2 which is Flash/ISP but for some reason it's not compatible with FLEX6K. Anyone know why? Any way to get it to work with the EPF6010A? I also noticed Atmel makes Altera compatible configuration PROMs that are EEPROM/FLASH. Specifically, the AT17LV512A-10JC (8-PDIP). Can anyone give me a ball park figure on the price for either Altera or Atmel configuration ROM? DigiKey doesn't have them in stock and the price for the Atmel 1MBit one they do have in stock scares me (> $45). Today is not the best day for me to do battles with the distributors...so ballparking would be nice. Any other suggestions for cheapo configuration PROMs? I think awhile back I saw someone mention parts from ISSI...would that work in this case? I'm not tied down to a Flex6K persay, I think however it's the cheapest 3.3V(core) FPGA Altera offers with a TQFP package. Thanks! Jay.Article: 60066
"Mario Trams" <Mario.Trams@informatik.tu-chemnitz.de> wrote in message news:bj70hb$3j3$1@anderson.hrz.tu-chemnitz.de... (snip) > > I see that devices are sold in terms of their gate count. How > > efficient is a typical design? For instance, if I want to make a 16 by > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > > see that I need 16 OR gates each with 16 AND array inputs for the > > output terms, 64 latches to store the selection and some more gates to > > do the latch address decoding. Is there any easy way to choose the > > right part? > > That is very difficult to answer. This issue has been discussed sometimes > in this newsgroup already, and will probably be discussed again and again. > > You should never ever draw some conclusions from the gate-count > given by the manufacturers. This is just a marketing number. > I started with Lucent (now Lattice) ORCA FPGAs and got a feeling > what can be put inside. Then I turned to Xilinx Virtex FPGAs (because > of the free development software) and got rather shocked how much > less one can put into such an FPGA with a comparable gate count. Well, some designs fit the FPGA model better than others. My guess is that a crossbar switch is one that doesn't fit very well, but that is a guess. > For instance, they include internal RAM-Blocks in the official > gate-count number. That gives a shiny value, but is nonsense if > you ask me. > My guess is that the Xilinx people that are around here in this > newsgroup think similar because they are more engineers rather than > marketing people. > But apart from that, the Xilinx FPGAs are not bad ones. The traditional CMOS definition for gate count is the number of transistors divided by four. It takes four to make a CMOS 2 input NAND gate. RAM arrays are included in that count. (snip) > Once you got some design software, you might also try to synthesize > your design (provided it has been finished already) and try to fit > it into different FPGA types. There you will also see how much of > the FPGAs' capacity would be used. This is probably the best way. First, the manufacturer given gate count is a maximum, and you should expect somewhat less. There may be a wide variation on how much you actually get. -- glenArticle: 60067
All, I beg to differ. We have not only a good solution, but a great solution: http://www.xilinx.com/prs_rls/end_markets/02151crossbar.htm The worlds first FPGA cross bar switch that uses the programmable interconnect as....well, as a corss bar switch! Extremely efficient (able to do 1024x1024 in a 2V6000 at 155 Mbs each wire, non-blocking). For a really small cross bar, one could use the ICAP with the microblaze for control, and a bram for the patterns....and perhaps only 16 CLBs for a 16X16 non-blocking cross point switch..... Austin Glen Herrmannsfeldt wrote: > "Mario Trams" <Mario.Trams@informatik.tu-chemnitz.de> wrote in message > news:bj70hb$3j3$1@anderson.hrz.tu-chemnitz.de... > > (snip) > > > > I see that devices are sold in terms of their gate count. How > > > efficient is a typical design? For instance, if I want to make a 16 by > > > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > > > see that I need 16 OR gates each with 16 AND array inputs for the > > > output terms, 64 latches to store the selection and some more gates to > > > do the latch address decoding. Is there any easy way to choose the > > > right part? > > > > That is very difficult to answer. This issue has been discussed sometimes > > in this newsgroup already, and will probably be discussed again and again. > > > > You should never ever draw some conclusions from the gate-count > > given by the manufacturers. This is just a marketing number. > > I started with Lucent (now Lattice) ORCA FPGAs and got a feeling > > what can be put inside. Then I turned to Xilinx Virtex FPGAs (because > > of the free development software) and got rather shocked how much > > less one can put into such an FPGA with a comparable gate count. > > Well, some designs fit the FPGA model better than others. My guess is that > a crossbar switch is one that doesn't fit very well, but that is a guess. > > > For instance, they include internal RAM-Blocks in the official > > gate-count number. That gives a shiny value, but is nonsense if > > you ask me. > > My guess is that the Xilinx people that are around here in this > > newsgroup think similar because they are more engineers rather than > > marketing people. > > But apart from that, the Xilinx FPGAs are not bad ones. > > The traditional CMOS definition for gate count is the number of transistors > divided by four. It takes four to make a CMOS 2 input NAND gate. RAM > arrays are included in that count. > > (snip) > > > Once you got some design software, you might also try to synthesize > > your design (provided it has been finished already) and try to fit > > it into different FPGA types. There you will also see how much of > > the FPGAs' capacity would be used. > > This is probably the best way. First, the manufacturer given gate count is > a maximum, and you should expect somewhat less. There may be a wide > variation on how much you actually get. > > -- glenArticle: 60068
"Brian Fairchild" <spam.spam@spam.com> wrote in message news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com... > efficient is a typical design? For instance, if I want to make a 16 by > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > see that I need 16 OR gates each with 16 AND array inputs for the > output terms, 64 latches to store the selection and some more gates to > do the latch address decoding. Is there any easy way to choose the Just as an academic thing for myself. Is a bi-directional crosspoint switch able to be produced with a FPGA? My understanding is they are a matrix of fets each one having a memory cell to store it's setting. So I would say that it was impossible. Even a fully digital one would still require that an an I/O pin can be used for input and output at the same time. Can anyone confirm or deny? Thanks RalphArticle: 60069
Regardless which method is used, using a CIC limits the number of memory
transactions per sample to just two: a read and a write. The memory is used as
a delay queue, so the read pointer is N samples behind the write pointer. The
memory required for all those channels is pretty big, so DRAM would be the way
to go if you are using semiconductor memories. Since the addressing can easily
be made linear, you can simplify it by using page mode or burst accesses. This
should make it fast enough to multiplex many channels into one memory .
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60070In a flurry of electrons Ralph Mason spake thus: >"Brian Fairchild" <spam.spam@spam.com> wrote in message >news:jhcclv0p5n1628t9s1cdfpthac60ltjub4@4ax.com... > >> efficient is a typical design? For instance, if I want to make a 16 by >> 16 CPU controlled crosspoint how many FPGA gates will I need? I can >> see that I need 16 OR gates each with 16 AND array inputs for the >> output terms, 64 latches to store the selection and some more gates to >> do the latch address decoding. Is there any easy way to choose the > >Just as an academic thing for myself. > >Is a bi-directional crosspoint switch able to be produced with a FPGA? My >understanding is they are a matrix of fets each one having a memory cell to >store it's setting. > >So I would say that it was impossible. Even a fully digital one would still >require that an an I/O pin can be used for input and output at the same >time. To clarify, what I wanted to do as an example was a uni-directional crosspoint. -- Brian Fairchild B dot Fairchild at Dial dot Pipex dot Com "But apart from that Mrs Lincoln, how did you enjoy the play?"Article: 60071
"Rgr" <find@ham.dk> wrote in message news:<bj6ubr$f7$1@news.net.uni-c.dk>... > When I add an interrupt controller to my design I get the following error > when I try to generate libraries: > What does this error mean??? someone at xilinx may know :) we found it extremly difficult to make a system from ground up its simpler to take some existing design and modify it, so take a desing with interrupt controller, synthesize it, verify it is ok then compare with your design,.. there are really lots of problems with XPS, lots of things fail and the problems are not always visible antti http://www.graphord.com/forumArticle: 60072
"Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message news:3F5782D1.746E1D51@xilinx.com... > All, > > I beg to differ. We have not only a good solution, but a great solution: > > http://www.xilinx.com/prs_rls/end_markets/02151crossbar.htm > > The worlds first FPGA cross bar switch that uses the programmable interconnect > as....well, as a corss bar switch! Extremely efficient (able to do 1024x1024 in > a 2V6000 at 155 Mbs each wire, non-blocking). > > For a really small cross bar, one could use the ICAP with the microblaze for > control, and a bram for the patterns....and perhaps only 16 CLBs for a 16X16 > non-blocking cross point switch..... That does sound pretty neat. I was thinking of it in terms of synthesizable logic using CLB's. Can you do a barrel shifter for floating point prenormalization/postnormalization that way, too? -- glenArticle: 60073
Someone knows like turn off the "pull up" that the family "spartan2" connects for default to " tristate" placed inner lines in, from buffer " Tbuf"? I use "Xilinx ISE 4.1ì" and language "vhdl". thanksArticle: 60074
Dear Arrigo The patent you mentioned is only the first one and not directly related to FFT. Following FFT specific patent is granted but not yet complete (I have to pay an issuance fee yet). The patent has nothing to do with sliding FFT, though it can perform inter-block pipelined (any block) transforms. The row- and column-transform are not related to row and column transform of a 2-D FFT as you described. The innovation is based on sampling and reconstruction of bandlimited signals (harmonic limited) of finite support in multi-dimensional space. Seung Arrigo Benedetti <arrigo@vision.caltech.edu> wrote in message news:<q0iso9qbjf.fsf@vision.caltech.edu>... > I have spent some time to study this patent and, to be honest, I have not found much innovation at all. > I might have missed something, but this seems a standard 2-D FFT implemented as a 1-D row (column) FFT > followed by N 1-D column (row) transforms. The memory requirement for the column transforms is of N words > for each transform for a total of N^2. This makes the architecture quite impractical for an FPGA implementation > of large size transform. > The basic block seems to be related to the sliding 1-D FFT, which has complexity N instead of N log(N). > This would reduce the complexity of the 2-D FFT from N^2 log(N) to N^2. > (I am using the conditional since I have not spent much time on this.) > I have seen very few references in the literature to the sliding FFT; if anyone is interested I can send the copy > of an IEEE paper about it. > Any other comments? > > -Arrigo
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