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In article <8c046f$pam$2@jetsam.uits.indiana.edu>, galexand@sietch.bloomington.in.us (Greg Alexander) wrote: > In article <8bv4us$7st$1@nnrp1.deja.com>, rob_dickinson@my-deja.com wrote: > >In article <8btl68$kjh$1@jetsam.uits.indiana.edu>, > >galexand@sietch.bloomington.in.us (Greg Alexander) wrote: > >> In article <8bt2io$rnp$1@nnrp1.deja.com>, rob_dickinson@my-deja.com > >wrote: > >> >Having read most of this thread I have the following global comments. > >> > > >> >1)If you just want to play then surely you can understand that > >company > >> >A or X have better things to do than to be bothered with even a few > >> >hundred people going "your" route. > >> > >> Total disagreement. As I've said before, most people competent in the > >> field learned most of what they knew going in just playing around. The > >> more hobbyists playing with it today the more companies buying hte > >things > >> tomorrow. I think Linux's commercial success proves that -- I don't > >think > >> managers picked it because htey liked it, I think managers picked it > >> because their employees said "I know and like Linux, it'll do the job > >and > >> if it doesn't we'll make it." > > > > > >Greg > >I'm about to disapoint you. > >FPGA's are inevitably designed by many people in such a manner that > >they can be maintained by other people over many years and probably > >ported easily to newer devices. The ability to "hack" at or near the > >bitstream level will not impress many people and I can assure you that > >decisions to invest 10,000 (say) man hours because "Greg played with > >bitstreams at home" will not cut it at all. If it was "Greg is bloody > >good at VHDL simulation using VITAL and does the job in half the time" > >then you probably will still not influence the decision making but you > >will get paid more than the next guy. > >Yes one guy can probably write good code for FPGA's on his own, doing > >it some strange weird way because X let him do it at the bitstream > >level, but you might go under a bus and you will almost definitely > >change companies during the lifetime of the #CODE#. You are therefore > >only usefull to a company if you are competent with the tools which the > >next guy can use. > >The more hobyists using VHDL (which is free from the right places) the > >better, the more people coming through degrees who still know what a > >counter or state machine is at the gate level, even better. A thorough > >knowledge of the routing architecture at any level is almost useless, > >Vertex will be almost completely superceeded in a frighteningly short > >time and no-one will give diddly squat that you know it litterally > >inside out. > > As easily as you dismiss my approach to learning, people who have been > through my approach to learning completely dismiss anything learned your > way as being inadequate and cloudy. *shrug* Bias can go both ways and it > doesn't make either side right -- but if there are two sides you shouldn't > be so sure yours is the only way. I maintain that you don't know anything > if you don't know how it works -- you can't learn how FPGAs in general > work if you don't look in depth at at least one example and looking in > edpth at the Vertex chip won't make you any stupider when you see the > foobar chip -- if anything, it'll make you smarter because you'll see the > historical basis for decisions and you'll see neat innovations rather than > just an entirely new system. If you'll never learn ANY of the chips then > I continue to maintain that you know plenty to get most jobs done, but not > enough for extreme excellence, which is sometimes demanded. > I absolutely do not dismiss your approach to learning in any way. I am certain that if X and A gave you what you want then you would *LEARN* more than I will ever know. However I am quite certain that I will achieve exactly as much as you ever will (and more, because you insist on not starting). This thread is becomming a waste of my time, you very childishly insist that X and A should give you exactly what you want, with the OS of YOUR choice. The need for extreme excellence requires that I understand the architecture of VIRTEX perfectly, and I do. I don't give a toss how X have routed the programming matrix. Ask 50 taxi drivers how to route across London and you will get 50 answers, they are all correct. You have decided that the route to extreme excellence is to learn everything, can I suggest that this requires an absolute knowledge of:- digital design at board level digital design at the FPGA level the exact architecture of the FPGA complete understanding of semi-conductor physics and particle physics and GOD! Have fun spending the rest of your life trying for your version of extreme excellence, I will do what engineers do, I will create things, using tools which are not perfect, but which will try n iterations to get a timing result which is excellent enough (while I learn something else). Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21776
Hello, I am writing a synthesisable model of 82C54 (Intel) and I have many questions to the circuit. Intel do not want to reply for these questions because the circuit is not supported now for Intel. If somebody could help me please about reply I will be very thankfull; Tomek tbrychcy@sensor.ime.pz.zgora.plArticle: 21777
You might have a bit of trouble locating "Lattice 22V10" on the Xilinx target device list :) By Murphy's law, it would be a miracle if the cables (e.g. the PC parallel port pins used) and programming algorithms were compatible between the two companies. You could check out the Xilinx CoolRunner (formerly from Philips) family which has a 22V10 ISP part. This seems to be programmable with a Xilinx JTAG cable & free webpack software. http://www.xilinx.com/products/coolpld.htm http://www.xilinx.com/products/software/webpowered.htm Though I wouldn't be surprised if Lattice offers something similar in the way of a simply constructed JTAG cable and free software. regards, tom Andy Peters wrote: > > Has anyone tried this? > > I need a small pld on a board I'm doing, and the Lattice ISP 22V10 should be > fine. I want ISP because I don't want sockets. And since I already have > the Xilinx software and cables, theoretically, this should work. > > Or not? > > -- a > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "Money is property; it is not speech." > -- Justice John Paul StevensArticle: 21778
Hello, Why during synthesis (xilinx foundation 2.1) are warnings: No net is connected to the set/reset pin of Cell (the warning relates to > each output) Why are so warnings?Article: 21779
hi, I am trying to create physical macro using Xilinx foundation series. But according to the xilinx technote, it is possibe only to create a macro with place component.is it true? Has any one done a routed macro? How did you do it ? thanks thanks spyng Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21780
In article <8c1e4i$r7i$1@jetsam.uits.indiana.edu>, Greg Alexander wrote: >Does anyone have any citations for Thompson's original work? > Adrian Thompson has a web page at http://www.cogs.susx.ac.uk/users/adrianth/ade.html There's an article on evolvable hardware in the March 2000 issue of IEEE Spectrum. It cites Explorations in Design Space: Unconventional electronics design through artificial evolution. Adrian Thompson, Paul Layzell and Ricardo Salem Zebulum. IEEE Transactions on Evolutionary Computation, September 1999, Volume 3, Number 3, pp. 167-196. which is available at the above address. An earlier paper describing the evolution of a tone discrimination circuit in a XC6216 is An evolved circuit, intrinsic in silicon, entwined with physics In: Proceedings of The First International Conference on Evolvable Systems: from Biology to Hardware (ICES96). Higuchi, T. and Iwata, M. (eds.), 390-405, Springer Verlag LNCS 1259, 1997. (also at the above URL) Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21781
some time ago I tried to ask the same question in thist group, unfortunatly peter chanced the topic to xilinx internals ... it seem to be is job ... so well - I am using Virtex and Spartan devices but on higher frequencies I've always the problem with power cosumption. Yes it is true, it doesn't depend on the resistors, but a SRAM based system has two disadvantages. Even SRAM LUT's have power consumption and capacitors. this will rais e the consumption too. Thats why I am going to use Quicklogic too. As far as I could see it is not a big problem to transfer a (vhdl- based) design form xilinx to quicklogic, if you use synopsys. But you have to keep in mind, that size does matter and the timing will also be completly different. If you do only protyping and your need incircuit programming ... stay with SRAM based one altera, xilinx, lucent etc. If you don't have huge designs (vitex sized), you wanna reduce your power consumtion and rais up the speed of your design, it a good idea to think about actel or quicklogic. But keep in mind that you need a programming device, but it may be partitionally sponsored by one of this vendors. If you do quick digital signal processing, have a look to quicklogic's QuickDSP stuff. good luck ff David Miller schrieb: > Does anyone have any experience of using these parts? > > The ProASIC is Flash based which, to me, seems an interesting half-way > house between antifuse and SRAM. Will it offer the best (or worst) of > both worlds? > > David MillerArticle: 21782
Hi friends, thank you very much for your help. I have found with timing analyser the clock net and then found this net in RTL viewer. So I could lokate,what net it was. The problem was caused by "bad" VHDL that was bad synthesiezed. Than you once more Bonio Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21783
In article <8bta6v$qkc@catapult.gatech.edu>, Anshuman Sharma <gte600f@prism.gatech.edu> wrote: > I am designing a processor that runs the calculator game "worm". I have > designed it in VHDL and I am going to use a Flex10k part to synthesize > it. I want help with the VGA display. Basically if anyone can help me find > something on how I can build a VGA module that will interact with my > datapath and the game as a whole. > You may find the following page useful: http://www.eecg.utoronto.ca/~singhd/241/vgacon.htm "This page contains basic information describing the use of the VGA output port provided on the Altera UP1 Educational board. VHDL source code for a simple VGA controller ( VgaCon ) is provided. The purpose of VgaCon is to isolate the details of VGA signal generation from all the other modules in a design. VgaCon allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. Thus for modules interfacing with VgaCon, the process of drawing on the screen consists of a request to colour a point located at any valid row and column." (The Altera UP1 board has a FLEX10K20 on it. The VHDL code should be re-usable.) Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21784
Hi Andy,
Andy Peters wrote:
> I need a small pld on a board I'm doing, and the Lattice ISP 22V10 should be
> fine. I want ISP because I don't want sockets. And since I already have
> the Xilinx software and cables, theoretically, this should work.
>
> Or not?
I'm not familiar with the Lattice ispGAL22V10, but from what I've heard, it is
not fully JTAG compatible. The ispGAL22*LV*10 is, however (well, at least the
datasheet explicitly says it's 1149.1 compliant when programming). I have
third-party JTAG tools and while they can program the 22LV10, they can't do so
with the 22V10.
The JTAG compatibility of 22V10-similar devices made by other manufacturers
should be verified.
Regards,
Étienne.
--
______ ______
*****/ ____// _ \_\*************************************************
* / /_/_ / /_/ / / Etienne Racine, Hardware Designer *
* / ____// __ /_/ Visual Systems Engineering *
* / /_/_ / / /\ \ \ CAE Electronics Ltd. *
*/_____//_/_/**\_\_\*************************************************
Article: 21785There are some other manufacturers of this chip, one of them is Intersil. The link below points to their 82C54 datasheet page http://www.intersil.com/data/fn/fn2/fn2970/index.asp An overwiew over all 8086/286 peripherals is at http://www.intersil.com/micro/upx86.asp Jens Tomasz Brychcy wrote: > > Hello, > > I am writing a synthesisable model of 82C54 (Intel) and I have many > questions to the circuit. Intel do not want to reply for these questions > because the circuit is not supported now for Intel. > > If somebody could help me please about reply > > I will be very thankfull; > > Tomek > > tbrychcy@sensor.ime.pz.zgora.plArticle: 21786
I agree with Rob's assessment of what it takes to make a good fpga designer. It also helps to have good visualization skills when it comes to floorplanning. I like to say floorplanning is much like doing a jigsaw puzzle, except that there are many solutions, some better than others. It seems to take a knack to see the good solutions through the not-so good. From what I've seen some people have it and some don't. I think a quote from Jerry Avins (one of the Comp.dsp regulars) sums this up just about right: "Engineering is the art of making what you want from things you can get." rob_dickinson@my-deja.com wrote: > I absolutely do not dismiss your approach to learning in any way. I am > certain that if X and A gave you what you want then you would *LEARN* > more than I will ever know. However I am quite certain that I will > achieve exactly as much as you ever will (and more, because you insist > on not starting). > > This thread is becomming a waste of my time, you very childishly insist > that X and A should give you exactly what you want, with the OS of YOUR > choice. The need for extreme excellence requires that I understand the > architecture of VIRTEX perfectly, and I do. I don't give a toss how X > have routed the programming matrix. Ask 50 taxi drivers how to route > across London and you will get 50 answers, they are all correct. You > have decided that the route to extreme excellence is to learn > everything, can I suggest that this requires an absolute knowledge of:- > > digital design at board level > digital design at the FPGA level > the exact architecture of the FPGA > complete understanding of semi-conductor physics > and particle physics > and GOD! > > Have fun spending the rest of your life trying for your version of > extreme excellence, I will do what engineers do, I will create things, > using tools which are not perfect, but which will try n iterations to > get a timing result which is excellent enough (while I learn something > else). > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21787
I can't agree with alot of this. See my comments interspersed. Hans Holm wrote: > ... > > so well - I am using Virtex and Spartan devices but on higher frequencies > I've always the problem with power cosumption. Yes it is true, it doesn't > depend on the resistors, but a SRAM based system has two disadvantages. > Even SRAM LUT's have power consumption and capacitors. this will rais e > the consumption too. The static consuption of the LUTs is a very small fraction of the total chip power, even for modest designs. FPGAs are fabricated using CMOS technology. CMOS gates inputs are very hgh impedance, but do have a significant capacitance associated with them. As a result, an internal driver drives a significant current when the node is switching to charge or discharge the input capacitance. When the node is static (not switching), the current is limited to the sum of the leakage currents of the complementary transistor in the output and the MOS gate inputs. This static current is quite small compared to the switching currents. > Thats why I am going to use Quicklogic too. > As far as I could see it is not a big problem to transfer a (vhdl- based) > design form xilinx to quicklogic, if you use synopsys. But you have to > keep in mind, that size does matter and the timing will also be completly > different. If your designs transfer that easily, the likelyhood is quite high that the design is not well suited to either FPGA. Even coding strictly at an RTL level, you can make a design that is more suited to a particular array. For example, Xilinx arrays have a rich local interconnect structure, but the delays increase as you move further from a source node. Clock enables come for free in the Xilinx. In the Altera arrays, using a clock enable in arithmetic logic will push the adder to two logic levels, doubling the size of the circuit. Altera does however have a fairly distance independent propagation delay as long as you stay within a row. Thus, if I am targeting an FIR filter for Xilinx, I'll connect the adders as a linear chain and absorb the pipeline delay as part of the filters delay by using a partially transposed architecture. Since the clock enable is there anyway, there is no problems with an intermittent data stream. (also xilinx lets you use the LUTs as delay queues, but thats another story). Now, If I were to jsut put that same filter in Altera, the size of the adder chain alone would be double that of xilinx in terms of number of 4-luts because of the clock enable. Instead, in Altera, I'll arrange the adders in a tree structure so that the clock latency for each tap is equal, that way I can use the clock enables just on the inputs and outputs of the tree, allowing the data to just trickle through the pipelined tree all the time, whether it is valid or not. In this case, the long connections caused by the tree structure are not a handicap since Altera's routing delay is not strongly dependent on distance. The point is, the overall structure (linear chain vs tree) is considerably different for optimal designs in these two devices. These structural differences have to be part of your code, as it is not something the synthesis tools can figure out...and I don't see that changing anytime soon. > > If you do only protyping and your need incircuit programming ... stay with > SRAM based one altera, xilinx, lucent etc. > If you don't have huge designs (vitex sized), you wanna reduce your power > consumtion and rais up the speed of your design, it a good idea to think > about actel or quicklogic. But keep in mind that you need a programming > device, but it may be partitionally sponsored by one of this vendors. > If you do quick digital signal processing, have a look to quicklogic's > QuickDSP stuff. I think if you put dollars to donuts, you'd find that the SRAM based devices are as fast or faster than the antifuse devices. This happens because the antifuse fabrication is more complex, so it tends to be at least a generation behind the process used in the SRAM devices. Again, I don't think you'll see a significant difference in power either, in fact the SRAM devices may win out there too by using a smaller geometry. The power in either case is dominated by the power required to charge and discharge the gate and route capacitances when the design is switching. If you are doing DSP, you really want an architecture that handles arithmetic well in the fabric, which means capable carry chains. Additionally, you need the ability to implement numerous small delay queues (filters for example). This makes the xilinx architectures hands down winners for DSP applications. Quicklogic's QuickDSP answers this by using a relatively small number of somewhat fixed arithmetic resources. While these resources are quite fast, you wind up getting into a situation similar to that of a DSP processor where you have a small number of high value resources that need to be shared by a number of tasks. For certain applications this will work well, but for highly parallel DSP processing, I find a more distributed capability such as is presented by the Xilinx architecture to be superior (Sorry John, but that's the way I see it). The problem there is that there are no carry chains in the programmable fabric, only in the high value arithmetic elements, of which there are only a few. > > > good luck ff > > David Miller schrieb: > > > Does anyone have any experience of using these parts? > > > > The ProASIC is Flash based which, to me, seems an interesting half-way > > house between antifuse and SRAM. Will it offer the best (or worst) of > > both worlds? > > > > David Miller -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21788
That circuit is quite thoroughly documented in a number of computer architecture textbooks from the mid-eighties. Unfortunately, I cant recall any of the titles where I had seen it. Tomasz Brychcy wrote: > Hello, > > I am writing a synthesisable model of 82C54 (Intel) and I have many > questions to the circuit. Intel do not want to reply for these questions > because the circuit is not supported now for Intel. > > If somebody could help me please about reply > > I will be very thankfull; > > Tomek > > tbrychcy@sensor.ime.pz.zgora.pl -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21789
One option is to host a 6200 like architecture on an existing FPGA by creating a 'virtual structure' on an existing FPGA. I have done some work on this and can provide an overview and details where necessary. This approach is by no means an optimal use of resources on the target FPGA but it can be done. I have not though attempted to do similar experiments to Thompson's using the resultant circuits. However, this approach does let you put down random configurations without frying the device, you could also look at other cell designs etc. For a very good overview of Thompsons work, his PhD thesis was published by Springer (there's details about it on his web site), it's highly readable and gives an excellent overview of the field of evolvable hardware as a whole. The IEEE Transactions on Evolutionary Computation last year had a special issue dedicated to the topic and is also a good starting point. "Anshuman Sharma" <gte600f@prism.gatech.edu> wrote in message news:8c0h40$b3f@catapult.gatech.edu... > Anybody who is familiar with Adrian Thompson and his work with Hardware > Evolution can help. I am trying to duplicate theArticle: 21790
I see that his previous reference was already posted. Also, Adrian Thompson has a book out about his work. Please see: http://www.amazon.com/exec/obidos/ISBN=3540762531/optimagicsprograA/ -- ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- "Greg Alexander" <galexand@sietch.bloomington.in.us> wrote in message news:8c1e4i$r7i$1@jetsam.uits.indiana.edu... > Does anyone have any citations for Thompson's original work? > > In article <38E4342A.4B3CD10C@xess.com>, Dave Vanden Bout wrote: > >This is a multi-part message in MIME format. > >--------------635EE6AE738F288B60AB5AEF > >Content-Type: text/plain; charset=us-ascii > >Content-Transfer-Encoding: 7bit > > > > > > > >Rickman wrote: > > > >> I am not at all familiar with the work of Adrian Thompson or much > >> familiar with Hardware Evolution, but why can't you do the same thing in > >> a simulation rather than to have to work directly with a bitstream and > >> load a part for test? > >> > >> EDIF files can be "randomly" connected and simulated to test the > >> functionality. Your software may crash once in awhile, but it is > >> unlikely to fry the computer. > >> > > > >Thompson's results were heavily dependent upon parasitic effects in the FPGA chip that affected the selection of fit individuals in the population. Software simulations could be used in the genetic algorithm feedback loop, but a lot of the interesting circuits evolved during Thompson's experiments would never emerge. These evolved circuits often used LUTs and routing resources in ways that any logic or timing simulator (or human) would consider completely whacked. > > > > > >-- > >|| Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || > >|| devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || > >|| http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 || > > > > > >--------------635EE6AE738F288B60AB5AEF > >Content-Type: text/x-vcard; charset=us-ascii; > > name="devb.vcf" > >Content-Transfer-Encoding: 7bit > >Content-Description: Card for Dave Vanden Bout > >Content-Disposition: attachment; > > filename="devb.vcf" > > > >begin:vcard > >n:Vanden Bout;Dave > >tel;fax:(919) 387-1302 > >tel;work:(919) 387-0076 > >x-mozilla-html:FALSE > >url:http://www.xess.com > >org:XESS Corp. > >adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA > >version:2.1 > >email;internet:devb@xess.com > >title:FPGA Product Manager > >x-mozilla-cpt:;-16464 > >fn:Dave Vanden Bout > >end:vcard > > > >--------------635EE6AE738F288B60AB5AEF-- > > >Article: 21791
Tom Burgess wrote in message <38E46B41.D6E991FC@home.com>...
>You might have a bit of trouble locating "Lattice 22V10" on the Xilinx
>target device list :) By Murphy's law, it would be a miracle if the cables
>(e.g. the PC parallel port pins used) and programming algorithms were
>compatible between the two companies.
Yup, I checked! No choices for Lattice there...but I downloaded a BSDL file
from Lattice's web site, and you can select that, but there's no way to
indicate which .JED file you need. And if you choose a .JED file instead of
the BSDL file, it complains that the file is not valid.
>You could check out the Xilinx CoolRunner (formerly from Philips) family
>which has a 22V10 ISP part. This seems to be programmable with a Xilinx
>JTAG cable & free webpack software.
>
>http://www.xilinx.com/products/coolpld.htm
>http://www.xilinx.com/products/software/webpowered.htm
The datasheet for the coolrunner 22V10 doesn't mention anything about ISP,
which is why I went down the Lattice route.
>Though I wouldn't be surprised if Lattice offers something similar in the
>way of a simply constructed JTAG cable and free software.
They do, but it sorta seems silly to replicate the functionality of
something I've already got.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 21792We maintain a list of various FPGA and VHDL related books on The Programmable Logic Jump Station site at: http://www.optimagic.com/books.html I've heard fairly positive reviews of the Xilinx Student Edition/XESS board combination. The book is listed at: http://www.optimagic.com/books.html#Xilinx Be sure to get version 1.5. The various VHDL books are listed at: http://www.optimagic.com/books.html#VHDL As with the previous poster, I like the HDL Chip Design book because it's a bit of a Rosetta stone with VHDL, Verilog, and schematic side-by-side. -- ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- "Pratip Mukherjee" <pratipm@yahoo.com> wrote in message news:qJWB4.19073$YU2.424590@typhoon.ne.mediaone.net... > I want learn about FPGA and VHDL or Verilog programming. I am planning to buy > the kit from XESS Corp. along with their book and software. Is that sufficient > for learning or should I also buy a standard book on the subject? In that case > which book has good practical examples for the starters to try (which are not > too simple like blink a LED nor too difficult like design of a 16bit RISC > processor, as in the recent Circuit Cellar article? > Thanks. > > Pratip MukherjeeArticle: 21793
>Hi Andy,
>I'm not familiar with the Lattice ispGAL22V10, but from what I've heard, it
is
>not fully JTAG compatible. The ispGAL22*LV*10 is, however (well, at least
the
>datasheet explicitly says it's 1149.1 compliant when programming). I have
>third-party JTAG tools and while they can program the 22LV10, they can't do
so
>with the 22V10.
The LV part would work, too, since it's got 5V-tolerant I/O and I have both
3.3V and 5V on the board. I just wanted to use a bit of hardware and
software that I've already got, rather than trying to hook up yet another
parallel port cable.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Etienne Racine wrote in message <38E49073.C57B3357@cae.ca>...
Article: 21794>Remaining advantages: Instant-on, single-chip, and a certain degree >of radiation-resistance. I would add that antifuse gives you a certain measure of design security that is difficult to achieve with SRAM based devices. Since your bitstream is never seen by an end user of an antifuse device, it is more difficult to duplicate a design exactly (certainly NOT impossible given enough $) This is a problem in the industry I work in (video games) because there are lots of people who would quickly produce knock-off hardware of a successful game if we didn't do what we can to prevent it. Xilinx will say that you can protect the bitstream by never allowing the FPGA to power down with a battery backup approach, but this is pretty impractical in my book. Having to send a piece of hardware back to the factory when some idjit shorts the battery out would really suck :-( It's too bad that xilinx can't figure out a way to store a key permanently on the device and generate an encrypted bitstream. I understand that any kind of non-volatile cel/fuse would add process steps and/or cost, but it would make using sram based FPGAs so much easier for us. -- Andrew Dyer <adyer@enteractDOTcom> Where do you want to go today? Nevermind, you're coming with us.Article: 21795
Dear Forum, Is there sameone experience with Modem Pooling device using serial port. Where could i get any reference for design this project/ Thank's a lot regards, HartonoArticle: 21796
Andy Peters wrote:
> Yup, I checked! No choices for Lattice there...but I downloaded a BSDL file
> from Lattice's web site, and you can select that, but there's no way to
> indicate which .JED file you need. And if you choose a .JED file instead of
> the BSDL file, it complains that the file is not valid.
Selecting a third-party BSDL file is typically done when you have a JTAG chain
with mixed devices; to properly configure one device, all others must be placed
in BYPASS. Since the software doesn't know the length of the JTAG instruction
registers on those devices, you need to provide BSDL files so the components can
be correctly BYPASS'ed.
As for the JEDEC file goes, there is a header somewhere within the file that
indicates the targeted device; if the programming software does not recognize
that header (as it is the case here), it won't work. The result is the error
message you got that stated something about the file being invalid.
> They do, but it sorta seems silly to replicate the functionality of
> something I've already got.
Fortunately, standardization is on its way; until then, you'll have to either
swap cables/software, make a standard interface, or get a third party tool.
Hope it helps,
Étienne.
--
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*****/ ____// _ \_\*************************************************
* / /_/_ / /_/ / / Etienne Racine, Hardware Designer *
* / ____// __ /_/ Visual Systems Engineering *
* / /_/_ / / /\ \ \ CAE Electronics Ltd. *
*/_____//_/_/**\_\_\*************************************************
Article: 21797Kate, Sorry for the confusion. The APS-V240 Rev A data sheet did have an error on the PC-104 pin out. The new sheet can be seen at: http://www.associatedpro.com/v240.pdf Also I will email it to you. You should have also gotten some scheamtics and examples on a CD. I will email the schematics, just in case. Let me know if you did not get the CD. Richard Schwarz, President APS Kate Atkins wrote: > Hi all > > We have one of these boards and are having some hassle because the data > sheet on the web site gives the wrong FPGA to PC104 bus interface pin > mapping. We are also not sure about the FPGA to ZBT RAM pin mapping (or any > of the rest of it). This part of the data sheet appears to have been copied > from the X240 data sheet but doesn't match the PCB. > > APS have not replied to our emails about this. Before we resort to > microscope and continuity tester can anybody help with any more info? > > Regards > > KateArticle: 21798
Oops, I was indeed sadly mistaken - looks like only the newer and bigger) XPLA3s support ISP. Looks like a design win for Lattice. Hmm. 4 ns speeds, 3 ns Tcko, 250 MHz fmax - these 22LV10s look pretty nice, except for the >100 mA static power. regards, tom Andy Peters wrote: > > > The datasheet for the coolrunner 22V10 doesn't mention anything about ISP, > which is why I went down the Lattice route. > -- Tom Burgess -- Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.caArticle: 21799
fulvs@my-deja.com ha scritto nel messaggio <8c06as$d2u$1@nnrp1.deja.com>... >I'm trying to understand the difference between >antifuse, SRAM and flash based FPGAs At www.actel.com you can find many documents about antifuse technology. Antifuse was the only technology for the FPGAs produced by Actel, but recently his introduced a new FPGA family based on FLASH erasable (ProASIC). Luigi
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