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Sorry, in my confused state I ommited some very important information. I'm using Xilinx ISE 4.1 with FPGA Express. Thanks, Dave "Dave Brown" <dbrown@novatel.ca> wrote in message news:9qnk2u$2pu$1@pallas.novatel.ca... > I get the following Timing Constraint not met message: > > Asterisk (*) preceding a constraint indicates it was not met. > > -------------------------------------------------------------------------- -- > ---- > Constraint | Requested | Actual | > Logic > | | | > Levels > -------------------------------------------------------------------------- -- > ---- > * TS_CLK20MHZ = PERIOD TIMEGRP "CLK20MHZ" | 50.000ns | 28.049ns | 11 > 50 nS HIGH 50.000000 % | | | > -------------------------------------------------------------------------- -- > ---- > > Sorry the spacing is kind of messed up. What it says is Requested period is > 50.000ns, and actual is 28.049ns. Is this supposed to mean that 28.049ns is > half my actual period? If not, I'd say I met the timing constraint, why is > it giving me an error? > Thanks, > Dave > > >Article: 35826
Thanks all. "Christoph Hauzeneder" <chauzen@t-online.de> wrote in message news:3BCF46B5.A8A7C076@t-online.de... > Hello, > > I have made my diploma thesis about FireWire. The problem is, that you need an > IEEE 1394 chipset, that is ideal for your application. > > If you will send data from an camera, then you can use link layers from philips, > because they have an port for audio and video signals. Also you can look at TI > and Fujitsu, Sony and NEC. > > Christoph > > Ben schrieb: > > > Hi all, > > I'm working on a university project invloving using Firewire (IEEE 1394) > > interfaces for input and output from an FPGA-based video processing board. > > The firewire will form a link from a DV camera to the board, and from the > > board to a PC/workstation. > > > > Does anyone have any reccomendations for physical layer interfaces and link > > layer controller devices? I've found the > > Altera IP for FPGA-based LLCs, but would prefer to have an external device > > if possible, as I need all the logic resources for other things. > > > > Also, has anyone else done this kind of thing before? If so, any > > hints/tips/links would be handy. > > > > Thanks, > > Ben. >Article: 35827
Theron Hicks wrote: > A second question comes to mind. I have a system with two boards. Each board > has one FPGA. Board 1 supplies _most_ but not all of the test signals for > board 2. I would like to use the output of board 1 as test vectors for board > 2. I am using web-pack. Is there a way to separately compile each FPGA and > yet use a single test bench to run the simulation? What about if I went to the > full version of the software? (i.e. Foundation ISE or equiv.)? I've simulated boards with multiple FPGAs using ModelSim. Basically, your "board" test bench instantiates each FPGA as a component, with whatever interconnects and other components are required. It's not a Web Pack issue at all. -aArticle: 35828
hi, I have this heirarchy ADD_mantissa in VHDL where i instantiate a 56 bit adder which inturn instantiates 1 bit adder, so the TOP level being add_mant. I am trying to map this circuit using xilinx alliance M1 tool, and I get the following errors. can someone tell me as to why such an error occurs and how it can be avoided, i tried various ways to avoid the same. the entity simulates/synthesises fine... the ERRORS are: temp_mant and mant_out are 56 bit slv and this error occurs for every pad net ERROR:basnu:142 - output pad net "mant_out36<56>" has an illegal connection ERROR:basnu:114 - logical net "temp_mant2<55>" has multiple drivers ERROR:basnu:114 - logical net "add_carry_in" has multiple drivers ERROR:basnu:142 - input pad net "add_carry_in" has an illegal connection ERROR:basnu:114 - logical net "to_start_adder" has multiple drivers ERROR:basnu:142 - input pad net "to_start_adder" has an illegal connectionArticle: 35829
Dave Brown wrote: > > I get the following Timing Constraint not met message: > > Asterisk (*) preceding a constraint indicates it was not met. > > ---------------------------------------------------------------------------- > ---- > Constraint | Requested | Actual | > Logic > | | | > Levels > ---------------------------------------------------------------------------- > ---- > * TS_CLK20MHZ = PERIOD TIMEGRP "CLK20MHZ" | 50.000ns | 28.049ns | 11 > 50 nS HIGH 50.000000 % | | | > ---------------------------------------------------------------------------- > ---- > > Sorry the spacing is kind of messed up. What it says is Requested period is > 50.000ns, and actual is 28.049ns. Is this supposed to mean that 28.049ns is > half my actual period? If not, I'd say I met the timing constraint, why is > it giving me an error? Are you using both edges of the clock? Half of 50 ns is 25 ns, and your "actual" 28 ns is 3 ns too long... --aArticle: 35830
Jack wrote: > Hi everyone. > I'm a software engineer and graduating soon for my MSEE. > I would like to make a career change to hardware design, since i'm > more interested in hardware design now after taking advanced computer > architecture courses, advanced logic design, and other hardware > related courses. > Also, I'm learning verilog and xilinx fpga now. > > What do you suggest me to learn specifically to land a job in > fpga/asic designer, especially for new guy like me? (such as, pci bus > design, risc machine, etc) > or any advice what to start, roadmap, and everything you can advice. > > Thanks so much. I'd appreciate any help. > > Jack Be careful - University courses are a few hundred parsecs from the real thing. Many years ago I came of of University and applied for a s/w job. During the interview it emerged that they had spotted on my CV some time I spent doing some simple minded digital h/w 7-8 years previously and more-or-less press ganged me into h/w. This was in the days when PALs were the red-hot bleeding edge of technology. To this day I sometimes wish I'd said *NO* but then some piece of h/w I've been sweating blood over suddenly comes to life and I forget just how hard this game is - till the next time.Article: 35831
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Yes. I have always liked that implementation of a PWM. Uses just one
up/down counter and one additional register. Unfortuantely, that app note
is a bit dated though and there are no HDL (VHDL or Verilog) files
availible for it and the schematic files do not work with the current
software and FPGA technologies. I did write that code into Verilog some
time ago though and will share it here for those intersted. Sorry no VHDL
but it is simple code and self-explanatory and should not be too difficult
to translate.
-- Brian
//
// PULSE_WIDTH_MODULATOR.V Version 1.0
// Pulse Width Modulation Circuit
// Addapted from "Pulse-Width Modulation
// in Xilinx Programmable Logic" application
// Brief, April 11, 1995
//
module pulse_width_modultor (pwm, duty_cycle, new_value, clk, reset);
input new_value, clk, reset;
input [7:0] duty_cycle;
output pwm;
reg pwm;
reg [7:0] dc, q;
always @ (posedge clk or posedge reset)
begin
if (reset)
dc <= 8'h00;
else if (new_value)
dc <= duty_cycle;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
q <= 8'h00;
else if (q)
q <= dc;
else if (pwm)
q <= q + 1;
else
q <= q - 1;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
pwm <= 1'b0;
else if (q)
pwm <= ~pwm;
end
endmodule
Manfred Kraus wrote:
> You may want to look at:
>
> Xilinx Application Brief: Pulse-Width Modulation in Xilinx Programmable
> Logic, application note, v0.2 (4/95)
> The design presented in this brief uses a register to store the desired
> 'mark' value, which is automatically loaded into a down counter upon
> reaching its terminal count. The PWM Frame Period is the product of the
> counter's clock period an...
> http://www.xilinx.com/appnotes/pwm.pdf
> (89632 bytes, Modified 10-03-2000)
>
> Hope this helps. Its not a VHDL design, but the block diagram on
> the last page should be easy to describe using VHDL.
>
> -Manfred
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<p>Yes. I have always liked that implementation of a PWM. Uses
just one up/down counter and one additional register. Unfortuantely,
that app note is a bit dated though and there are no HDL (VHDL or Verilog)
files availible for it and the schematic files do not work with the current
software and FPGA technologies. I did write that code into Verilog
some time ago though and will share it here for those intersted.
Sorry no VHDL but it is simple code and self-explanatory and should not
be too difficult to translate.
<p>-- Brian
<p><tt>//</tt>
<br><tt>// PULSE_WIDTH_MODULATOR.V Version 1.0</tt>
<br><tt>// Pulse Width Modulation Circuit</tt>
<br><tt>// Addapted from "Pulse-Width Modulation</tt>
<br><tt>// in Xilinx Programmable Logic" application</tt>
<br><tt>// Brief, April 11, 1995</tt>
<br><tt>//</tt><tt></tt>
<p><tt>module pulse_width_modultor (pwm, duty_cycle, new_value, clk, reset);</tt><tt></tt>
<p><tt> input new_value,
clk, reset;</tt>
<br><tt> input [7:0] duty_cycle;</tt><tt></tt>
<p><tt> output pwm;</tt><tt></tt>
<p><tt> reg pwm;</tt>
<br><tt> reg [7:0] dc, q;</tt><tt></tt>
<p><tt> always @ (posedge clk or posedge reset)</tt>
<br><tt> begin</tt>
<br><tt> if (reset)</tt>
<br><tt> dc <= 8'h00;</tt>
<br><tt> else if (new_value)</tt>
<br><tt> dc <= duty_cycle;</tt>
<br><tt> end</tt><tt></tt>
<p><tt> always @ (posedge clk or posedge reset)</tt>
<br><tt> begin</tt>
<br><tt> if (reset)</tt>
<br><tt> q <= 8'h00;</tt>
<br><tt> else if (q)</tt>
<br><tt> q <= dc;</tt>
<br><tt> else if (pwm)</tt>
<br><tt> q <= q + 1;</tt>
<br><tt> else</tt>
<br><tt> q <= q - 1;</tt>
<br><tt> end</tt><tt></tt>
<p><tt> always @ (posedge clk or posedge reset)</tt>
<br><tt> begin</tt>
<br><tt> if (reset)</tt>
<br><tt> pwm <= 1'b0;</tt>
<br><tt> else if (q)</tt>
<br><tt> pwm <= ~pwm;</tt>
<br><tt> end</tt><tt></tt>
<p><tt>endmodule</tt>
<br>
<br>
<p>Manfred Kraus wrote:
<blockquote TYPE=CITE>You may want to look at:
<p>Xilinx Application Brief: Pulse-Width Modulation in Xilinx Programmable
<br>Logic, application note, v0.2 (4/95)
<br>The design presented in this brief uses a register to store the desired
<br>'mark' value, which is automatically loaded into a down counter upon
<br>reaching its terminal count. The PWM Frame Period is the product of
the
<br>counter's clock period an...
<br><a href="http://www.xilinx.com/appnotes/pwm.pdf">http://www.xilinx.com/appnotes/pwm.pdf</a>
<br>(89632 bytes, Modified 10-03-2000)
<p>Hope this helps. Its not a VHDL design, but the block diagram on
<br>the last page should be easy to describe using VHDL.
<p>-Manfred</blockquote>
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Article: 35832Dave Brown wrote: > I get the following Timing Constraint not met message: > > Asterisk (*) preceding a constraint indicates it was not met. > > ---------------------------------------------------------------------------- > ---- > Constraint | Requested | Actual | > Logic > | | | > Levels > ---------------------------------------------------------------------------- > ---- > * TS_CLK20MHZ = PERIOD TIMEGRP "CLK20MHZ" | 50.000ns | 28.049ns | 11 > 50 nS HIGH 50.000000 % | | | > ---------------------------------------------------------------------------- > ---- > > Sorry the spacing is kind of messed up. What it says is Requested period is > 50.000ns, and actual is 28.049ns. Is this supposed to mean that 28.049ns is > half my actual period? If not, I'd say I met the timing constraint, why is > it giving me an error? > Thanks, > Dave You need to run the timing analyser to get details of the failing paths. If it is a double-edge clock problem as Andy Peters suggests then this will show up in the TRCE report.Article: 35833
Austin Lesea schrieb: > > Falk, > > Guten Tag! Moin. [Lots of good comments on jitter ] Uhh, I would better not mess around with the gods in this NG ;-)) Seriously, the statement regarding the "not so real measurements" is not originally from me. Sorry, I should have made this clear. It was absolutely NOT my intention to lower the performance of any design. -- MFG FalkArticle: 35834
Rick Filipkiewicz schrieb: > > Be careful - University courses are a few hundred parsecs from the real > thing. ;-))))))))) -- MFG FalkArticle: 35835
luigi funes schrieb: > > Generally, for a given device, there are many packages > with different pin counts. > But inside, is the chip always the same? AFAIK Yes. > If yes, if I'm using a package with fewer pins, could I > use the unbonded I/O cells as general purpose flip-flops? > How do it? Simpy use them as FlipFlops, create bidirectional signals in the entity, but Iam afraid that the P&R tools as well as bitgen will check your design and will notice that this IO pins are not available. Havnt done it yet, but it may be worth a try. -- MFG FalkArticle: 35836
Hello, I ask to tell me about BLIF to smth. convertors working in Windows 9x/2000. I'd prefer BLIF to Bool equations or VHDL convertors. What about free simulators for BLIF? Thanks, Alexander Chemeris chemeris@svitonline.comArticle: 35837
If the VHDL code actually reads a*b then it's a simple multiplier which should give a full resolution result. If you're working from a functional block that you don't have any details for, the designer may have done things in the code you wouldn't expect that might change the results ever so slightly. A multiplier can be implemented in an FPGA with dedicated multipliers, an FPGA with multiplier optimization to reduce the distributed resources, or as a simple and/add adder tree. How efficiently the multipiers are implemented can be dependent on the synthesis tool. The bottom line: VHDL will give you accurate results. The FPGA and synthesis tool may give you efficient implementation. The designer might pull some tricks. eas wrote: > Topi Maurola <tm@TopiSoft.fi> wrote in message news:<3BCDB981.B862976A@TopiSoft.fi>... > > Complex multiplication is needed only if mirror image is a problem. > > When you multiply a complex (I & Q) signal with complex oscillator (LO) ( > > cos(wt),sin(wt) or exp(i*w*t). w = 2*pi*lo_freq ), then the result is > > original signal sifted in frequency domain by lo_freq. If lo_freq is > > negative, then frequency of original signal is decreased and vice a versa. > > > > If you have complex signal and you multiply it with real local > > (cos(wt),0), then you are actually multilplying it with two district local > > signals lo_freq and -lo_freq. > > (cos(wt),0) = 0.5*(cos(wt),sin(wt)) + 0.5*(cos(wt),-sin(wt)) > > And result is convolution of original signal with these two district local > > signals, in frequency domain. > > That is, result is (original signal shifted up by lo_freq) summed with > > (original signal sifted down by lo_freq). Both in half amplitude. > > > > If you have real signal and you multiply it with real local oscillator, > > then result is of course real. > > In complex base we can write this: [ (a,b) is written as a+b*i (i is > > imaginary unit)] > > > > sig_in(t) * cos(wt) = sig_in(t) * (cos(wt) + 0*i) > > = sig_in(t) * (cos(wt) + (0.5*sin(wt) - 0.5*sin(wt))*i) > > = sig_in(t) * 0.5*(cos(wt) + sin(wt)*i) + sig_in(t)*0.5*(cos(wt) - > > sin(wt)*i) > > = sig_in(t) * 0.5*(cos(wt) + sin(wt)*i) + sig_in(t)*0.5*(cos((-w)*t) + > > sin((-w)*t)*i) > > > > Which is sig_in(t) sifted up & down by 2*pi*w herzs. > > > > BUT, because sig_in(t) is real, it is actually sum of positive and > > negative version of itself. So in complex base result can be interpreted > > to have 4 copies of sig_in(t) in different frequencies. > > If we interpret only absolute value of frequency (real signal) then we > > have only two different copies of sig_in(t), original_freq + 2*pi*w & > > original_freq - 2*pi*w. The proof is left as home exercise. > > > > If you can filter out unwanted mirror and other spurious signals, then the > > local oscillator can be as small as one bit. > > If we define that lo = '1' means value of one, and lo = '0' means value of > > minus one, then multipliction is: > > > > signal sig_in: std_ulogic_vector(7 downto 0); > > signal end_sig: std_ulogic_vector(7 downto 0); > > signal lo: std_ulogic; > > ... > > end_sig <= sig_in when lo = '1' else -sig_in. > > > > This works as following: > > > > Symmetric square wave (+1 / -1) of frequency freq (our lo signal) is sum > > of base frequency (freq), and all odd harmonic frequencies (3*freq, > > 5*freq, ...). Each with different amplituede (amplitude goes down as > > harmonic number increases). > > If we multiply sig_in with this square signal, then we are making > > convolution in frequency domain with these two signals. It means that > > original signal is copied to frequencies orig_freq + freq and orig_freq + > > 3*freq and orig_freq + 5*freq, etc. AND also copied to frequencies > > orig_freq - freq and orig_freq - 3*freq etc... > > > > If (when) your data is time quantised ( = samples), then frequencies going > > over sample_rate/2 (or under -sample_rate/2) are aliased back to > > -sample_rate/2...sample_rate/2. If these aliases are corrupting your > > original data => tough luck (use more bits with local!). > > [This is actually done in applications called undersampling. Let's say we > > have analog signal in frequency range 100 MHz ... 101 MHz.. And other > > frequencies are clean (zero). > > Then we can do analog-to-digital conversion with sample rate of 7 MHz > > (e.g.). This 7 MegaSamplesPerSecond contains original signal in frequncy > > range 2 MHz ... 3 MHz. > > 2 MHz + 14*7 Mhz = 100 MHz. > > This requires that ADC input frequency responce is upto at least 101 MHz.] > > > > Outch, this come out as a quite long text. If you don't grasp something, > > please fee free to ask for more explaining respond. > > > > -- > > Topi > > > > Thanks for your detailed response. I want to use the digital mixer in > a COSTAS LOOP where the input signal in the I or Q signal is > ak*cos(wt+alpha)+ bk*sin(wt+alpha). They are mixed/multiplied on the I > and Q arm and Lowpass filtered. The operation is clear to me. What I > dont know is how the multiplier is realized in VHDL? > Is it an ordinary 8x8 multiplier or are there any special > requirements? > > Thanks eas wrote: > Thanks for your detailed response. I want to use the digital mixer in > a COSTAS LOOP where the input signal in the I or Q signal is > ak*cos(wt+alpha)+ bk*sin(wt+alpha). They are mixed/multiplied on the I > and Q arm and Lowpass filtered. The operation is clear to me. What I > dont know is how the multiplier is realized in VHDL? > Is it an ordinary 8x8 multiplier or are there any special > requirements? > > ThanksArticle: 35838
This is a multi-part message in MIME format. ------=_NextPart_000_000A_01C15884.8C540B10 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Well, there is indeed a block that uses the negative edge of the clock, = and this is the path that fails timing. Below is an expert of what the = block that uses the negative edge is trying to do. I'd like to eliminate = the use of the negative edge of the clock. However, I think if I extend = the generated load pulse to 2 clk cycles, that won't work, then there = will be 3 potential edges where registers could load. Any ideas for a = work around? -- SYNCLD: = =20 -- = =20 -- Sent to all blocks to initiate a load of the addressed register.=20 -- This is a synchronous register load pulse. Pulse is one inverted CLK = pulse -- wide, centred about the noninverted CLK rising edge. =20 -- _______ _______ -- CLK __| |_______| |______ -- _______________ -- SYNCLD __________| |______ -- | =20 -- /|\ -- | -- Registers load at this edge Thanks for any help. Dave "Ray Andraka" <ray@andraka.com> wrote in message = news:3BD02004.E4B520AA@andraka.com... > You've got a path between registers using opposite edges of the clock = that > exceeds half the clock period. Run the timing analyzer to show the = details of > the failing path(s). Note that if you cannot guarantee a 50% clock = duty cycle, > then using both edges of the clock can be very dangerous. If the = clock duty > cycle is not 50%, or you can't guarantee that it is, then you need = additional > margin on your time constraints for paths between falling and risign = edge > registers (and vise-versa), which will require the use of from:to = constraints. >=20 > If this is a device that has a DLL and you set the DLL for duty cycle = correction > this is OK. If the clock comes from outside the device, even if it is = 50% duty > outside, you can't guarantee a 50% duty cycle inside the chip. The = input > thresholds will modulate the duty cycle if they are not perfectly = symmetric > about your high and low levels of the input signal. >=20 >=20 > Dave Brown wrote: >=20 > > I get the following Timing Constraint not met message: > > > > Asterisk (*) preceding a constraint indicates it was not met. > > > > = -------------------------------------------------------------------------= --- > > ---- > > Constraint | Requested | Actual = | > > Logic > > | | = | > > Levels > > = -------------------------------------------------------------------------= --- > > ---- > > * TS_CLK20MHZ =3D PERIOD TIMEGRP "CLK20MHZ" | 50.000ns | = 28.049ns | 11 > > 50 nS HIGH 50.000000 % | | = | > > = -------------------------------------------------------------------------= --- > > ---- > > > > Sorry the spacing is kind of messed up. What it says is Requested = period is > > 50.000ns, and actual is 28.049ns. Is this supposed to mean that = 28.049ns is > > half my actual period? If not, I'd say I met the timing constraint, = why is > > it giving me an error? > > Thanks, > > Dave >=20 > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com >=20 > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 >=20 >=20 ------=_NextPart_000_000A_01C15884.8C540B10 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY> <DIV><FONT face=3DCourier size=3D2>Well, there is indeed a block that = uses the=20 negative edge of the clock, and this is the path that fails timing. = Below is an=20 expert of what the block that uses the negative edge is trying to do. = I'd like=20 to eliminate the use of the negative edge of the clock. However, I think = if I=20 extend the generated load pulse to 2 clk cycles, that won't work, then = there=20 will be 3 potential edges where registers could load. Any ideas for a = work=20 around?</FONT></DIV> <DIV><FONT face=3DCourier size=3D2></FONT> </DIV> <DIV><FONT face=3DCourier size=3D2>--=20 SYNCLD: = &= nbsp; &n= bsp; &nb= sp; &nbs= p; =20 <BR>-- &= nbsp; &n= bsp; &nb= sp; &nbs= p;  = ; = =20 <BR>-- Sent to all blocks to initiate a load of the addressed register. = <BR>--=20 This is a synchronous register load pulse. Pulse is one inverted = CLK=20 pulse<BR>-- wide, centred about the noninverted CLK rising edge. =20 <BR>-- &= nbsp; =20 _______ =20 _______<BR>-- CLK=20 __| =20 |_______| =20 |______<BR>-- = =20 _______________<BR>-- SYNCLD=20 __________| &n= bsp; =20 |______<BR>-- = &= nbsp; =20 | = &= nbsp; =20 <BR>-- &= nbsp; &n= bsp; =20 /|\<BR>-- &nbs= p;  = ; =20 |<BR>-- = =20 Registers load at this edge</FONT></DIV> <DIV><FONT face=3DCourier size=3D2></FONT> </DIV> <DIV><FONT face=3DCourier size=3D2>Thanks for any help.</FONT></DIV> <DIV><FONT face=3DCourier size=3D2>Dave</FONT></DIV> <DIV><FONT face=3DCourier size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>"Ray Andraka" <</FONT><A=20 href=3D"mailto:ray@andraka.com"><FONT face=3DArial=20 size=3D2>ray@andraka.com</FONT></A><FONT face=3DArial size=3D2>> = wrote in message=20 </FONT><A href=3D"news:3BD02004.E4B520AA@andraka.com"><FONT face=3DArial = size=3D2>news:3BD02004.E4B520AA@andraka.com</FONT></A><FONT face=3DArial = size=3D2>...</FONT></DIV><FONT face=3DArial size=3D2>> You've got a = path between=20 registers using opposite edges of the clock that<BR>> exceeds half = the clock=20 period. Run the timing analyzer to show the details of<BR>> the = failing=20 path(s). Note that if you cannot guarantee a 50% clock duty = cycle,<BR>>=20 then using both edges of the clock can be very dangerous. If the = clock=20 duty<BR>> cycle is not 50%, or you can't guarantee that it is, then = you need=20 additional<BR>> margin on your time constraints for paths between = falling and=20 risign edge<BR>> registers (and vise-versa), which will require the = use of=20 from:to constraints.<BR>> <BR>> If this is a device that has a DLL = and you=20 set the DLL for duty cycle correction<BR>> this is OK. If the = clock=20 comes from outside the device, even if it is 50% duty<BR>> outside, = you can't=20 guarantee a 50% duty cycle inside the chip. The input<BR>> = thresholds=20 will modulate the duty cycle if they are not perfectly symmetric<BR>> = about=20 your high and low levels of the input signal.<BR>> <BR>> <BR>> = Dave=20 Brown wrote:<BR>> <BR>> > I get the following Timing Constraint = not met=20 message:<BR>> ><BR>> > Asterisk (*) preceding a constraint = indicates=20 it was not met.<BR>> ><BR>> >=20 -------------------------------------------------------------------------= ---<BR>>=20 > ----<BR>> > =20 Constraint &nb= sp; &nbs= p; =20 | Requested | Actual |<BR>> > = Logic<BR>>=20 > &nb= sp; &nbs= p;  = ; =20 | =20 | = |<BR>>=20 > Levels<BR>> >=20 -------------------------------------------------------------------------= ---<BR>>=20 > ----<BR>> > * TS_CLK20MHZ =3D PERIOD TIMEGRP = "CLK20MHZ" |=20 50.000ns | 28.049ns | 11<BR>> = > 50=20 nS HIGH 50.000000=20 % = =20 | =20 | = |<BR>>=20 >=20 -------------------------------------------------------------------------= ---<BR>>=20 > ----<BR>> ><BR>> > Sorry the spacing is kind of messed = up. What=20 it says is Requested period is<BR>> > 50.000ns, and actual is = 28.049ns. Is=20 this supposed to mean that 28.049ns is<BR>> > half my actual = period? If=20 not, I'd say I met the timing constraint, why is<BR>> > it giving = me an=20 error?<BR>> > Thanks,<BR>> > Dave<BR>> <BR>> = --<BR>> --Ray=20 Andraka, P.E.<BR>> President, the Andraka Consulting Group, = Inc.<BR>>=20 401/884-7930 Fax 401/884-7950<BR>> email = </FONT><A=20 href=3D"mailto:ray@andraka.com"><FONT face=3DArial=20 size=3D2>ray@andraka.com</FONT></A><BR><FONT face=3DArial size=3D2>> = </FONT><A=20 href=3D"http://www.andraka.com"><FONT face=3DArial=20 size=3D2>http://www.andraka.com</FONT></A><BR><FONT face=3DArial = size=3D2>>=20 <BR>> "They that give up essential liberty to obtain a = little<BR>>=20 temporary safety deserve neither liberty nor safety."<BR>>=20 &= nbsp; &n= bsp; &nb= sp; =20 -Benjamin Franklin, 1759<BR>> <BR>> </FONT></BODY></HTML> ------=_NextPart_000_000A_01C15884.8C540B10--Article: 35839
Priced for quick turnover VG condition Details upon request Tony Stein Alex VaArticle: 35840
Dave Brown wrote: > Well, there is indeed a block that uses the negative edge of the > clock, and this is the path that fails timing. Below is an expert of > what the block that uses the negative edge is trying to do. I'd like > to eliminate the use of the negative edge of the clock. However, I > think if I extend the generated load pulse to 2 clk cycles, that won't > work, then there will be 3 potential edges where registers could load. > Any ideas for a work around? -- SYNCLD: > -- > -- Sent to all blocks to initiate a load of the addressed register. > -- This is a synchronous register load pulse. Pulse is one inverted > CLK pulse > -- wide, centred about the noninverted CLK rising edge. > -- _______ _______ > -- CLK __| |_______| |______ > -- _______________ > -- SYNCLD __________| |______ > -- | > -- /|\ > -- | > -- Registers load at this edge Thanks for any > help.Dave It would appear that you are doing this to avoid hold-time problems on those registers that receive ``SYNCLD'' ? If so you don't really have to do this since, as long as you are using a global buffer for the clock distribution, hold-time is not an issue in Xilinx FPGAs for registers clocked from the same clock edge.Article: 35841
Falk Brunner wrote: > For anybody interested in some deadly glitches, have a look at > > www.burned-fuses.de > > beside the non-sense links ;-) you will find a link to the glitch datas. > But its still preliminary. > > -- > MFG > Falk Falk, Could you give a full reference for that ``Handbook of Black Magic'' ? It sounds like just the sort of thing to give to our s/w engineers as a Christmas present :-)Article: 35842
High-Speed Digital Design A handbook of black magic by Howard Johnson and Martin Graham 1993 Prentice Hall ISBN 0-13-395724-1 Cost about $ 70, and well worth it. Dr Johnson is a very lively speaker... But this is real HARDWARE stuff, and gory details... Peter Alfke ============================== Rick Filipkiewicz wrote: > Falk Brunner wrote: > > > For anybody interested in some deadly glitches, have a look at > > > > www.burned-fuses.de > > > > beside the non-sense links ;-) you will find a link to the glitch datas. > > But its still preliminary. > > > > -- > > MFG > > Falk > > Falk, > > Could you give a full reference for that ``Handbook of Black Magic'' ? It > sounds like just the sort of thing to give to our s/w engineers as a > Christmas present :-)Article: 35843
Rick, I can't resist. In 1978, I was responsible for a technical Lexicon that was distributed at some trade shows and seminars by Sybex Publishing (Rue LeCourbe, Paris). For fun, I defined a "glitch" as: "a snivitz with a magnitude of greater than 1000 volts." Later (in alphabetical order, of course) the "snivitz: a glitch with a magnitude of less than 1000 volts" was listed. The Lexicon was black, with silver or gold cover ink, roughly 5cm by 5cm square. If anyone can part with theirs? Austin Rick Filipkiewicz wrote: > Falk Brunner wrote: > > > For anybody interested in some deadly glitches, have a look at > > > > www.burned-fuses.de > > > > beside the non-sense links ;-) you will find a link to the glitch datas. > > But its still preliminary. > > > > -- > > MFG > > Falk > > Falk, > > Could you give a full reference for that ``Handbook of Black Magic'' ? It > sounds like just the sort of thing to give to our s/w engineers as a > Christmas present :-)Article: 35844
Here's the description on the author's web site: http://www.sigcon.com/books.htm Best book I've seen on the topic. Lots of other useful stuff on the site too. Rick Filipkiewicz wrote: <snipped> > > Could you give a full reference for that ``Handbook of Black Magic'' ? It > sounds like just the sort of thing to give to our s/w engineers as a > Christmas present :-) -- Tom Burgess -- Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 35845
Does any one know how to do the memory dump on Xilinx Block RAM? I am using Modelsim as my simulation software. I try to do this at RTL, Post-synthesis and Post-route simulation. Thank you Jack TaiArticle: 35846
On Fri, 19 Oct 2001 19:46:48 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote: >Could you give a full reference for that ``Handbook of Black Magic'' ? It >sounds like just the sort of thing to give to our s/w engineers as a >Christmas present :-) Howard Johnson's "High-Speed Digital Design" is a classic, and deservedly so. I used it as a text for several years in a signal integrity course I taught, and never had a single student say anything bad about it. Times have moved on, though, and issues that weren't terribly important in 1993 (when HSDD was published) are starting to bite us. An excellent, recently-published book is "High-Speed Digital System Design" by Hall, Hall, and McCall, ISBN 0-471-36090-2, John Wiley and Sons. If you're doing digital design, it deserves a place on your bookshelf. But I don't think the software engineers are going to like it much. Bob PerlmanArticle: 35847
Bob Perlman wrote: > On Fri, 19 Oct 2001 19:46:48 +0100, Rick Filipkiewicz > <rick@algor.co.uk> wrote: > <snip> > > But I don't think the software engineers are going to like > it much. > > Bob Perlman Its just that they are always complaining that what I do and the reasons I do it doesn't make sense to them. When I try to explain their eyes just glaze over after the first few minutes (*). More to the point I need to convince our board guy that when, for example, I utter the dreaded words ``clock skew'' I'm deadly serious and not just talking h/w Voodoo. Being able to point to a book or book(s) might help. I often think that signal integrity issues follow what I call the 1st law of Advertising after this quote from the MD of some company (appox.): ``I know that 60% of my advertising budget is wasted, what I don't know is which 60%''. (*) ``Any sufficiently advanced technology will appear to be magic to those not versed in it'' - Arthur C. Clark. (again approx.)Article: 35848
Austin Lesea wrote: > Rick, > > I can't resist. > > In 1978, I was responsible for a technical Lexicon that was distributed at > some trade shows and seminars by Sybex Publishing (Rue LeCourbe, Paris). > > For fun, I defined a "glitch" as: "a snivitz with a magnitude of greater than > 1000 volts." > > Later (in alphabetical order, of course) the "snivitz: a glitch with a > magnitude of less than 1000 volts" was listed. > > The Lexicon was black, with silver or gold cover ink, roughly 5cm by 5cm > square. If anyone can part with theirs? > > Austin > > The secret's out, now we know why Xilinx is so successful. If I saw this on a CV (U.S. = resume) it would be an instant hire, you'd be sitting at your new desk before the interview ended :-)).Article: 35849
Someone can help me? Thanks for all, Zoltan Rado
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