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Messages from 124250

Article: 124250
Subject: Re: sounds
From: "MikeJ" <mikej@fpgaarcade.nospam.com>
Date: Sun, 16 Sep 2007 14:22:02 GMT
Links: << >>  << T >>  << A >>

"Icky Thwacket" <it@it.it> wrote in message 
news:13eqdfqfmdvo662@corp.supernews.com...
>
> <carlmorada@gmail.com> wrote in message 
> news:1189939782.072927.66770@k79g2000hse.googlegroups.com...
>> hello to everyone,
>>
>> im a newbie in using spartan 3e kit...Is it possible for the spartan
>> 3e kit to store an audio sounds like wav file or mp3 file?
>>
>
>
> Let size of wav/mp3 file = x
>
> Let available RAM on spartan 3e kit = y
>
> if y >= x then yes, else no
>
Let size of FLASH = Z

if y >=x or y>= Z then yes, else no
...

I actually, turned a spartan 3e sample kit (the freebee one) into a sample 
player used in an old car a mate tool on a cross europe car rally.

About 30 samples were stored in 8 bit mono 22K in the flash (several 
minuites in total if I rememer correctly), and a phase accumulator used to 
play them at different pitches controlled by some dash mounted switches. A 
delta-sigma DAC inside the FPGA used an external resistor/cap filter feeding 
an integrated amp/horn speaker.
job done....
/MikeJ
www.fpgaarcade.com 



Article: 124251
Subject: Re: Beginner Advice (Languages, tools etc.)
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Mon, 17 Sep 2007 07:40:08 +1200
Links: << >>  << T >>  << A >>
RL wrote:
> Hi,
> 
> Please excuse me for sounding like I don't have a clue what I'm talking 
> about. I am here because I want to learn.
> 
> I have a project I have been working on that requires physical hardware. 
> I will be getting someone to assist with building the hardware, but it 
> will be up to me to programme it. Originally I was going to use a 
> microcontroller, as I have C programming experience. After further 
> investigation, I thought it would be a better idea to use an FPGA and do 
> it all in hardware. The functionality is mainly I/O related, so hardware 
> seems like a sensible choice.

What sort of IO ? - Microcontrollers are also designed for I/O related
tasks, and have many hardware peripherals for the common tasks.

Only when you hit a limit on a uC, should you look at FPGA.
Examples where a FPGA/CPLD is nessary might be if you need simultaneous 
changes on 80 IO lines, or a special 50MHz serial link, or
high bandwidth memory access.

Another approach is to start with a uC, and refine the design in uC/SW,
and then move whatever portion of the design needs HW to speed up.

For specialist uC look at devices like these
http://www.parallax.com/propeller/index.asp
http://www.innovasic.com/fido.htm

-jg


Article: 124252
Subject: Re: Physical Design Contribution to FPGA/CPLD success
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Mon, 17 Sep 2007 09:05:24 +1200
Links: << >>  << T >>  << A >>
acd wrote:

> CPLDs and FPGAs both make (or made) use of "non-standard"
> implementation
> of digital circuits, namely wired-OR and pass-transistors.
> Both techniques are much more difficult to use in standard cell ASICs
> or gate arrays.
> Therefore, one could argue  that the use of these methods reduced the
> area and speed
> overhead induced by the programmability.
> So while many ASICs that have been replaced by FPGAs  would not have
> used the methods,
> the CPLDs/FPGAs did.
> 
> How strong do you think was and is this effect?
> Would FPGAs have been successfull, if they had been implemented with
> vanilla CMOS gates and latches?
> Or better, how much smaller  the success story of FPGAs  would have
> been without the use of  pass transistors in LUTs and routing?

It's not clear what you mean by 'vanilla CMOS gates and latches' ?

CPLDs were quite different from FPGAs in structure, and Philips
were the leaders in 'true CMOS' CPLDs, which now sees 
Atmel/Lattice/Xilinx(via Philips) offering CMOS CPLDs.

FPGAs have always needed MUX elements (your pass-transistor)
as they have always had a routing element.

If you again look back at CPLDs, you will see above a certain size,
they also have recently moved to MUX/Tiled designs - so that gives
you the answer. Below a certain size, 'vanilla CMOS' makes sense,
and above that level, you need MUX's to stay efficent.

A factor in that branch, will also be the Software experience
that exists in FPGA design tools. Whilst there may possibly
have been another middle structure, the mature design flows in
the FPGA camp, made that jump natural for CPLDs.

-jg


Article: 124253
Subject: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Sun, 16 Sep 2007 17:26:42 -0700
Links: << >>  << T >>  << A >>
Hi,
I would like to pose an interesting guess topics for experienced
engineers:
What is the largest number of state machines in a current chip design:
1k, 10k or ...

I have finished 8 projects and only counted 27 state machines in one
of my biggest designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Weng


Article: 124254
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Uncle Noah <nkavv@skiathos.physics.auth.gr>
Date: Sun, 16 Sep 2007 17:36:54 -0700
Links: << >>  << T >>  << A >>
On Sep 17, 3:26 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> I would like to pose an interesting guess topics for experienced
> engineers:
> What is the largest number of state machines in a current chip design:
> 1k, 10k or ...
>
> I have finished 8 projects and only counted 27 state machines in one
> of my biggest designs.
>
> I may know the answer. The final result may surprise everyone who
> gives a guess.
>
> Weng


I am afraid as it stands your question does not make any sense.

These state machines:
1. How many states does each has?
2. State encoding, any associated datapath, operation?

BTW 27 is not a small number but the quality of your work
questionable. Maybe you could live with a smaller number of FSMs. I
just say that 27 doesn't say anything. 42 either ^_^

Nikolaos Kavvadias


Article: 124255
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Sun, 16 Sep 2007 17:55:05 -0700
Links: << >>  << T >>  << A >>
On Sep 16, 5:36 pm, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote:
> On Sep 17, 3:26 am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > Hi,
> > I would like to pose an interesting guess topics for experienced
> > engineers:
> > What is the largest number of state machines in a current chip design:
> > 1k, 10k or ...
>
> > I have finished 8 projects and only counted 27 state machines in one
> > of my biggest designs.
>
> > I may know the answer. The final result may surprise everyone who
> > gives a guess.
>
> > Weng
>
> I am afraid as it stands your question does not make any sense.
>
> These state machines:
> 1. How many states does each has?
> 2. State encoding, any associated datapath, operation?
>
> BTW 27 is not a small number but the quality of your work
> questionable. Maybe you could live with a smaller number of FSMs. I
> just say that 27 doesn't say anything. 42 either ^_^
>
> Nikolaos Kavvadias

Hi NK,
The guess is about what the largest number of state machine a current
chip may contain is.

It doesn't ask how many states each state machine has or what coding
method is used.

Just guess the largest number of state machine in a current chip
design.

It is not an easy guess, because your experiences may fall short of
imagination.

Why I listed 27 state machines is I used to make a wrong guessing
about the number, only based on my experiences with digital designs. I
guess most of experienced engineers may have the same experiences as I
had.

Weng


Article: 124256
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Andrew FPGA <andrew.newsgroup@gmail.com>
Date: Sun, 16 Sep 2007 21:44:42 -0700
Links: << >>  << T >>  << A >>
27 is far too little. I reckon its more like a billion state machines,
or perhaps a bit more these days. Asics and FPGAS(?) can have more
than a billion transistors. A transistor can have at least 2 states
(on or off), so I suppose you can say a transistor is a state machine.

http://www.intel.com/technology/mooreslaw/


Article: 124257
Subject: Unexplained behavior with DDR2 controller on Xilinx V5
From: "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com>
Date: Mon, 17 Sep 2007 09:50:16 -0000
Links: << >>  << T >>  << A >>
Hi,

I'm working on a custom DDR2 controller on Virtex 5 and I have a very
weird behavior that I can't explain.
I'm doing my tests on a SO-DIMM of which I only use 8 bits and running
it at 200 MHz. My controller uses
the ISERDES / OSERDES so that it only runs at 100 MHz and expose a 32
bits data interface to the user.

The problem is that the first word of a write burst is corrupted.

The weird part is that depending on the reset/power-up, either it
works fine, or it fails. That is, I reset the board, then either the
controller works OK and it will stay OK indefinitly. Or it exhibit the
problem and it will continue to show the same problem until reset.

So for example the test I'm running in loop is :

- Write 0x01234567 to 0x0000
- Write 0x89abcdef to 0x0004
- Write 0x02468ace to 0x0008
- Write 0x13579bdf to 0x000c
- Write 0x600dbabe to 0x0010
- Pause
- Write 0xf05a3c7d to 0x0008
- Pause
- Read 0x0000
- Read 0x0000
- Read 0x0004
- Read 0x0008
- Read 0x000c
- Read 0x0010
- Read 0x0010

So I write some known words in burst, then overwrite the middle word
with another in a single write, then reread the whole burst (but
reading the first and last word twice).

The results are :
 - Either every thing is fine
 - or, at 0x0000 I read 0x3c7d4567 (instead of 0x01234567) during both
reads
   and at 0x0008  I read 0xf05af05a (instead of 0xf05a3c7d)


My problem is that I don't see what in my code could cause that kind
of problems because I have nothing clocked at clk_2x ... I just
provide 4 bits in // to the serdes and let it do the job.


Sylvain


Article: 124258
Subject: global clock on virtex5 question
From: vasile <piclist9@gmail.com>
Date: Mon, 17 Sep 2007 12:24:32 -0000
Links: << >>  << T >>  << A >>
Hi to everybody,

I'ts not very clear from the Virtex 5 User guide, Clock resources
chapter if it's possible to route (on different GCLK inputs) single
ended and differential CLKs. Then at configuration time use either the
single ended clock (routed at the P side of the differential input
pair) or differential clock (say LVDS clock).

User manual say: "The 20 global clock pins on Virtex-5 devices can be
connected to 20 differential or 20 singleended board clocks"
page20-21  and "Each clock input can be either single-ended or
differential" page 20. That means only either single ended either
differential clock is allowed?

The second question is about differential clocks routed to XY  GTP
transcievers. Can those be used safely as GCLK or RCLK for the GTP
opposite banks (banks far away from the GTPs) or an outer clock must
be routed on PCB?

thx,
Vasile


Article: 124259
Subject: ECP2/M und Serdes
From: Martin Sauer <msauer@gmx.org>
Date: Mon, 17 Sep 2007 14:46:41 +0200
Links: << >>  << T >>  << A >>
Hello,

do have anyone expierence with the SERDES in the lattice ECP2/M family?

bye

martin sauer

Article: 124260
Subject: Re: post translate and post PAR problems with XST and Modelsim
From: Gabor <gabor@alacron.com>
Date: Mon, 17 Sep 2007 07:13:49 -0700
Links: << >>  << T >>  << A >>
On Sep 14, 1:56 pm, alle...@gmail.com wrote:
> I am trying to do a Virtex4 design, I have completed the post
> synthesis (XST) simulations in Modelsim - everything appears fine.
> When I run the PAR and simulate the generated model. I get all zeros
> on the output. None of the registers in the desing appear to be
> loading. I have specified the timing constraints for the period of the
> clock (only that constraint). Is there something I may be forgetting
> to do? My desing is runnig at 125Mhz.
>
> Thanks


The post P&R simulation model contains a GSR (global set/reset)
signal which defaults to 100 nS assertion after power-on and
overrides all other logic set/reset functions.  If your stimulation
relies on logic to be function before this 100 nS period is over,
you can have problems.  If you don't want to change your stimulus
it is possible to driver the GSR signal yourself to reduce the
pulse width.

HTH,
Gabor


Article: 124261
Subject: Re: Virtex-4 PCB design
From: Gabor <gabor@alacron.com>
Date: Mon, 17 Sep 2007 07:24:30 -0700
Links: << >>  << T >>  << A >>
On Sep 13, 7:26 pm, cstring...@yahoo.com wrote:
> Xilinx posts gerber file in *.pho format on their website for all of
> the evaluation boards.  Does anyone no how to import these into
> cadence OrCad? or what tool they used to design them in?
> Thanks,


Gerber files are like printouts.  They were designed to run X/Y photo-
plotters.  There are a number of Gerber file viewers available on the
web, some of them are free.  It is also possible to generate a
netlist from a set of Gerbers, but you won't have meaningful net
names unless they were embedded in the files.  It is unlikely that
you can get back the design database from the Gerber files.  This
is a little like trying to get source code from a .bit file in
an FPGA.

The .pho file extension (for photoplot) may indicate that the
design database was PADS.  AFAIK there is no common standard for
filename extension of gerber files, although the file format
itself is well defined (usually RS-274X).

I use a viewer from pentalogix called ViewmasterEZ, which is not
free, but it is cheap.  It allows editing of Gerber files as well
as some rudimentary design-rule checking.  This sort of tool is
extremely useful if you design PCB's, because there is often a
"disconnect" between the design database and the final deliverables
for laminate fabrication.  One of the other engineers here uses
a package called Gerbtool (IIRC) and that one has more features
including netlist generation.

HTH,
Gabor


Article: 124262
Subject: Re: clock skew problems
From: Gabor <gabor@alacron.com>
Date: Mon, 17 Sep 2007 07:32:48 -0700
Links: << >>  << T >>  << A >>
On Sep 12, 8:44 am, michel.ta...@gmail.com wrote:
> Hi,
>
> I found the pin list, and all pins are named like .ICLK
> The two pins which have a different name are inputs of two BUFGMUX.
> It seems to be matching with my ISE warning  (  my_clock may have
> excessive skew because 2 NON-CLK pins failed to route using a CLK
> template ).
> But there is something I don't understand.. I used BUFGMUX primitive
> to avoid clock problems and to keep my_clock on the global clock
> network.
> Does it mean that I can't connect a clock on a BUFGMUX input ? so, how
> can I do to multiplex clocks keeping my_clock on a global clock
> network to avoid skew problems ?
>

The input to a BUFGMUX is not on the global clock trees.  Normally
it would be fed by standard routing if the clock is generated inside
the FPGA, or dedicated routing from a DCM or a global clock input
buffer.  In any case the BUFGMUX itself has a significant delay and
therefore it is not reasonable to expect the output of a BUFGMUX
to have low skew compared to its input.  If you need the multiplexed
clocks to have low skew compared with a non-multiplexed clock, you
need to place the same signals on the BUFG and BUFGMUX inputs,
and you need to use BUFG and BUFGMUX on the same edge of the chip.
Generally there is no problem routing dedicated clock sources to
more than one BUFGMUX.  The FPGA editor can give you a better
view of the routing and timing.

HTH,
Gabor

> Thanks by advance,
>
> Best regards, Michel.
>
> On 6 sep, 12:51, Joseph Samson <u...@not.my.company> wrote:
>
> > michel.ta...@gmail.com wrote:
> > > Hi all,
>
> > > I've got a FPGA design with a lot of clocks!
> > > ISE
> > > gives me warnings :
> > > Route:447  - CLK Net : my_clock may have excessive skew because 2 NON-
> > > CLK pins failed to route using a CLK template. ( I've this warning for
> > > a lot of others clock generated by combinatorial logics... )
>
> > > My question is how can I locate the 2 NON-CLK pins
>
> > Use FPGA Editor to open the routed design.
> > Find the clock net and highlight it.
> > Press F2, or select Edit -> Properties of Selected Items...
> > Choose the 'Pins' tab.
> > You will see a list of all the pins on that net.
> > Scroll down the list until you find pins that don't have .CLK (or some
> > variant like .ICLK1 or .CLKA) in their name.
>
> > ---
> > Joe Samson
> > Pixel Velocity



Article: 124263
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Tricky <Trickyhead@gmail.com>
Date: Mon, 17 Sep 2007 08:19:53 -0700
Links: << >>  << T >>  << A >>
On Sep 17, 1:55 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Sep 16, 5:36 pm, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote:
>
>
>
> > On Sep 17, 3:26 am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > Hi,
> > > I would like to pose an interesting guess topics for experienced
> > > engineers:
> > > What is the largest number of state machines in a current chip design:
> > > 1k, 10k or ...
>
> > > I have finished 8 projects and only counted 27 state machines in one
> > > of my biggest designs.
>
> > > I may know the answer. The final result may surprise everyone who
> > > gives a guess.
>
> > > Weng
>
> > I am afraid as it stands your question does not make any sense.
>
> > These state machines:
> > 1. How many states does each has?
> > 2. State encoding, any associated datapath, operation?
>
> > BTW 27 is not a small number but the quality of your work
> > questionable. Maybe you could live with a smaller number of FSMs. I
> > just say that 27 doesn't say anything. 42 either ^_^
>
> > Nikolaos Kavvadias
>
> Hi NK,
> The guess is about what the largest number of state machine a current
> chip may contain is.
>
> It doesn't ask how many states each state machine has or what coding
> method is used.
>
> Just guess the largest number of state machine in a current chip
> design.
>
> It is not an easy guess, because your experiences may fall short of
> imagination.
>
> Why I listed 27 state machines is I used to make a wrong guessing
> about the number, only based on my experiences with digital designs. I
> guess most of experienced engineers may have the same experiences as I
> had.
>
> Weng

The most state machines any design can have is the same as the number
of registers available on the design. Each register could be counted
as a 2 state FSM. so in todays FPGAs, there are is a maximum of
somewhere in the hundreds of thousands of FSMs.


Article: 124264
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 17 Sep 2007 16:49:02 +0100
Links: << >>  << T >>  << A >>
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message 
news:1189988802.612765.289620@50g2000hsm.googlegroups.com...
>
> Weng
>

IF OP = "Weng Tianxiang" AND group = comp_arch_fpga THEN
  be_prepared_for_a_long_thread;
ORIF crossposted = to_comp_lang_vhdl THEN
  this_could_go_on_all_week;
ANDIF both_the_above THEN
  make_that_a_month;
BUTIF plonk! THEN
  blessed_relief;
ELSIF experiences < imagination THEN
  OP_question <= not(sense);
ELSE
  possibly_on_topic;
END IF;

HTH., Syms. ;-)

p.s. Sorry, couldn't resist it!

p.p.s. I guess one. You can view the whole FPGA as one big state machine. Do 
I win 5? 



Article: 124265
Subject: Re: overloading ' operators in VHDL
From: "RCIngham" <robert.ingham@gmail.com>
Date: Mon, 17 Sep 2007 11:20:12 -0500
Links: << >>  << T >>  << A >>
>Is it also possible to overload the attribute operators like: 'high,
>'left, 'low, ..? Is it possible to create your own attributes?
>
Yes, it is possible to create new ones and possibly to overload existing
ones, but probably not worth it. The attributes are added to the database
and used by software tools that process it, for instance physical
implementation tools. Various of these come with a set of tool-specific
attributes that you can use as directives. Not sure whether simulators
will do useful things with user-defined attributes...



Article: 124266
Subject: Re: VCCAUX too high on a Spartan 3 design
From: "Dan K" <danielgkNOSPAM@visi.com>
Date: Mon, 17 Sep 2007 11:28:54 -0500
Links: << >>  << T >>  << A >>

"vasile" <piclist9@gmail.com> wrote in message 
news:1189669145.788124.243100@50g2000hsm.googlegroups.com...
> On Sep 7, 7:54 pm, Peter Alfke <pe...@xilinx.com> wrote:
>> Hi John.
>> That's what I suggested in my posting yesterday.
>> "Great minds think the same way"  :-)
>> Peter Alfke
>>
>> On Sep 7, 9:29 am, John Larkin
>>
>>
>>
>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> > On Thu, 6 Sep 2007 17:23:39 -0500, "Dan K" <danielgkNOS...@visi.com>
>> > wrote:
>>
>> > >Using linear adjustable regulators for VCCINT (1.25v), VCCIO (3.3v), 
>> > >and
>> > >VCCAUX (2.5v).  VCCINT and VCCIO are dead on, but VCCAUX is 2.72v, 
>> > >2.88v,
>> > >and 2.92v on the 3 boards I grabbed and measured.  All boards seem to 
>> > >work
>> > >just fine.
>>
>> > >The regulator output voltage is controlled by just 2 resistors.  When 
>> > >I
>> > >changed one of the resistors to lover the voltage a bit, VCCAUX did 
>> > >not
>> > >change.  This leads me to believe that VCCAUX is somehow being "back"
>> > >powered from the Xilinx chip.  These voltages are present like this 
>> > >before
>> > >the Xilinx chip has been programmed.  I have not removed the regulator 
>> > >to
>> > >measure current yet.  Another thought was to put a shotkey diode 
>> > >between the
>> > >regulator output and the load to see if the Xilinx really is powering
>> > >VCCAUX, but I thought I'd post and see if anyone else has come across 
>> > >this
>> > >issue.  Half the I/O banks are 2.5v and half are 3.3v if that makes 
>> > >any
>> > >difference.
>>
>> > >Thanks - Dan
>>
>> > Try adding a "dump" resistor from Vccaux to ground, and see if that
>> > pulls the voltage down.
>>
>> > John- Hide quoted text -
>>
>> - Show quoted text -
>
> I'm curious if the original poster has solved the problem in the
> indicated way above.
> I have a design with Stratix II which has the same behaviour.
>
> thx,
> Vasile
>
Yes, that was the problem.  I had the M0, M1, and M2 pins connected to +3.3 
v.  As soon as they were disconnected from 3.3v and connected to 2.5v the 
2.5v power supply was right on.

Dan 




Article: 124267
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Mon, 17 Sep 2007 09:57:24 -0700
Links: << >>  << T >>  << A >>
Hi,
I don't say how many state machines a design CAN or MAY generate, but
I say GUESS what the largest number of state machines a real design
ACTUALLY HAS GENERATED and those state machines are critical, not
trivial in design functions.

The problem core is how you know other people's design internal
affairs?

You may not have a chance to generate so many state machines and you
may not have the knowledge about why there are so many state
machines.

I guess less than 27 engineers in the world who have a chance to do
the designs and have the experiences.

All who have responded to the post so far seem to be no knowledge
about it and just missed the target.

Weng


Article: 124268
Subject: Re: Guess: what is the largest number of state machines in a current
From: Philip Potter <pgp@doc.ic.ac.uk>
Date: Mon, 17 Sep 2007 18:03:42 +0100
Links: << >>  << T >>  << A >>
Weng Tianxiang wrote:
> I would like to pose an interesting guess topics for experienced
> engineers:
> What is the largest number of state machines in a current chip design:
> 1k, 10k or ...
> 
> I have finished 8 projects and only counted 27 state machines in one
> of my biggest designs.
> 
> I may know the answer. The final result may surprise everyone who
> gives a guess.

As others have said, how do you define a state machine? Is an SRAM bit a state 
machine? They fit quite a few of them onto a chip these days...

(followups set to remove crosspost)

-- 
Philip Potter pgp <at> doc.ic.ac.uk

Article: 124269
Subject: Re: Beginner Advice (Languages, tools etc.)
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Mon, 17 Sep 2007 10:10:57 -0700
Links: << >>  << T >>  << A >>
Hi - 

On Sun, 16 Sep 2007 08:04:18 +1200, RL <rl@null.void.test> wrote:

>Hi,
>
>Thanks to everyone who responded. I'm still undecided on which path to 
>take for this particular project, but I've spent about two hours so far 
>going through a VHDL tutorial. It is starting to make sense, so at least 
>I will have a better idea of what is going on in the rest of the hardware.
>
>A few comments for Bob below...
>
>> Mike Treseler has already addressed the issue of whether a
>> microcontroller solution might not be more suitable (I suspect it is),
>> so I'll set that aside.
>
>I should have mentioned, I am driving this development, and from my 
>point of view spending six months refining my VHDL skills wouldn't be a 
>major issue if the end result is going to justify this.
>
>> There's one issue that's more important than languages, tools, and the
>> like, to wit:
>> 
>> Do you know how to do digital design?  In particular, 
>> 
>>  - Do you know the principles of synchronous logic design?
>>  - Do you know how to reliably initialize a digital circuit?
>>  - Do you know how to analyze a timing path?
>>  - Do you know how to move signals between mutually asynchronous clock
>> domains?
>>  - Do you know how to handle digital signals at the FPGA I/O?  Do you
>> understand the fundamentals of different digital interface standards?
>> (I'm talking about the simple stuff, like what qualifies as a valid
>> HIGH or LOW for a 3.3V logic signal, or how to interface a 5V domain
>> to a 3.3V domain).  Do you know how to use signal terminations to
>> guarantee good signal quality?
>> 
>> And I'm just scratching the surface.
>> 
>> You are embarking on a hardware design, not a programming exercise.
>> Hardware design skills are essential, no matter what the SystemC
>> brochure says.
>
>I may be completely wrong about this, so feel free to comment.
>
>My intention is to only work on what is going on internally within the 
>FPGA (or CPU), and only the core logic to make it do what it has to do. 
>The actual interfacing to other electronic components will be handled by 
>someone with more knowledge than myself. I will be mainly concerned with 
>the internal logic of what happens when external events occur (in this 
>case, button presses, serial communications, and one clock).

Do you plan to review this person's design?  If so, you'll need to be
conversant with the I/O-related issues I mentioned above.

>Any electronics knowledge I once had was a decade ago, so I'm starting 
>out with very little. From a point of view of interpreting the input and 
>getting the output I want, dealing only with 0s and 1s, I don't think 
>I'm taking on too much.
>
>If I use a CPU, I need to read and write binary values that the 
>supporting electronics has to handle. If I used VHDL, I need to design 
>hardware to do certain things when values change, and set output 
>accordingly. The approaches are different, but taking the black box 
>approach, inputting and outputting binary values, both should work 
>equally well.
>
>I can see some major advantages doing this in VHDL. Yes, I have more to 
>learn, but I wouldn't have to worry about interrupts and race 
>conditions. In theory, and again I may be wrong, I should be able to be 
>more confident that the FPGA does what I expect, when I expect it to.

The fact that you'll be working within the confines of an FPGA does
simplify things somewhat, but it's by no means a get-out-of-jail-free
card.  It's like being at the beach: you have a lot of sand, and you
can build a beautiful castle, or something that looks like you just
filled up a pail and overturned it.  

Here's one example of the problems you'll have to deal with.  You have
a single clock, some button inputs, and a serial link or links.  The
serial links are probably asynchronous to the clock, and the button
pushes most certainly are.  How do you take these asynchronous signals
and synchronize them to your clock domain safely and reliably?  The
FPGA gives you the raw materials with which to craft a good circuit,
but it's not automatic: you have to design a solution.

>> Maybe this is coming across as unduly harsh; that's not my intent. All
>> of us hardware designers were newcomers at one point, so folks
>> starting out in hardware design today deserve our support.  But I'd
>> really, really like to drive a stake in the heart of the "designing
>> FPGAs is programming" meme.
>
>This is actually part of the reasoning behind selecting VHDL in 
>preference to SystemC. With SystemC, I could see there would be a 
>tendency to fall back to the familiar style of programming used for 
>software development. Hardware is a completely different concept and 
>should be treated as such.

VHDL is nothing more than a means of describing your logic design.
Yes, the synthesizer will do some of the low-level scut work, like
reducing Booleans expressions.  But when all is said and done, you
still have to do the design.

If you decide to proceed with the FPGA design, Eric Crabill's SJSU
course is an excellent introduction.  You can find the presentations
here:

http://www.engr.sjsu.edu/crabill/

Good luck,
Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com

Article: 124270
Subject: Altera / Lattice / Xilinx CPLDs ?
From: "Amontec, Larry" <laurent.gauch@ANTI-SPAMamontec.com>
Date: Mon, 17 Sep 2007 19:14:53 +0200
Links: << >>  << T >>  << A >>
Hi

We are searching a small CPLD gate count like a coolrunner 128.

- Two IO banks 1.4V to 3.3V with 5V tolerant
- VCC should be 3.3V or 1.8V

The 5V tolerant is important !

Volume : 5000 - 10000 pces

Any CPLDs ?

Regards,
Laurent


Article: 124271
Subject: Re: global clock on virtex5 question
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Mon, 17 Sep 2007 10:39:43 -0700
Links: << >>  << T >>  << A >>
vasile wrote:
> Hi to everybody,
> 
> I'ts not very clear from the Virtex 5 User guide, Clock resources
> chapter if it's possible to route (on different GCLK inputs) single
> ended and differential CLKs. Then at configuration time use either the
> single ended clock (routed at the P side of the differential input
> pair) or differential clock (say LVDS clock).
> 
> User manual say: "The 20 global clock pins on Virtex-5 devices can be
> connected to 20 differential or 20 singleended board clocks"
> page20-21  and "Each clock input can be either single-ended or
> differential" page 20. That means only either single ended either
> differential clock is allowed?
> 
> The second question is about differential clocks routed to XY  GTP
> transcievers. Can those be used safely as GCLK or RCLK for the GTP
> opposite banks (banks far away from the GTPs) or an outer clock must
> be routed on PCB?
> 

You are misinterpreting the documentation.  A clock circuit is made
up of multiple resources including an package input pin (IBUF or IBUFDS),
an optional DCM or PLL and a global clock tree (BUFG).

The paragraph that you quoted was discussing that the package input pin
could be either single ended (LVCMOS, SSTL, HSTL, etc) or differential
(LVDS).  These package pins would be connected to a physical on board
clock device that outputs a specific signaling standard.  A

The MGTREFCLK input pins are intended only for use with the RocketIO
transceivers.  These can be driven into the array, but it must be done
through an instantiated RocketIO and the only allowed connection from
here is to a BUFG.  It is not recommended to use these pins for anything
other than RocketIO based designs.  In particular you would not want to
use these pins for system synchronous designs as the timing is not the
same as defined clock input pins.

Ed McGettigan
--
Xilinx Inc.

Article: 124272
Subject: Re: Altera / Lattice / Xilinx CPLDs ?
From: austin <austin@xilinx.com>
Date: Mon, 17 Sep 2007 10:53:12 -0700
Links: << >>  << T >>  << A >>
Laurent,

5V tolerance may be easily achieved by using external series resistors
on the IO pins.

Is this OK?

Then, you may choose Altera, Lattice, or Xilinx solutions.

Austin

Article: 124273
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Mon, 17 Sep 2007 11:03:47 -0700
Links: << >>  << T >>  << A >>
Hi,
OK, a state machine is defined by standard one process or two
processes in VHDL.

There is no short cut.

It can be implemented in anywhere in a design and where the state
machine is located is decided by compilers and beyond the interest of
this topics.

I have to expand the guess to include Verilog group people, because
VHDL people may have no chance to do the designs.

I may know the answer. The final result may surprise everyone who
gives a guess.

Thank you.

Weng


Article: 124274
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: Shannon <sgomes@sbcglobal.net>
Date: Mon, 17 Sep 2007 18:14:15 -0000
Links: << >>  << T >>  << A >>
On Sep 17, 11:03 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> OK, a state machine is defined by standard one process or two
> processes in VHDL.
>
> There is no short cut.
>
> It can be implemented in anywhere in a design and where the state
> machine is located is decided by compilers and beyond the interest of
> this topics.
>
> I have to expand the guess to include Verilog group people, because
> VHDL people may have no chance to do the designs.
>
> I may know the answer. The final result may surprise everyone who
> gives a guess.
>
> Thank you.
>
> Weng

Ok Weng,

Since you obviously don't understand the questions the people who have
responded...

let's define a state machine as a process or processes that have a
classic "state variable".  Sigh...
Furthermore since you rejected the concept that our guess should not
be based on what is "possible" but instead on what has actually been
done...

I will answer you question that ***I*** have created the design that
has the most classic state machines in it.  And since you know the
answer you will tell ***me** how many I had to use.  Hint:  It's more
than 27 and I know you ***will*** be surprised by the answer!

Shannon




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