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Hi all, When do Formal Equivalent Check (RTL and Gate Level) , I remember that the tool compare the comb logic between D-FF . But when synthesis use re-timing and gated clock, can LEC tool compare RTL and Gate? And is gated clock one form of re-timing? I am reading a paper from SNUG about gated clock (How to successfully use gated clock...) but I cannot understand the waveform... Best regards, DavyArticle: 111551
NigelE wrote: > Davy wrote: > > Hi NigelE, > > > > Thanks a lot! I mis-understand virtual interface. > > > > Is there any web seminar or online video talk about AVM? That I want to > > understand AVM more clearly. > > > > Best regards, > > Davy > > > > Hi Davy > > Try a look at > > http://www.mentor.com/products/fv/events/ > > You'll find listed in the online events, our recent 'Hitchhikers Guide > to Verification' seminar that covers AVM and other SV verification > topics. > > It's split into 5 sessions so you don't need to watch it all at once ;) > > Best regards > > - Nigel Hi Nigel, Thanks a lot for the help! Best regards, DavyArticle: 111552
KJ, is it so difficult for two reasonably intelligent engineers to communicate ? We are forced to be very efficient (small size) and very (fast high clock rate), that's what the market demands. Sacrificing performance by adhering to one or another of the so-called interface standards is, at best, our second or third priority. You may not like it, others do. 'nough said. Peter Alfke On Nov 5, 3:08 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > "Peter Alfke" <a...@sbcglobal.net> wrote in messagenews:1162698535.527609.266650@f16g2000cwb.googlegroups.com...> Well, KJ, first of all, tone down, and dont second-guess how much I can > > grasp. > > "Peter Alfke goes off on his rant about his X's hard coded fifo runs at > > 550 > > MHZ but doesn't seem to grasp the fact that he is talking about > > performance > > and that that hard coded fifo is implementing the EXACT SAME FUNCTION."I call them as I see them. You were the one who several times went on with > the sales pitch on the 550 MHz fifo when we were talking about interface > standardization, not performance. > > > I have designed FIFOs over a longer time period than anybody else in > > the world, for I created the world's first IC FIFO design in 1970, the > > Fairchild 3341. So much for credentials...Good, now let's move on. > > > > > When we put a HARD FIFO into the Virtex-4 and Virtex-5 devices, we > > realized that it had to be fully functional, fast and small, for every > > BlockRAM is "burdened" with it. And once the transistors are > > implemented on the chip, there is nothing that can be changed or taken > > away, and any additional circuitry in the fabric would reduce > > performance significantly. (There was, unfortunately, a subtle error in > > the Virtex-4 implementation that forced us to come up with a > > work-araound. We did not repeat that mistake inVirtex-5).Even now, instead of actually responding to anything that I had posted you > are rambling on about things that Xilinx has done inside the various X > products. It reads again like a sales pitch, give it a rest....the > relevance of what you have to say to my post is completely missing.....maybe > you intended this for some other post, who can tell? > > > We had talked to many customers and listened to their ideas. That's why > > there are not only programmable "ALMOST" full or empty flag, there isI'm thinking that the programmable flags idea came not so much from > listening to customers but from the discrete fifos that existed long before > in the industry that also had 'programmable' flags. A bit of digging > would've led you to that what most customers really needed was not > programmability of the flag levels but being able to specify as a generic > parameters the fifo fill level and how many flags were needed. The discrete > IC fifo guys couldn't really do this so they had to make it programmable, > but in the soft IP world of CPLD/FPGAs you could....but instead chose to > copy industry parts. Maybe that's a good decision, maybe not but I'll bet > not having run-time programmability is acceptable in most situations. For > the others, this would be a different function (different entity). > > > We designed the FIFO to be fast and small, with a comprehensive and > > intuitive user interface.Fifo interfaces are all pretty intuitive, so why does X not support the > lpm_fifo interface? Is it not intuitive? > > > Are clock-multiplexers > > standardized? How's about DCMs and PLLs, and IDELAY and ODELAY > > fine-tuning circuits, and even multiplier/accumulators. Of course not, > > none do!Why not? As a user I want to multiply and divide clock frequency, skew them > if necessary and possibly mux them together. Sounds like something that can > be standardized to me. Toss in standardization of the various memory > controllers as well while you're at it since the memory devices are > standardized. Remember what standardization means....interchangable with > somebody else equivalent function. > > > Inside the chip we optimize the circuitry, and we are running way ahead > > of standardization.That's your opinion (about being so far ahead). Does that statement also > imply that Xilinx is just so far ahead that they can't bother with component > standardization? That's another reading I could take away from that > statement and seems to be what you're suggesting as well. > > > But, thanks to programmable logic, you can add soft standardization > > layers to your heart's content. Nothing stops smart IP of implementing > > any conceivable standard, but unfortunately usually at a cost and > > performance sacrifice.Maybe. Are you suggesting that the lpm_fifo function wouldn't run at your > horn tooting 550 MHz? Would be a bit of a bummer to think that you > couldn't. > > > If someone knows a smarter way to design FPGAs, we really are > > listening. Honest !I don't want to design FPGAs, I want to use them better and not be > re-creating the wheel either and I think darn near all of your users would > too. The Xilinx way appears to be to avoid adhering to or encouraging any > design standards for IP creation other than to imply that the X way is the > only and the best way. > > > Our customers want performance at the lowest cost, plus ease-of-design. > > But everybody has his own ideas about relative priorities.Yep > > KJArticle: 111553
Davy wrote: > NigelE wrote: > > Davy wrote: > > > Hi NigelE, > > > > > > Thanks a lot! I mis-understand virtual interface. > > > > > > Is there any web seminar or online video talk about AVM? That I want to > > > understand AVM more clearly. > > > > > > Best regards, > > > Davy > > > > > > > Hi Davy > > > > Try a look at > > > > http://www.mentor.com/products/fv/events/ > > > > You'll find listed in the online events, our recent 'Hitchhikers Guide > > to Verification' seminar that covers AVM and other SV verification > > topics. > > > > It's split into 5 sessions so you don't need to watch it all at once ;) > > > > Best regards > > > > - Nigel > > Hi Nigel, > > Thanks a lot for the help! > > Best regards, > Davy The direct path to 'Hitchhikers Guide to Verification' seminar is http://www.mentor.com/products/fv/events/hitchhiker_online_sem.cfm# Just a memo for myself :) Thanks! DavyArticle: 111554
Hi all,
Thanks for your help.I got the problem with software.I just
uninstalled chipscope and installed again.Then it worked out.
But when i am doing boundary scan with JTAG or iMPACT,it couldn't
identify the one of the devices on the ML461 baord.We have four Xilinx
FPGAs(xc4vlx25) on ML461 and one SystemACE.But it identifies only last
three FPGAs and it couldn't identify the SystemACE and first FPGA
properly.Due to this it is also showing the number of devices on the
board are more than four,different number at different times.I don't
know what is the problem with this.If we exclude this first FPGA from
boundary scan chain,then it detects the other three FPGAs properly.This
first FPGA is giving problem in the boundary scan chain.
-Ramesh.
On Nov 5, 7:15 pm, yttrium <yttr...@telenet.be> wrote:
> John Adair wrote:
> > One thing to check is that Impact is not open when using Chipscope. I
> > have seen cases of Impact affecting chipscope operation.
>
> > John Adair
> > Enterpoint Ltd.
>
> > kollarame...@gmail.com wrote:
> >> Hi,
> >> I need help for solving the following problem.I am trying to
> >> connect to ML461 JTAG port from PC parallel port by using XILINX
> >> parallel cable through chipscope.But it couldn't connect properly.It
> >> gives the following error.
>
> >> ERROR: Socket Open Failed. localhost/127.0.0.1:50001
> >> localhost
> >> java.net.ConnectException: Connection refused: connect
> >> ERROR: Failed to open Xilinx Parallel Cable. See message(s) above.
>
> >> And the same cable setup works properly with the another same board.
>
> >> I really appreciate your help.
>
> >> Thanks,
> >> -Rameshyes i had the same problems ... and yes [Markus Meng] the parallel pod
> is still supported (i still use it) ... maybe something to do with the
> IO settings of the parallel port (ECP/EPP...) i had to change this one
> in the beginning ...- Hide quoted text -- Show quoted text -
Article: 111555On 4 Nov 2006 09:31:57 -0800, "Xesium" <amirhossein.gholamipour@gmail.com> wrote: >Hi guys, >I'm trying to connect a simple co-processor to microblaze. The >co-processor simply gets 8 inputs and does a simple arithmetic and >gives one output. The problem that I'm currently experiencing is (I >figured it out during simulation) that, when I put a data from >microblaze on FSL the fsl_m_write signal from microblaze doesn't become >1. So the co-processor never notices that there are data on the bus and >it never changes status. As well when I check the data on the FSL >microblaze-to-coprocessor bus, it is not what I'm trying to write. Put >instruction takes 2 cycles to execute. The first cycle the data on FSL >master output of microblaze is insane but the second cycle it becomes >one. However I've made sure that FSL_M_FULL is not 1. So my FIFO is >empty. The clk and reset signal of the co-processor is correctly >connected to the processor. As well I'm doing blocking read and write. >Do you have any idea why it is not working? <...> I am not sure on how you do this on verilog (never workes with it!), but I know for sure you must tell the micrtoblaze instance to really have an fsl port (in VHDL: generic map (... C_FSL_LINKS=> 1..) Have you done so? Because, although all pins are there, the fsl connection will not be instantiated if you don't tell the synthesiser to do so best regards, ZaraArticle: 111556
There is another simple possibility to speed up calculations. Do you know that the GPU on a modern graphics card can do matrix calculations a lot times faster than a CPU? There are several SDKs and you wont need special Hardware for that. Xilinx and Altera stuff takes a lot of time and a high risk because if you really have a problem to solve the engineers from there say: "This is not supported"... You get only help if you a buying in large quantaties. And in scientific computing you never have a large quantatie. So use alternativly a GPU for fast calculations like FFT and Sorting. My favorite SDK is BrookGPU (http://graphics.stanford.edu/projects/brookgpu/). Easy to use and a lot of out oft the box runnig examples. It works with every modern 3d Accellertor because it uses OpenGL and DirectX. You will implement the stuff in a week or two. In VHDL you'll need half a year for the simulation and timig stuff for the same result. Think about it! Eric lancepickens@gmail.com schrieb: > Thanks for the speedy reply everyone, I appreciate the help. > > ~Lance > > On Nov 3, 10:26 am, "Marc Reinig" <M...@newsgroups.nospam> wrote: >> The other area where FPGA's win is in latency. Parallel or networked PC's >> cannot meet the latency requirements of many large computationally intensive >> real-time systems, even though they can meet the throughput requirements >> >> Marco >> ________________________ >> Marc Reinig >> UCO/Lick Observatory >> Laboratory for Adaptive Optics >> >> "JJ" <johnjak...@gmail.com> wrote in messagenews:1162578053.176232.266200@e3g2000cwe.googlegroups.com... >> >> >> >>> Nico Coesel wrote: >>>> helmut.leonha...@gmail.com wrote: >>>>> Everything what can parallelize is possibly running faster in Hardware >>>>> than in Software. >>>> Still, the amount of processing power a modern PC processor can >>>> deliver is enormous. It is problably more cost effective to optimize >>>> an algorithm to run parallel on 10 PC's than to develop a specific >>>> FPGA solution. If space is a constraint, the answer is in using blade >>>> servers. >>> This is often true even for obvious applications of FPGA, PC can still >>> be better. >>> The analysis needs to account for factors such as floating point use, >>> high locality referencing or lots of computing on tiny data sets and >>> use of standard 32, 64 bit operands favors PCs On the other hand bit >>> mangling, very high rates of memory shuffling, use of unusual bit wise >>> or odd size mathematical operators and strategic use of buffer memories >>> are a win for FPGAs. >>> I suspect that as Flash drives replace hard drives at the 30GByte level >>> the case for hardware taking control of data management in Flash only >>> increases since a hardware FPGA design wouldn't usually include disk >>> systems and can then push the PC host further away. >>> Some problems can be factored both ways to get similar results in which >>> case PCs still have the familiarity edge. Still a PC based solution >>> that is just recompiled to hardware will perform far less well since >>> it has already been factored to favor the PC. >>> For a hardware solution, the software version can be viewed as the >>> simulation of same hardware and most simulations usually run many >>> orders slower than real hardware. >>> This is why the best hardware solution is unlikeley to ever be achieved >>> by software folks who have little experience in hardware who would >>> force the FPGA to emulate the PC strengths. >>> John Jakson >>> transputer guy >Article: 111557
No. := (others=>'0'); in signal declarations are not synthesizable. RgdsArticle: 111558
add this to your code library VITAL; use VITAL.VITAL_TIMING.ALL; regards, Krishna Janumanchi sergey wrote: > Forgot to include the actual lines that its erroring on: > > inmatA : in STD_LOGIC_VECTOR2 ( 3 downto 0 , 16 downto 0 ); > inmatB : in STD_LOGIC_VECTOR2 ( 3 downto 0 , 16 downto 0 ); > outmat : out STD_LOGIC_VECTOR3 ( 3 downto 0 , 3 downto 0 , 16 > downto 0 ) > > (I see that they're declared as multi-dimensional and probably aren't > supposed to be... but why is Xilinx translating them that way, and what > can I do about it?) > > -- Sergey > > sergey wrote: > > Hi all again, > > > > I have a fairly straight forward systolic array design which uses the > > fixed_point type. It simulates fine for the behavioral simulation. It > > synthesizes fine (there are a few warnings, but they appear to be > > OK)... but when I try to do a post-synthesis simulation in ModelSim, I > > get: > > > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): > > Prefix of a slice must be a 1 dimensional array. > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): > > Prefix of a slice must be a 1 dimensional array. > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): > > Unknown identifier 'std_logic_vector2'. > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): > > Prefix of a slice must be a 1 dimensional array. > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): > > Prefix of a slice must be a 1 dimensional array. > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): > > Unknown identifier 'std_logic_vector2'. > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): > > Prefix of a slice must be a 1 dimensional array. > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): > > Prefix of a slice must be a 1 dimensional array. > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): > > Prefix of a slice must be a 1 dimensional array. > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): > > Unknown identifier 'std_logic_vector3'. > > ** Error: > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(241): > > VHDL Compiler exiting > > > > Do I need to include some library that I'm not? What might be the > > issue? > > > > Thanks in advance, > > > > SergeyArticle: 111559
Thomas Entner wrote: >>> I took the plunge and built up a 2nd PC using a Core2Duo. >>> Here are the specs: >>> Old PC: P4 3GHz HT, 2GB DDR2-533 RAM, Gigabyte GA81915 mobo, stock >>> cooler >>> New PC: Core2Duo E6600, 2GB DDR2-800 RAM, ASUS P5B Mobo, ArcticFreezer7 >>> cooler >>> Using a Spartan3 design running clean from scratch in ISE 8.2.3i >>> Old PC: 82mins >>> New PC: 35mins >>> New PC (overclocked to 3.2GHz): 25mins >>> I'm really pleased with the Core2Duo and would recommend it. >> Conclusion dual cores (multiprocessor) benefits Xilinx ISE substantially? >> > No, cache size matters.... As far as I know, neither ISE nor Quartus use the > second core, but both benefit from the huge cache. > > Thomas > > www.entner-electronics.com > > I'm sure the second core will make a difference - while the one long task is occupying one core, other minor tasks will run on the other core. While these other tasks might only take a tiny proportion of the processor time, you avoid the penalties of task switching (like losing your cache) on the working processor.Article: 111560
The opencores.org I2C appears to be only in VHDL. Does anyone know of a free I2C master in Verilog? Thanks, Chris.Article: 111561
Hi, Davy schrieb: > When do Formal Equivalent Check (RTL and Gate Level) , I remember that > the tool compare the comb logic between D-FF . > > But when synthesis use re-timing and gated clock, can LEC tool compare > RTL and Gate? LEC is the tool from Cadence(former Verplex). AFAIK is this tool able to handle retiming (or better: is able to support the user to handle retiming). > And is gated clock one form of re-timing? IMHO no. Gated clock is another problem for formal verification. bye ThomasArticle: 111562
Hi all, I'd like to announce that the open source Schifra C++ Reed-Solomon error correcting code library is now available and awaiting your download. What is it? Schifra is a very robust, highly optimized and extremely configurable Reed-Solomon error correcting code library implemented in C++. Schifra supports standard, shortened and punctured Reed-Solomon codes. It also has support for stacked product codes and interleaving. url: http://www.schifra.com Arash Partow ________________________________________________________ Be one who knows what they don't know, Instead of being one who knows not what they don't know, Thinking they know everything about all things.Article: 111563
Hello everyone, I need some help coising a platform to programm an fpga for my project. I need a fast fpga because the signal will be proccessed @ near 800Mhz. Do you have any suggestions for the platform? I saw the Sandance solution (www.sundance.com) and it seems to me ok. If anyone can give me an advise on this it is very welcome. Thanks in advance, Tsemer.Article: 111564
Hi, I have a design in which I need to instantiate two microblaze system instances (the same microblaze system in two places). I'm doing it by the following way: 1) I've created a system containing a single microblaze (in EDK) 2) I've instantiated it in my hdl code in two different places. 3) Then I merged the two bmm files into a single bmm file which looks like this: /////////////////////////////////////////////////////////////////////////////// // // Address space 'rmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). // /////////////////////////////////////////////////////////////////////////////// ADDRESS_BLOCK rmac_lmb_bram RAMB16 [0x00000000:0x00001fff] BUS_BLOCK CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; CORE/rmac_i/system_rmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; /////////////////////////////////////////////////////////////////////////////// // // Address space 'tmac_lmb_bram' 0x00000000:0x00001FFF (8 KB). // /////////////////////////////////////////////////////////////////////////////// ADDRESS_BLOCK tmac_lmb_bram RAMB16 [0x00000000:0x00001fff] BUS_BLOCK CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_0 [31:24] ; CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_1 [23:16] ; CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_2 [15:8] ; CORE/tmac_i/system_tmac/lmb_bram/lmb_bram/ramb16_3 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; 4) I synthesize my design using synplify 8.1 5) I call the following script (for translate and map) ngdbuild -a -p XC4VLX80-FF1148-10 -bm /home/motic/projects/fpga/units/mac/mac_bmax/802_16d/ublaze/rmac_tmac.bmm -sd ../../../../syn/syn_v4/edf -uc ../../bs_lx80.ucf bs rev1/bs.ngd; map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b rev1/bs.ngd rev1/bs.pcf; The ngdbuild goes well but the mapping process has lots of errors ( it seems that the mapper tries to place the two microblaze instances on top of each other) part of the map log file (.mrp) is attached Can you please advise ? Thanks in advance, Mordehay. Snippet of the map report file (originaly conatins 465 errors): Release 7.1.03i Map H.41 Xilinx Mapping Report File for Design 'bs' Design Information ------------------ Command Line : map -cm area -p XC4VLX80-FF1148-10 -detail -o rev1/map.ncd -pr b rev1/bs.ngd rev1/bs.pcf Target Device : xc4vlx80 Target Package : ff1148 Target Speed : -10 Mapper Version : virtex4 -- $Revision: 1.26.6.4 $ Mapped Date : Mon Nov 6 11:55:10 2006 Design Summary -------------- Number of errors : 465 Number of warnings :3074 Section 1 - Errors ------------------ ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y0) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y1) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_High) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg1_High" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y2) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y3) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_High) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/RAM16x1D_Reg1_High" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I15/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y0) which require the combination of the following symbols into a single SLICE component: LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg1_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<31>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg1_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<31>) LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[31]) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Data_Write_Mux" (Output Signal = CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[31]) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y4) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y1) which require the combination of the following symbols into a single SLICE component: LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT31" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<31>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT31" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<31>) LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg2_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<31>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/Reg2_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<31>) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y5) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_High) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/RAM16x1D_Reg1_High" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I30/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y2) which require the combination of the following symbols into a single SLICE component: LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg1_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<15>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg1_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<15>) LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/raw_Data_Write<15>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Data_Write_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/raw_Data_Write<15>) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y6) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y3) which require the combination of the following symbols into a single SLICE component: LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT15" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/mux_Data_Read<15>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Dopb_Interface_I/OPB_Data_ Mux_I1/MUX_LUT15" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/mux_Data_Read<15>) LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg2_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<15>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I15/Reg2_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg2_Data<15>) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y7) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_High) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I14/RAM16x1D_Reg1_High" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I14/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X1Y4) which require the combination of the following symbols into a single SLICE component: LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = CORE/tmac_i/system_tmac/dlmb_LMB_WriteDBus[30]) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Data_Write_Mux" (Output Signal = CORE/rmac_i/system_rmac/dlmb_LMB_WriteDBus[30]) LUT symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Reg1_Mux" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<30>) LUT symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I30/Reg1_Mux" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/reg1_Data<30>) There are more than two function generators. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y8) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X2Y0) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg2_Data_Low) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I31/RAM16x1D_Reg2_Low" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I31/reg2_Data_Low) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=microblaze_0, RLOC=X0Y9) which require the combination of the following symbols into a single SLICEM component: RAMDP symbol "CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal = CORE/tmac_i/system_tmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_High) RAMDP symbol "CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_ I/Register_File_Bit_I29/RAM16x1D_Reg1_High" (Output Signal = CORE/rmac_i/system_rmac/microblaze_0/microblaze_0/Data_Flow_I/Register_File_I /Register_File_Bit_I29/reg1_Data_High) The address signals must match exactly when using both F and G in RAM mode. Please correct the design constraints accordingly. and it continues like this ....Article: 111565
Hi, The problem is that the two microblazes have the exact same name. MicroBlaze is a RLOC block which requires a unique name. In this case, I think you need to create two EDK designs which are more or less the same except for the instance name of MicroBlaze or you can also create two microblaze in one EDK design. GöranArticle: 111566
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1162777204.878034.242930@f16g2000cwb.googlegroups.com... > KJ, is it so difficult for two reasonably intelligent engineers to > communicate ? No, and I might suggest that you would not find it so difficult either if, when you make your posts, you would give the courtesy of replying to what was said in the post that you're replying to instead of going into a speech or sales pitch. Speeches and pitches can be interesting and can often spawn their own sub-topics, but that doesn't make them relevant to the discussion. One technique is to not top post. > We are forced to be very efficient (small size) and very (fast high > clock rate), that's what the market demands. Among other demands as well. Customers are like that. We all have them. > Sacrificing performance by adhering to one or another of the so-called > interface standards is, at best, our second or third priority. And yet the basis for this statement is "because Peter said so". You haven't been able to offer even a single example to back up what you've said. You have offered no benchmarks, no references, nothing to back up your statement that one would be "Sacrificing performance by adhering to one or another of the so-called interface standards". > You may not like it, others do. Others are free to (dis)like things for no rational basis if they so choose. Personally I think you're shortchanging the intelligence of a good chunk of your users and power users with the statements you've made in this thread. > 'nough said. > Peter Alfke KJArticle: 111567
<ALuPin@web.de> wrote in message news:1162800744.822146.61370@f16g2000cwb.googlegroups.com... > No. > > := (others=>'0'); > > in signal declarations are not synthesizable. > > Rgds Whether or not it is synthesizable depends on the synthesis tool and the target device. Specifying the power up default value for the output of a clocked register certainly can be synthesizable. In fact both brand 'A' and brand 'X' (and I'm sure others) FPGAs do specify that registers are reset at the completion of configuration which is the FPGA equivalent of 'power up' so the construct certainly is synthesizable. One should tread with care though and probably limit the usage of default values to only those signals that have to do directly with generating the internal reset signal as was mentioned earlier in the post. One should probably also only try to only use a default value of '0' as well since most (all?) FPGAs will clear the flip flops not set some of them to '0' and others to '1'. There is a very simple technique that can be used that would allow a default value of '1' to be specified in the code even though the flip flop resets to '0' but then you'll be counting on the synthesis tool to implement this. KJArticle: 111568
Maybe I'll regret jumping in here, but here's my take :-)
We designers want standard interfaces to FPGA bits and bobs.
FIFOs are a good example, no-one *wants* to design their own. There is
a "standard" interface defined, but it's not used across all vendors,
which makes life painful to port...
Also, mostly we don't need lots of clever configurations.
If I want to use Xilinx's FIFO, I use code like this (with some snippage):
-- FIFO18: 16k+2k Parity Synchronous/Asynchronous BlockRAM FIFO BlockRAM Memory
-- Virtex-5
-- Xilinx HDL Libraries Guide, version 8.2.2
FIFO18_inst : FIFO18
generic map (
ALMOST_FULL_OFFSET => X"0080", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
DATA_WIDTH => 18, -- Sets data width to 4, 9, or 18
FIRST_WORD_FALL_THROUGH => false) -- Sets the FIFO FWFT to TRUE or FALSE
port map (
DO => DO, -- 16-bit data output
DOP => DOP, -- 2-bit parity data output
EMPTY => EMPTY, -- 1-bit empty output flag
FULL => FULL, -- 1-bit full output flag
WRCOUNT => WRCOUNT, -- 12-bit write count output
DI => DI, -- FIFO data input, with determined by DATA_WIDTH
DIP => DIP, -- 2-bit partity input
RDCLK => RDCLK, -- 1-bit read clock input
RDEN => RDEN, -- 1-bit read enable input
RST => RST, -- 1-bit reset input
WRCLK => WRCLK, -- 1-bit write clock input
WREN => WREN -- 1-bit write enable input
);
As an aside: And what's this DI/DO and DIP/DOP about? I ask for 18
bits, I just want 18-bits!
Now, not inly is this non-standard, if I want a different size, I have
to instantiate a different component with a different name!
The same goes for RAMs.
Anyway, if I want to use most others' I use this:
LPM_FIFO_1: entity work.LPM_FIFO
generic map (
LPM_WIDTH => LPM_WIDTH,
LPM_WIDTHU => LPM_WIDTHU,
LPM_NUMWORDS => LPM_NUMWORDS,
LPM_SHOWAHEAD => LPM_SHOWAHEAD,
LPM_TYPE => LPM_TYPE,
LPM_HINT => LPM_HINT)
port map (
DATA => DATA,
CLOCK => CLOCK,
WRREQ => WRREQ,
RDREQ => RDREQ,
ACLR => ACLR,
SCLR => SCLR,
Q => Q,
USEDW => USEDW,
FULL => FULL,
EMPTY => EMPTY);
Now, I agree with KJ, the LPM_WIDTH and WIDTHU thing is daft. The
TYPE and HINT don't usually help me much, but the rest of it maps
directly onto Xilinx's template doesn't? There's a different entity
with async clocks, for those cases, but chnaging between async and
sync clocks happens a lots less often than between sizes of FIFO!
And if I change the size, the SW is smart enough to instantiate the
low-level stuff in the right way for me.
If I need absolute control, then sure, I can go and instantiate those
myself, but for the majority, all I need is a straightforward FIFO!
And again the same applies for things like LPM_RAM.
They all do the same thing. Why can't I just write the same thing for
all of them?
After all, I can write a bit of VHDL to wrap it, which get's me there
- but why do *I* (and everyone like me) have to do this, why can't the
vendors do it for me?
Maybe I'm missing something fundamental, but when I use a FIFO, all I
want is a simple FIFO with a consistent interface. Do others have a
different view?
Perhaps we should all get together and write the wrappers and docs for
this between us for the benefit of future generations ( :-)?)
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Article: 111569Hello, The sourcecode of the CPLD... <http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm>Article: 111570
Hi Im trying to design a high speed data capture card. Im using a Lattice ECP2M-50 FPGA with the one-board SERDES units (MGBT in Xilinx dtasheets). Im using a MSPS Nation ADC. This dual ADC has a output of 1Gb/s and thus the combined x4 lane PCIe will match this rate. HOWEVER, if there is latency on the PCIe bus more than 100us then my RAM inside the FPGA will overflow. I need to know bus latency between TLP's because i need to know if I require external RAM or if the design in possible! Can someone please help me!!?? Thanks JasonArticle: 111571
Dear Krishna, Thank you for your response. Which file do I add that to? The post-synthesis VHDL file, or the pre-synthesis top-level module? Also, I tried adding it to the post-synthesis file and ModelSim can't find library VITAL. Is that something only available with the full version? (I'm using the starter version). Thanks again, Sergey krishna.janumanchi@gmail.com wrote: > add this to your code > > library VITAL; > use VITAL.VITAL_TIMING.ALL; > > regards, > Krishna Janumanchi > > sergey wrote: > > Forgot to include the actual lines that its erroring on: > > > > inmatA : in STD_LOGIC_VECTOR2 ( 3 downto 0 , 16 downto 0 ); > > inmatB : in STD_LOGIC_VECTOR2 ( 3 downto 0 , 16 downto 0 ); > > outmat : out STD_LOGIC_VECTOR3 ( 3 downto 0 , 3 downto 0 , 16 > > downto 0 ) > > > > (I see that they're declared as multi-dimensional and probably aren't > > supposed to be... but why is Xilinx translating them that way, and what > > can I do about it?) > > > > -- Sergey > > > > sergey wrote: > > > Hi all again, > > > > > > I have a fairly straight forward systolic array design which uses the > > > fixed_point type. It simulates fine for the behavioral simulation. It > > > synthesizes fine (there are a few warnings, but they appear to be > > > OK)... but when I try to do a post-synthesis simulation in ModelSim, I > > > get: > > > > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): > > > Prefix of a slice must be a 1 dimensional array. > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): > > > Prefix of a slice must be a 1 dimensional array. > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(237): > > > Unknown identifier 'std_logic_vector2'. > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): > > > Prefix of a slice must be a 1 dimensional array. > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): > > > Prefix of a slice must be a 1 dimensional array. > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(238): > > > Unknown identifier 'std_logic_vector2'. > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): > > > Prefix of a slice must be a 1 dimensional array. > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): > > > Prefix of a slice must be a 1 dimensional array. > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): > > > Prefix of a slice must be a 1 dimensional array. > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(239): > > > Unknown identifier 'std_logic_vector3'. > > > ** Error: > > > C:/thesis/SDRE/VHDL/FINAL/mult/netgen/synthesis/mult_arr_synthesis.vhd(241): > > > VHDL Compiler exiting > > > > > > Do I need to include some library that I'm not? What might be the > > > issue? > > > > > > Thanks in advance, > > > > > > SergeyArticle: 111572
Hi Davy, Yes, LEC can compare RTL and GLN with retiming. Command is analyze retiming... For gated clock, it is not part of retiming. LEC has limited default gated clock structure recognition but you still can use LEC to perform formal verification on GLN with your gated clock netlist. Best regards, ABC Davy wrote: > Hi all, > > When do Formal Equivalent Check (RTL and Gate Level) , I remember that > the tool compare the comb logic between D-FF . > > But when synthesis use re-timing and gated clock, can LEC tool compare > RTL and Gate? > > And is gated clock one form of re-timing? > > I am reading a paper from SNUG about gated clock (How to successfully > use gated clock...) but I cannot understand the waveform... > > Best regards, > DavyArticle: 111573
Jim Granville wrote: > rickman wrote: > > > Jim Granville wrote: > >>Packages are relatively cheap (a new package is way cheaper than > >>a new die development), give them a large enough volume target, > >>and they will chase it. > > > > > > That is not what X and A will tell you. They plan out the packaging > > when they design a product family. It seems to be a major issue to put > > a part in a new package. > > Of course, salesmen will always pitch what they have, and give all > sorts of spin as to why anything else should be off your radar :) It is kind of hard to spin the loss of a sale when the competition has what we need. > When we spoke with infineon years ago, they said ~50K > was enough to contemplate a new package. > If it is one already in their flow, that helps as well. > So, for Xilnix that means probably the QFN48. > Then they think about OTHER customers, and something like > this is NOT a blind alley, as there are many applications > for CPLDs with more macrocells, but less IO. It may not be a blind alley for us, but for the FPGA vendors, they don't seem interested. The other issue with Xilinx is the family. They are all about the Coolrunner II parts while I much prefer the Coolrunner XPLA parts which only require a single power supply. At least the Lattice parts incorporate an LDO if you want the advantages of the newer process and are size limited.Article: 111574
KJ wrote: > > One should tread with care though and probably limit the usage of default > values to only those signals that have to do directly with generating the > internal reset signal as was mentioned earlier in the post. One should > probably also only try to only use a default value of '0' as well since most > (all?) FPGAs will clear the flip flops not set some of them to '0' and > others to '1'. There is a very simple technique that can be used that would > allow a default value of '1' to be specified in the code even though the > flip flop resets to '0' but then you'll be counting on the synthesis tool to > implement this. The synthesis tools I have used correctly synthesize even non '0' declaration initializations, and X does support non '0' initialization. And this is very handy in a lot of places. For example, I often use this to set the default value of registers, since I know that software will not attempt to change the registers until long after the FPGA has initialized.
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