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Messages from 130075

Article: 130075
Subject: Re: Design entries for FSM
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 14 Mar 2008 09:43:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 14, 9:21=A0am, Sue <sudha...@gmail.com> wrote:
>
> I have very long and lenghty FSMs to work on. This is just a small
> example. Some of the benchmark circuits that I have to work on have 20
> states and around 100 transitions so it is not feasible to hard code
> each FSM in VHDl. Instead if I can have a tool which takes FSM in =A0a
> txt file format and converts it to a synthesizable format, it will be
> very useful.
> Any suggestions?
> -Sue-

Thanks for providing some information about your real needs and your
capabilities.

I don't think you'll find anything to take the kiss2 format and
generate synthesizable code.

Given that you're a software person, you probably have the ability to
quickly put together perl scripts or other parsers to generate simple
VHDL case statements from the kiss2 format.

You understand what the state information is communicating so you only
need to understand the VHDL case statement to get the mapping between
your state machines and real hardware.  If you do your own very simple
parser, you can generate cut-and-paste text for very straight-forward
case statements.

Go for it!  It shouldn't take you long.  I'm not a software guy so it
*would* take me a while.

Article: 130076
Subject: Re: Xilinx S3DSP + EDK Board, too good to be true?
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Fri, 14 Mar 2008 16:59:50 +0000 (UTC)
Links: << >>  << T >>  << A >>
John_H <newsgroup@johnhandwork.com> wrote:
...

> Where do you get the idea EDK is free or available for a very low
> price?

https://roulette.das-labor.org/bzrtrac/browser/fpga/soc-lm32/soc-lm32

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 130077
Subject: Re: Design entries for FSM
From: Gabor <gabor@alacron.com>
Date: Fri, 14 Mar 2008 10:13:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 14, 12:43 pm, John_H <newsgr...@johnhandwork.com> wrote:
> On Mar 14, 9:21 am, Sue <sudha...@gmail.com> wrote:
>
>
>
> > I have very long and lenghty FSMs to work on. This is just a small
> > example. Some of the benchmark circuits that I have to work on have 20
> > states and around 100 transitions so it is not feasible to hard code
> > each FSM in VHDl. Instead if I can have a tool which takes FSM in  a
> > txt file format and converts it to a synthesizable format, it will be
> > very useful.
> > Any suggestions?
> > -Sue-
>
> Thanks for providing some information about your real needs and your
> capabilities.
>
> I don't think you'll find anything to take the kiss2 format and
> generate synthesizable code.
>
> Given that you're a software person, you probably have the ability to
> quickly put together perl scripts or other parsers to generate simple
> VHDL case statements from the kiss2 format.
>
> You understand what the state information is communicating so you only
> need to understand the VHDL case statement to get the mapping between
> your state machines and real hardware.  If you do your own very simple
> parser, you can generate cut-and-paste text for very straight-forward
> case statements.
>
> Go for it!  It shouldn't take you long.  I'm not a software guy so it
> *would* take me a while.

A quick Google of "Kiss2 to VHDL" shows that this has been done more
than once.  There is a paper on the subject on IEEE and I found
a book review at:

http://books.google.com/books?id=3087sDKL_vQC&pg=PA36&lpg=PA36&dq=kiss2+to+VHDL&source=web&ots=yE3KwGxypO&sig=VS8NydzKNrwRanTqKubW5Vkz74o&hl=en

HTH,
Gabor

Article: 130078
Subject: Re: DDR3 speed, Altera vs Xilinx
From: nico@puntnl.niks (Nico Coesel)
Date: Fri, 14 Mar 2008 17:41:21 GMT
Links: << >>  << T >>  << A >>
Antti <Antti.Lukats@googlemail.com> wrote:

>On 14 Mrz., 16:24, austin <aus...@xilinx.com> wrote:
>> Morten,
>>
>> We chose different paths:  Altera used hardened logic to get their
>> speed, where we chose to stay general, and use any pins/any fabric/any
>> standard.
>>
>> We have DDR3 designs that are also working at 533 MHz.
>>
>> Best to sit down and talk with your FAE on the subject.
>>
>> There are many other factors to consider (not he least of which is we
>> are in full production on Virtex 5 LX, LXT, SXT, and they are just now
>> in ES on on few parts, with S3 GX canceled completely).
>>
>> Even though Altera has some really mean, cool, and neat power point
>> presentations, we basically have no competition whatsoever at 65nm at
>> the high end (as you can't ship power point in your systems).
>>
>> Austin
>
>LOL, eh, think there is only one tool we need:
>
>"powerpoint to silicon compiler" ;)
>
>Antti
>
>PS 553 MHz DDR3 without hardened io and general purpose FPGA is nice
>achievment

But is it worth something in a real application or is it just 'cool'?
When reading Xilinx memory interface application notes I get the
feeling the cool factor (to get numbers to put in nice powerpoint
presentations) is often more important than practical use. 533 MHz is
pushing the limits on a Xilinx device but with dedicated I/O logic
(like fast local clock paths for DQS) it would be a breeze to design.
The way Xilinx works they say it can be done, but every more
complicated interface like PCI, DDRx, PCI Express, serial ata, etc,
etc is suddenly extremely difficult and should be left to the
professionals. It is like Ford saying their cars are great and better
than the rest, but in the real world you'll find you need 3 arms to
drive around.

A lot can be said about Altera, but almost every hobbiest FPGA user in
the world is using Altera devices. This certainly says something about
the ease of use of Altera parts and software.

-- 
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

Article: 130079
Subject: Re: DDR3 speed, Altera vs Xilinx
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 14 Mar 2008 11:03:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 14, 10:41=A0am, n...@puntnl.niks (Nico Coesel) wrote:
<snip>
>
> A lot can be said about Altera, but almost every hobbiest FPGA user in
> the world is using Altera devices. This certainly says something about
> the ease of use of Altera parts and software.
>
<snip>

I'd love to see your reference  ;-)
Or perhaps you know most of the hobbyists personally?

I like seeing hobbyists use the tools and parts that are best for
their activities whatever they may be.

- John_H

Article: 130080
Subject: Re: Xilinx S3DSP + EDK Board, too good to be true?
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 14 Mar 2008 11:07:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 14, 9:59=A0am, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
wrote:
> John_H <newsgr...@johnhandwork.com> wrote:
>
> ...
>
> > Where do you get the idea EDK is free or available for a very low
> > price?
>
> https://roulette.das-labor.org/bzrtrac/browser/fpga/soc-lm32/soc-lm32
>
> --
> Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-darm=
stadt.de
>
> Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------


I'm at a directory listing.  Nothing obvious there.  A search for edk
comes up with no matches.

Was there a specific location within that directory configuration
where you get the idea EDK is free or available for a very low price?

- John_H

Article: 130081
Subject: Re: Xilinx S3DSP + EDK Board, too good to be true?
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Fri, 14 Mar 2008 18:18:17 +0000 (UTC)
Links: << >>  << T >>  << A >>
John_H <newsgroup@johnhandwork.com> wrote:
> > https://roulette.das-labor.org/bzrtrac/browser/fpga/soc-lm32/soc-lm32

> I'm at a directory listing.  Nothing obvious there.  A search for edk
> comes up with no matches.

> Was there a specific location within that directory configuration
> where you get the idea EDK is free or available for a very low price?

Sorry, there is no Xilinx EDK at that location. But there is a port of
Lattice Mico32 to Xilinx and files to test it. If you want to experiment
with softcores, its a great and cheap way. So it's an E_mbedded D_evelopment
K_it, but not Xilinx "EDK".
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 130082
Subject: Re: Xilinx S3DSP + EDK Board, too good to be true?
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Fri, 14 Mar 2008 18:19:47 +0000 (UTC)
Links: << >>  << T >>  << A >>
Antti <Antti.Lukats@googlemail.com> wrote:
...
> Uwe there is no free DDR2 for mico32.
> yet.

Does this "yet" have any meaning?
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 130083
Subject: Re: Virtex-4 VLX25 DCM problem
From: "Grubi" <dkolev@hotmail.com>
Date: Fri, 14 Mar 2008 13:22:23 -0500
Links: << >>  << T >>  << A >>
Thanks Peter. By touching reference oscillator output during power up I can
force FPGA DCM to work incorrectly (not work actually). The interesting
thing was that simple power cycle dows not solve the problem, u 

--
Message posted using http://www.talkaboutelectronicequipment.com/group/comp.arch.fpga/
More information at http://www.talkaboutelectronicequipment.com/faq.html


Article: 130084
Subject: Re: DDR3 speed, Altera vs Xilinx
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 14 Mar 2008 11:28:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 14 Mrz., 19:03, John_H <newsgr...@johnhandwork.com> wrote:
> On Mar 14, 10:41 am, n...@puntnl.niks (Nico Coesel) wrote:
> <snip>
>
> > A lot can be said about Altera, but almost every hobbiest FPGA user in
> > the world is using Altera devices. This certainly says something about
> > the ease of use of Altera parts and software.
>
> <snip>
>
> I'd love to see your reference  ;-)
> Or perhaps you know most of the hobbyists personally?
>
> I like seeing hobbyists use the tools and parts that are best for
> their activities whatever they may be.
>
> - John_H

almost ROTFL :)

1. all assumptions are assumed false..

well, there is some trend towards "altera-love" for the hobby use:

1) C1 reconfigurable computer -> ACEX-1K
2) japanese MSX computer -> Cyclone
3) TREX-C1 -> Cyclone

so some retro-hobby folks defenetly prefer Altera,
but that of course doesnt mean "almost every hobby user"

Antti

Article: 130085
Subject: Re: Actel PA3 with DirectC or SVF, anybody had any success?
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 14 Mar 2008 11:32:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 14 Mrz., 13:36, j...@amontec.com wrote:
> On Mar 14, 1:25 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
> > On 14 Mrz., 11:34, j...@amontec.com wrote:
>
> > > On Mar 14, 11:03 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > On 14 Mrz., 10:50, j...@amontec.com wrote:
>
> > > > > On Mar 14, 9:20 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > On 14 Mrz., 08:26, j...@amontec.com wrote:
>
> > > > > > > On Mar 14, 7:14 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > > > > > > Hi
>
> > > > > > > > I wonder if anyone had any success using either DirectC 2.2 or SVF
> > > > > > > > files to program Actel PA3 devices. All my attempts are failing so
> > > > > > > > far.
>
> > > > > > > > 1) DirectC 2.2 compiled with VC2005 (adapted to Xilinx Cable III), had
> > > > > > > > 1 time success from 100 attempts to program the part
> > > > > > > > 2) playing SVF or XSVF files with Impact fail very quick, SVF doesnt
> > > > > > > > even get as far as checking jtag IDCODE
> > > > > > > > 3) custom SVF player also shows weird behaviour
>
> > > > > > > > Antti
>
> > > > > > > Maybe try with the Amontec SVF Player + the Amontec JTAGkey (USB to
> > > > > > > JTAG Cable).
> > > > > > > Amontec SVF Player support Trailer Header and infinite Scan Length.
>
> > > > > > > Note: if the IDCODE failed SOMETIMES this could mean you have a bad
> > > > > > > JTAG connection (between the Xilinx Cable III <-> target board).
> > > > > > > Make sure to not route the TCK parallel to the TDI or TDO, we have the
> > > > > > > experience that this could infer to the stability of the JTAG FSM even
> > > > > > > if you run JTAG at very low speed.
> > > > > > > You could try to add a 100R resistor on TCK close to Target.
>
> > > > > > > Almost sure your issue is not coming from the SVF file nor the Player,
> > > > > > > but from your JTAG signal integrity.
>
> > > > > > > Regards,
> > > > > > > Laurenthttp://www.amontec.com
>
> > > > > > Larry
>
> > > > > > normally I would agree with you, but:
>
> > > > > > it is not that the failures are some times or random:
>
> > > > > > 1) TLR-->shift-DR ===> correct IDCODE ALWAYS 100% reliable !!!
>
> > > > > > 2) TLR->RTI->shift-IR (IDCODE)->RTI->shift-DR
>
> > > > > > 100% failure when trying with SVF file and impact
> > > > > > 100% ok, when trying XSVF file and impact
>
> > > > > > 100% failure when adding extra delay in RTI state (TCK IDLE NOT
> > > > > > TOGGLING) in custom SVF player
> > > > > > 100% ok when doing FAST playback in custom SVF player
>
> > > > > > 3) DirectC
> > > > > > a) once worked full programming cycle
> > > > > > b) place of failure depends on the VC compile target (debug or
> > > > > > release) the place of failure is constant, but rather soon in the
> > > > > > file, ISP_entry command,  after IDCODE check. the DirectC timing
> > > > > > calibration value is dependant on the build target, so i assume some
> > > > > > speed issue here
>
> > > > > > hardware currently in use
> > > > > > *) Amontec Chameleon with Xilinx JTAG fly-wire adapter
> > > > > > *) A3P250 on proto board, wire length from IC to JTAG pin < 10 mm for
> > > > > > all connections
>
> > > > > > I cant use Amontec svfplayer it does NOT SUPPORT amontec Chameleon :
> > > > > > ( for some time ago I purchased 3 pcs of FT2232 mainly to rebuild the
> > > > > > jtagkey, but didnt ever bother doing it, so I dont have any jtagkey to
> > > > > > test with :(
> > > > > This could help.
>
> > > > > > Please look above my observations, could you still assume it is signal
> > > > > > integrity issue? The pass-fail depends on the time spent in RTI when
> > > > > > TCK is not toggling, meaning there are no signal toggling at all! I am
> > > > > > puzzled at least.
>
> > > > > > Antti
>
> > > > > What is your ENDIR and ENDDR ?
>
> > > > > Maybe try to add RUNTEST when in RTI. But if this help, there could be
> > > > > a bug in the Actel JTAG FSM!
>
> > > > > ... anyway, why do you not provide us a part of the SVF you are
> > > > > running for the IDCODE?
>
> > > > > Laurenthttp://www.amontec.com
>
> > > > == cutout from Actel libero 8.1 generated SVF ==
> > > > FREQUENCY 4E6 HZ;
> > > > STATE RESET;
> > > > RUNTEST IDLE 5 TCK;
> > > > ENDIR IRPAUSE;
> > > > ENDDR DRPAUSE;
> > > > SIR 8 TDI(0F);
> > > > SDR 32 TDI(00000000);
> > > > STATE IDLE;
> > > > RUNTEST IDLE 1 TCK;
> > > > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF);
> > > > ===
>
> > > > the above fails 100% with impact if played back as SVF
> > > > the same or modified one converted to XSVF works 100%
>
> > > > in my own code i tried ENDxR IDLE vs PAUSE but i did not work out any
> > > > fully working solution
>
> > > > Antti
>
> > > Try the two following one and let us know the result:
>
> > > == cutout from Actel libero 8.1 generated SVF ==
> > > FREQUENCY 4E6 HZ;
> > > STATE RESET;
> > > RUNTEST IDLE 5 TCK;
> > > ENDIR IDLE;
> > > ENDDR IDLE;
> > > SIR 8 TDI(0F);
> > > SDR 32 TDI(00000000);
> > > // STATE IDLE;
> > > RUNTEST IDLE 1 TCK;
> > > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF);
> > > ===
>
> > > == cutout from Actel libero 8.1 generated SVF ==
> > > FREQUENCY 4E6 HZ;
> > > STATE RESET;
> > > STATE RESET;
> > > STATE RESET;
> > > STATE RESET;
> > > STATE RESET;
> > > RUNTEST RESET 5 TCK;
> > > ENDIR IDLE;
> > > ENDDR IDLE;
> > > SIR 8 TDI(0F);
> > > SDR 32 TDI(00000000);
> > > // STATE IDLE;
> > > RUNTEST IDLE 1 TCK;
> > > SDR 32 TDI(00000000) TDO(02A141CF) MASK(0EFFFFFF);
> > > ===
>
> > > Laurenthttp://www.amontec.com
>
> > I tried some similar things, and many more, with not much luck
>
> > Antti
>
> Antti,
>
> But did you have try the two ones I gave you?
> similar or similar or maybe similar ? ;-)
>
> Laurenthttp://www.amontec.com

maybe similar ;)

I will run your commented version when i have the system again online,
but do not think they will make explanation visible for the problem

Antti










Article: 130086
Subject: Re: Virtex-4 VLX25 DCM problem
From: "Grubi" <dkolev@hotmail.com>
Date: Fri, 14 Mar 2008 13:34:27 -0500
Links: << >>  << T >>  << A >>
Uf, I touch submit message before I finish... So, I successfully simulate
failing of DCM by touching output of reference oscillator. Typically power
cycle and 20 seconds in between was enough(even there is not big decoupling
capacitors in the power supply) DCM to start work correctly when it is
untouched. So, I think the problem is early releasing of FPGA reset, which
I will test tomorrow and all the boards actually work on the edge - if
oscillator start-up time is small everything is OK, but otherwise DCM stop
working. Thanks again to all.

--
Message posted using http://www.talkaboutelectronicequipment.com/group/comp.arch.fpga/
More information at http://www.talkaboutelectronicequipment.com/faq.html


Article: 130087
Subject: Re: Xilinx S3DSP + EDK Board, too good to be true?
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 14 Mar 2008 11:36:56 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 14 Mrz., 19:19, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
wrote:
> Antti <Antti.Luk...@googlemail.com> wrote:
>
> ...
>
> > Uwe there is no free DDR2 for mico32.
> > yet.
>
> Does this "yet" have any meaning?
> --
> Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

sorry, I meant= not yet.
and nothing known if ever, but..
well I  assume it would not be so complicated to convert the MIG
generated monster to the WB bus and connect to your beloved mico32
as it hasnt been done, then it means nobody cared todo it, thats all

Antti



Article: 130088
Subject: Re: DDR3 speed, Altera vs Xilinx
From: austin <austin@xilinx.com>
Date: Fri, 14 Mar 2008 11:55:41 -0700
Links: << >>  << T >>  << A >>
...

~984 hits for - Altera FPGA Hobby use - on google (no quotes).

~27,200 hits for - Xilinx FPGA Hobby use - on google (no quotes).

Not that "Hobby Use" is a big line item on the financial report, but...

As much as this is not a scientific survey, it is still pretty telling!

Oh yes, those hobbiests are just swarming all over those Altera parts.

Austin

Article: 130089
Subject: Re: SiliconBlue enters the FPGA fray
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 14 Mar 2008 12:13:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 13 Mrz., 01:41, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> Peter Alfke wrote:
> > Antti, when a much smaller company (like Actel) wants to compete and
> > survive in this field, it must pick a protected niche. (Ultra- small
> > size, lowest power, non-volatility, different logic-to-pin ratio, you
> > name it!).
> > It is up to Xilinx and Altera to evaluate these "niches" and assess
> > whether they are attractive for us. Sometimes they are, sometimes they
> > are not. What is right for Actel is not necessarily right for Xilinx
> > and Altera. The user, however, benefits from the variety made possible
> > by the wide differences between companies, and their genetic
> > diversification.
> > "Survival of the fittest" combined with a diverse gene-pool. It works
> > for plants and animals...
>
> and, of course, Xilinx could always Buy them out. They did that
> to get Coolrunner, and Coolrunner is now looking 'long in the tooth'
> [in FPGA terms] with no recent advances.
> MAX IIZ and MachXO are in a space Xilinx is missing.
>
> -jg

yes, Xilinx as purchased many things for slow death.
in 2004 just before the byout by Xilinx Triscend was about to come to
the market with the FPGA devices with
ARM+ethernet+ADC+something i dont remember

Spartan-4 (ARM+eth+usb+can) will maybe only announced Q1 2009 with
real silicon availability no sooner then H1 2010

so the Xilinx by-out politics made a 6 year vacuum for those FPGA
users who wanted to have ARM+ethernet hard-core in FPGA

Antti
sorry Xilinx, I was about to obtain those devices from Triscend. Was
really disappointed they never realized.

Article: 130090
Subject: Re: DDR3 speed, Altera vs Xilinx
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 14 Mar 2008 12:31:56 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 14 Mrz., 19:55, austin <aus...@xilinx.com> wrote:
> ...
>
> ~984 hits for - Altera FPGA Hobby use - on google (no quotes).
>
> ~27,200 hits for - Xilinx FPGA Hobby use - on google (no quotes).
>
> Not that "Hobby Use" is a big line item on the financial report, but...
>
> As much as this is not a scientific survey, it is still pretty telling!
>
> Oh yes, those hobbiests are just swarming all over those Altera parts.
>
> Austin

Austin,

your "hit comparison" is example of bad(brilliant) use of google for
statistics.

the 27000 to 990 is not true ration of xilinx:hobby vs altera:hobby

fact is there are no commercial retro-compurers ever built on Xilinx
devices, all are Altera based, this has surprised my sometimes, as it
really made me also think that hobby people (at least some) prefer
Altera

of course on reason for hobby-altera is the fact that LARGEST non-BGA
FPGA device is made by Altera. And that latest Xilinx low cost family
is not all available in non-BGA packages (i dont count the tiny S3A-50
at all, as it just so tiny)

Antti

Article: 130091
Subject: Re: Xilinx S3DSP + EDK Board, too good to be true?
From: Bryan <bryan.fletcher@avnet.com>
Date: Fri, 14 Mar 2008 12:42:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
Joel,

Your analysis of the kit is accurate -- board, usb JTAG cable, and
full seat of Xilinx Platform Studio (XPS for short and also referred
to as Xilinx EDK) are included.  See http://www.xilinx.com/products/devkits/DO-SD1800A-EDK-DK-UNI-G.htm.
The list price for XPS is $495; when bundled with a kit is typically
$130.  So, you are getting a $295 + $199 + $130 value for $395.

One catch is that this is a limited time offer after which the kit
pricing goes up to $595.  And, of course the intention is to get you
hooked.

For those wondering about DDR2 support, Xilinx provides the MIG DDR2
controller in Verilog or VHDL for free.  MIG is in CoreGEN which is
part of ISE WebPack or Foundation.  Note that support for the 1800A
part on this board is included in WebPack, which is free
(www.xilinx.com/webpack).

When using MicroBlaze in XPS, the MPMC core is used and is included
with XPS.  Example designs for MIG and MPMC are available from Xilinx
and/or Avnet.  The BlueCat Linux design makes use of MPMC and the
DDR2.  Many of the current Avnet Speedways use this board's DDR2
(www.em.avnet.com/xilinxspeedway) and Avnet also has additional
designs for this board posted here (www.em.avnet.com/spartan3a-dsp).

The board is also expandable through EXP modules (www.em.avnet.com/
exp), a SystemACE controller add-on (www.em.avnet.com/systemace),  and
Digilent 6-pin ports (http://www.digilentinc.com/Products/Catalog.cfm?
Nav1=Products&Nav2=Peripheral&Cat=Peripheral).

I hope the information is helpful.
Bryan

joel.pig...@gmail.com wrote:
> Hi All,
> I was looking at the Xilinx website today and saw the new Spartan 3
> DSP EDK board.
>
> It seems like a pretty good deal, as the board by itself is 295, the
> usb JTAG cable is 199 and the EDK, well, I couldn't work out how much
> that normally costs ($130?!?) , but still thats at least $100 off the
> price assuming the EDK is free, which is extremely tempting.
>
> Am I missing something. Or is this just a good initial offering to get
> me "hooked"
>
> Thanks
>
> Joel

Article: 130092
Subject: Re: Xilinx S3DSP + EDK Board, too good to be true?
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 14 Mar 2008 13:00:25 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 14 Mrz., 19:07, John_H <newsgr...@johnhandwork.com> wrote:
> On Mar 14, 9:59 am, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de>
> wrote:
>
> > John_H <newsgr...@johnhandwork.com> wrote:
>
> > ...
>
> > > Where do you get the idea EDK is free or available for a very low
> > > price?
>
> >https://roulette.das-labor.org/bzrtrac/browser/fpga/soc-lm32/soc-lm32
>
> > --
> > Uwe Bonnes                b...@elektron.ikp.physik.tu-darmstadt.de
>
> > Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>
> I'm at a directory listing.  Nothing obvious there.  A search for edk
> comes up with no matches.
>
> Was there a specific location within that directory configuration
> where you get the idea EDK is free or available for a very low price?
>
> - John_H

John

Uwe was "teasing" you. (is that correct word?)
he wanted to point that the FREE EDK is called Mico32 :)
but was too shy to say it directly.

Antti



Article: 130093
Subject: Re: DDR3 speed, Altera vs Xilinx
From: austin <austin@xilinx.com>
Date: Fri, 14 Mar 2008 13:25:28 -0700
Links: << >>  << T >>  << A >>
Antti,

Did you actually perform the google search, and read some of the links?

It is not as crazy as it seems.

As for "retro computing" I found more Xilinx implementations that any
other (of old computers).

But, I suggest we drop this, as it really has no meaning.

Some hobby areas I am well aware of use Altera exclusively, others use
Xilinx.  It really depends on who used what first.  If the first person
used A vs. X, then that entire genre is then using A (as the first
person did all the hard work, and the easiest path is to use what the
person did before you).

Regardless, the hobby market is not one that Altera or Xilinx is going
after.

Austin

Article: 130094
Subject: Help on Virtex-II Pro global clocks.
From: Daniel <dteira@gmail.com>
Date: Fri, 14 Mar 2008 13:26:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
I'm adding new logic to an existing IP. This IP uses a DCM to manage
it's sys_clk.
My logic is using another (external) clock which is an input port to
the top level.
My logic works fine if I don't use DCM nor bufg (a global clock), but
it doesn't pass routing stage. I get this message error:

ERROR:Place:249 - Automatic clock placement failed.  Please attempt to
analyze the Global clocking required for this
   design and either lock the clock placement or area locate the logic
driven by the clocks so that that the clocks may
   be placed in such a way that all logic driven by them may be
routed.  The main restriction on clock placement is that
   only one clock output signal for any Primary / Secondary pair of
clocks may enter any region.  For further
   information see the "Using Global Clock Networks" section in the V-
II User Guide (Chapter 2: Design Considerations)
Phase 5.30 (Checksum:2faf07b) REAL time: 2 mins 11 secs

Where to start?. I guess the problem are two clocks BUFGMUX#P and
BUFGMUX#S acessing the same quadrant but what to do?. How can I be
sure of what's realy happening?.

Please help me!!!.

Thanks,
Daniel.


Article: 130095
Subject: Re: DDR3 speed, Altera vs Xilinx
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 14 Mar 2008 14:12:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 14 Mrz., 21:25, austin <aus...@xilinx.com> wrote:
> Antti,
>
> Did you actually perform the google search, and read some of the links?
>
> It is not as crazy as it seems.
>
> As for "retro computing" I found more Xilinx implementations that any
> other (of old computers).
>
> But, I suggest we drop this, as it really has no meaning.
>
> Some hobby areas I am well aware of use Altera exclusively, others use
> Xilinx.  It really depends on who used what first.  If the first person
> used A vs. X, then that entire genre is then using A (as the first
> person did all the hard work, and the easiest path is to use what the
> person did before you).
>
> Regardless, the hobby market is not one that Altera or Xilinx is going
> after.
>
> Austin

:) you say it.
well, if you have found ONE commercially produced retro computing
platform with Xilinx i would like the reference.

yes, of course, Trenz has retro-computing BASEBOARD (for xilinx
modules) but this does not count.
there is also the board from the xilinx guy, but that was never
commercially produced.

besides those I do not know any.

ah, now i understand; yes there are may REAL hobby retro projects
implemented for Xilinx FPGA

but I was talking about BOARDS designed for retro-computing as MAIN
purpose.
from those 3 are made with xilinx.

burched tried something, but it was genpurpose xilinx board + modules
combined and named as retro computer, so it doesnt count as well.

but still, if any one is aware of ONE SINGLE commercially produced
device for retrocomputing made with Xilinx FPGA I am all ears..

Antti


















Article: 130096
Subject: Re: DDR3 speed, Altera vs Xilinx
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 14 Mar 2008 14:16:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 14 Mrz., 22:12, Antti <Antti.Luk...@googlemail.com> wrote:
> On 14 Mrz., 21:25, austin <aus...@xilinx.com> wrote:
>
>
>
> > Antti,
>
> > Did you actually perform the google search, and read some of the links?
>
> > It is not as crazy as it seems.
>
> > As for "retro computing" I found more Xilinx implementations that any
> > other (of old computers).
>
> > But, I suggest we drop this, as it really has no meaning.
>
> > Some hobby areas I am well aware of use Altera exclusively, others use
> > Xilinx.  It really depends on who used what first.  If the first person
> > used A vs. X, then that entire genre is then using A (as the first
> > person did all the hard work, and the easiest path is to use what the
> > person did before you).
>
> > Regardless, the hobby market is not one that Altera or Xilinx is going
> > after.
>
> > Austin
>
> :) you say it.
> well, if you have found ONE commercially produced retro computing
> platform with Xilinx i would like the reference.
>
> yes, of course, Trenz has retro-computing BASEBOARD (for xilinx
> modules) but this does not count.
> there is also the board from the xilinx guy, but that was never
> commercially produced.
>
> besides those I do not know any.
>
> ah, now i understand; yes there are may REAL hobby retro projects
> implemented for Xilinx FPGA
>
> but I was talking about BOARDS designed for retro-computing as MAIN
> purpose.
> from those 3 are made with xilinx.
>
> burched tried something, but it was genpurpose xilinx board + modules
> combined and named as retro computer, so it doesnt count as well.
>
> but still, if any one is aware of ONE SINGLE commercially produced
> device for retrocomputing made with Xilinx FPGA I am all ears..
>
> Antti

sorry my typo, above must read:

from those 3 are made with altera!

typing too fast. should maybe follow some advice given long time ago:
"cut the 37 fingers" (then it types better)

Antti





Article: 130097
Subject: Re: Problem with Spartan 3 StarterKit
From: Alex Colvin <alexc@TheWorld.com>
Date: Fri, 14 Mar 2008 21:59:17 +0000 (UTC)
Links: << >>  << T >>  << A >>
>about 98%, it stalls for 8 seconds, and then the message
>appears : "'1' : Programming terminated. DONE did not go high"

Exactly that happens to me when I select "Verify" in the dialogue.
Loading works when I don't check "Verify".

Vielleicht hilft's.

-- 
	mac the naf

Article: 130098
Subject: Detecting a pulse with minimum width
From: "M. Hamed" <mhs000@gmail.com>
Date: Fri, 14 Mar 2008 15:18:28 -0700 (PDT)
Links: << >>  << T >>  << A >>
I have an input signal that is required to be high for a certain
length in time before a halt request is issued to a processor. To
detect this signal, three solutions popped into my head.

1- A shift register with all bits ANDed together. The output is taken
from the AND gate and will not be high unless the signal has passed
completely through the pipeline without going to zero(except for any
glitches that wasn't captured by the first FF.

2- A shift register with the Reset line (active low) of all the FFs
tied to to the signal. The output is taken from the last FF. In such a
case the last FF will never be 1 unless the signal was high for the
whole period while passing through the entire pipeline. If it goes to
zero any time before that, then all FFs (and hence the last FF) will
be zero. This solution may be more elegant than the first since it
doesn't really matter how long the pipeline is, while in the first,
the more stages, the bigger the AND gate. It would also detect any
glitches on the signal.

3- Divide the master clock using a binary counter until the desired
time length is achieved, then use a variation of the previous two
schemes but with a much reduced shift register length.

Which solution would you choose? Are there any better approaches? I
would personally choose the third solution combined with the second,
since it means fewer FFs can be used for longer required times, and
any glitches will invalidate the pipeline.

Thank you!

Article: 130099
Subject: Re: DDR3 speed, Altera vs Xilinx
From: gavin@allegro.com (Gavin Scott)
Date: Fri, 14 Mar 2008 22:26:59 -0000
Links: << >>  << T >>  << A >>
austin <austin@xilinx.com> wrote:

> Some hobby areas I am well aware of use Altera exclusively, others use
> Xilinx.  It really depends on who used what first.  If the first person
> used A vs. X, then that entire genre is then using A (as the first
> person did all the hard work, and the easiest path is to use what the
> person did before you).

> Regardless, the hobby market is not one that Altera or Xilinx is going
> after.

It's not a "market" it's a marketing/advertising opportunity.  If I 
were A or X I think I'd hire a full-time product-evangelist engineering
position and task them with getting products into the hands of new 
users and supporting the "hobbyist" people.  Make a $10 battery
powered demo board with some blinkenlights and give them away to
pretty much anyone who wants one.  Send someone to the Maker Fair
and similar venues with a few hundred giveaway boards and CDs with
WebPack etc.  Sounds like pretty cheap advertising to me.

Austin's two paragraphs above only make sense together if he believes
that no hobbyist ever turns into (or even communicates with) a 
professional FPGA-using engineer.  Otherwise half of the game is
getting more mindshare than the competition and having people feel
good about your brand and tools when someday someone says "hey, 
maybe we should use an FPGA for this application".

There's a lot of profit in having your brand be the first one that
people encounter.

G.



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