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Andrea05 wrote: > Hi everybody, > i' trying to realize a custom OPB peripheral using EDK. > In my design I need a register in which one bit should be written by > software and by the peripheral itself. > > Ok... I'll try to explain it better. > > I would like to set a bit of one register from software to tell the > peripheral to start to work. When it has finished, i'd like that the > peripheral sets to ' 0 ' the same bit in order to communicate that the > work is done. In this way setting again the bit to ' 1 ' the > peripheral will start to workagain, and so on. > > The problem is: when I syntethize the peripheral I got the error: > > Multi-source in Unit <user_logic> on signal <slv_reg3(0)> > > I think it's due to the fact that the bit is written by the bus (via > software) and by the peripheral... > > How can i fix this problem? > > It seems that the SW register of the OPB peripherals in EDK can't be > written by the peripheral itself (this means that it's useless to try > to read that register from software).... > > How can I get information from software about the peripheral if the > register can't be written by the periperal? > > I'm quite new to this stuff and I hope my problem is clear (despite of > my poor english) > > Thanks a lot, > > A. Look at the IPIF examples, because that is what you are ultimately trying to build. You specify how many registers to reserve, and then you connect the registers to your design. Alternately, you can do the address decoding further down, but it's pretty easy to let the IPIF layer handle it.Article: 120701
On Jun 13, 9:00 pm, "davide" <dav...@xilinx.com> wrote: > J.Ram, > > You have selected to do a verify in iMPACT after configuration. This is why > iMPACT is looking for the .msk file. You have two options here. Either > deselect the verify operation or have Bitgen create the mask file for you > when you generate the bitstream. Look to the Bitgen documentation on using > the -m switch for this:http://toolbox.xilinx.com/docsan/xilinx9/books/docs/dev/dev.pdf > > -David > > "J.Ram" <jrgod...@gmail.com> wrote in message > > news:1181732731.232269.185750@d30g2000prg.googlegroups.com... > > >I have generated a .bit file and try to program xc2v3000 FPGA but > > through impact gives a message that checking done pin.............done > > pin do not high , program terminated. > > so i verify operation in impact and impact gives a error message that > > top_design.msk does not exist . > > my qustion is where .msk file will be generated and is it really > > needed during programming FPGAs. > > i checked all other probable error possibilities , so please give > > comment. Thanx david, give comment on why done pin do not go high.Article: 120702
> Thanks for your inputs, Andy. From your comments, it looks like I am > using the right tool, I've recently found a problem (not quite sure > whether it is a "feature" ) with Synplify Pro. The latest version of > Synplify Pro [8.8.0.4] overconstraints the timing of the design and > the 8.4 version had the problem of confusing itself with DIFFM/DIFFS > and IOB, the idea of comparing those two tools was to find a backup > when one tool fails I can still try the other one. If it fails, get straight on to support. That's what you paid all that money for. Cheers, JonArticle: 120703
In news:98c073t4kmbr3mcc4rqfdvuf1rjtouljpd@4ax.com timestamped Wed, 13
Jun 2007 19:31:14 +0100, Evan Lavelle <nospam@nospam.com> posted:
"I'm afraid that you are, and I'm trying to be polite here,"
Thank you for being polite.
"completely
wrong. SystemC does not operate the way that you think it does,
[..]
[..]"
What did I say that is wrong?
"Some simple Googling might convince you. Look up any thread that
discusses an endless loop which hangs up a Verilog or VHDL simulator.
How is this even possible with your world view?
2 minutes on Google found a simple explanation of how event-driven
simulation works, from Janick Bergeron. This is exactly what I've said
several times in this thread, but you may find it more believable from
Janick; see
http://groups.google.co.uk/group/comp.lang.vhdl/browse_frm/thread/3941f0c5edac84fa/ae8567e741594acb?lnk=st&q=endless+loop+group%3Acomp.lang.vhdl&rnum=6&hl=en#ae8567e741594acb
[..]"
Did I deny event-driven simulation exists? It is possible for
event-driven simulation to be implemented concurrently and for
simulated time to not advance at all due to an infinite number of
delta cycles stuck in a feedback loop. Paul J. Menchini gave an
example of such a feedback loop in the same thread you cited.
"[..]
I'm happy to discuss this with you if you have a specific
objection,"
Thank you.
"or can demonstrate that the SystemC kernel does not also behave in
this way (and it most emphatically *does*),"
I never said that it does not also have delta cycles.
" but it really isn't
helpful to add lots of irrelevant extras when replying to posts."
Sorry, I did not intend to add irrelevant extras. I am not sure which
ones I did, but here may be a few examples which I did not think were
irrelevant but if you want you can save time by ignoring the rest of
this post: I was asked "what is SystemC(R)?" so I explained that I am
supposed to use a registered trademark symbol and that I am supposed
to refrain from using "SystemC" as a noun; it was claimed that Unix
runs one process at a time without an admission that Unix can run more
than one process at a time and I was asked am I "aware of any VHDL or
Verilog implementations which exploit 'concurrent hardware'?" so I
showed evidence that a Unix clone can run more than one process and
that unfortunately NCSim does not exploit this; and you did not recall
"any specific discussions" from one of the SystemC.org forums about
how using a multiprocessor computer with an OSCI reference implementation
does not scale whatsoever so I showed two examples of such discussions.
Regards,
Colin Paul Gloster
Article: 120704
LogicSim v3.0, an affordable and user-friendly Verilog simulator for
ASIC and FPGA design verification is finally here. This is a major
release that contains many new features, updates and bug fixes.
Below is a summary of major features new in this release:
* Added 64-bit simulation time kernel support. In other words,
simulation time unit can now go up to 18,446,744,073,709,551,616,
which previously could only go up to 4,294,967,296.
* Added support for moving signals around with mouse Drag & Drop
in waveform viewer.
* Added support for multi-radix conversion in waveform viewer.
* Added support for sorting signals by signal names in waveform
viewer.
* Added support for pausing simulation for while simulation is
running. This is especially useful for designs that takes hours to
days to simulate.
* Added support for displaying progress of simulation time in
status bar. This is especially useful for designs that takes hours to
days to simulate.
* Added support for displaying partial waveform while simulation
is paused.
As you see, we have improved the project workspace and waveform viewer
substantially in this release. The simulation kernel itself has become
very stable now, which we hardly receive any bug reports. Besides new
features, we have also updated many existing features, and fixed many
important bugs. Please check out the release notes for more info.
I'd like to thank those who continue submitting bugs and feedbacks.
Without them, we would not be able to improve our software.
You can find this press release at: http://www.zeemz.com/blog/
To download LogicSim v3.0, please go to: http://www.zeemz.com/
Joe,
Zeemz, Inc.
Article: 120705Hi everybody I am trying to familiar to xps software .So i am trying to create a peripheral using 2kb bram block in which we can read or write. I have written verilog code for a bram controller atteched to opb bus.Now i have to write a c code which perform read and write operation in that bram block.Regarding this i have following confusion in my mind 1-For write operation following signal should be given in sequence a- m1request b-opb select c-opb address bus d-opb data bus ... etc opb bus has different frequency as that of microblaze processor ..how is it possible to put these signal on bus in sequence by a c programe.C Can anyone suggest some solution or give a model code for our reference ? thanks in advance rajivArticle: 120706
On Jun 11, 10:53 pm, "Roger" <enquir...@rwconcepts.co.uk> wrote: > I've been using a certain make of fibre-optic transceiver to provide optical > RIO connectivity at the full 3.125Gbps rate. The manufacturer has dropped > the parts I've been using and I'm now looking for an alternative. > > Has anyone else used optical links and if so, what transceiver did you use? > > TIA. > > Roger. Years ago i used trx from http://www.stratosoptical.com and they are still working. I think the company has still this product lineArticle: 120707
On 13 Jun., 16:52, "Amontec, Larry" <laurent.ga...@ANTI- SPAMamontec.com> wrote: > ON NEXT MONDAY : 17-JUNE-2006 > > Amontec will provide the 'how-to' program via a XILINX VIRTEX XC4VLX25 > 7.9Mbits bit stream) at 2.8 seconds using the Amontec JTAGkey ! > > On next Monday, your Amontec JTAG key will be close to the speed of a > Xilinx Platform Cable USB for programming any FPGA and CPLD vendors > (Altera Xilinx Lattice Cypress ...) > > Come back next Monday onhttp://www.amontec.com! > > Laurent Hi Laurent when making public announcements its generically a good idea not to lie.I am quoting your website: "On next Monday, your Amontec JTAGkey will receive the speed of a Xilinx Platform Cable USB for programming any FPGA (Altera Xilinx Lattice Cypress ...)" Platform USB Cable is USB HS Device, with dedicated CPLD for JTAG. It can support 24Mbit JTAG clock Amontec Key, is FT2232 a USB FS device with kinda support for JTAG with max bit rate of 6MBit the fact that it may take same time to program some FPGA under some condition with those 2 programmers doesnt really mean that amonteckey is as same speed as xilinx platform usb. the very next update to xilinx cable FW and or CPLD may increase the xilinx speed to the theoreatical maximum, that is at 4 times the speed any FT2232 MPSSE solution (without extra CPLD) can ever support. 4 times is not "same" to me. or have you find a way to convert FT2232 to HS device? or are you offering a HS USB solution to all customers? sorry, but I preffer when technical matters are explained correctly. AnttiArticle: 120708
I´m developing a FSL Peripheral. I´m having the following problem:
when trying to generate the bitstream it generates the error:
ERROR:MDT - issued from TCL procedure
"::hw_fsl_v20_v2_10_a::check_syslevel_settings" line 14
fsl_v20_0 (fsl_v20) - FSL_Clk is unconnected.
ERROR:MDT - issued from TCL procedure
"::hw_fsl_v20_v2_10_a::check_syslevel_settings" line 14
fsl_v20_1 (fsl_v20) - FSL_Clk is unconnected.
Looking at the system.mhs file I found:
BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_0
PARAMETER HW_VER = 2.10.a
END
BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_1
PARAMETER HW_VER = 2.10.a
END
But I expected to find something like:
BEGIN fsl_v20
PARAMETER INSTANCE = download_link
PARAMETER HW_VER = 1.00.b
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst
PORT FSL_Clk = sys_clk
END
I suppose this is the problem but I can´t just edit the file because
it seems to be regenerated (missing the ports again) every time I try
to generate the bitstream. Can anyone help me? Thanks
Article: 120709You can edit it when EDK is closed. This file should not be regenerated if you generate bitstream. I did it a lot. --WayneArticle: 120710
Wouldn't it be better to check and make sure it is connected correctly in the Bus view? And the Port view? You can filter the ports to display All and see where everything on the FSL is going.Article: 120711
On Jun 14, 7:47 am, Antti <Antti.Luk...@googlemail.com> wrote: > the fact that it may take same time to program some FPGA under some > condition with those 2 programmers doesnt really mean that amonteckey > is as same speed as xilinx platform usb. That depends on if it's true in a specific case, or if it's true in general. The theoretical speed of well designed hardware is unimportant, what matters is the speed of the available-to-users hardware + software system. Unless of course you end up limited by signal integrity issues instead...Article: 120712
On 13 jun, 19:40, "MM" <m...@yahoo.com> wrote: > "Pablo" <pbantu...@gmail.com> wrote in message > > news:1181755261.328091.228890@i38g2000prf.googlegroups.com... > > > > > I have a custom board with a Micron memory. The company has said to me > > that I should use a xilinx core but I have to modify this because they > > said that their memories use internal loopback. I have tried to modify > > these signals but this doesn't work. > > If I understand your question correctly, take a look at the reference design > at the link below. It shows how to close the feedback loop internally. I > guess, depending on the hardware, you might need to introduce some delay in > this path...http://www.digilentinc.com/Data/Products/FX12/FX_12_BIST_Clean.zip > > > Finally I have decide to implement the core neccesary for this but I > > don't know how could I integrate this with xps, since I need to use > > XMD for PowerPC debug. > > > So, I need some recommendation about how to create a core for my DDR > > Sdram and integrate in my PowerPC model (in XPS) so I could use XMD > > for download the application in this memory. > > XMD has nothing to do with the core. What exactly are you going to > implement? Integrating a peripheral into XPS isn't that difficult. Copy the > PLB_DDR core from the > %Xilinx_EDK\hw\XilinxProcessorIPLib\pcores\ directory into your projects > pcores directory and edit the source files however you want. Restart XPS or > rescan project repositories, XPS will pick up the local version of the core > instead of the one in the EDK tree. > > /Mikhail Thanks for your reply. Respect to the project you send me, I cannot see the vhdl code related to the ddr control. Where do I look for?. Once again I am very grateful for your help RegardsArticle: 120713
>On Jun 13, 3:09 pm, "cutemonster" <ckh...@hotmail.com> wrote: >> >On Jun 10, 2:38 pm, "cutemonster" <ckh...@hotmail.com> wrote: >> >> >So you want to display a stroke signal on monitor? >> >> >Why you need to sample the X? Is it time dimension? Is it a constant >> >> >ramping, or ramping with retrace, or random? >> >> >> I have to sample x and y because it doesn't work like raster signal. >> It's >> >> voltage varies in time. There is another signal input called >> Unblank(TTL). >> >> It turn on and off of XY signal. >> >> >Have you tried to lock the sampling clocks to the unblank? >> >> No, I don't understand how to lock it with sampling clock. Can you please >> explain? >> >> thanks > >Locking the clock to the unblank meaning that their phase relation is >fixed. For some reason I can't escape from the time dimension :) If >you just sample for 1 frame then probably you don't need to do >locking. Do you sample just 1 image then display it continuously on >the raster? > >If you capture it as live video or multiple frames, then how can you >tell which pixels belong to frame n, which belong to frames n+1, n >+2,... > >Regards, > > > > Yes, I tried synchronous and asynchronously to Unblank signal. There are two problems. The first one is the noise itself with the stroke signal and the second one is the stroke signal being drawn at the second time doesn't being drawn at the exact position. It's like one pixel toggling between frames. Do you know which kind of filter fit the best in this situation? thanks for you suggestionArticle: 120714
On Jun 14, 5:55 am, rajiv...@gmail.com wrote: > 1-For write operation following signal should be given in sequence > a- m1request > b-opb select > c-opb address bus > d-opb data bus ... etc > > opb bus has different frequency as that of microblaze processor ..how > is it possible to put these signal on bus in sequence by a c > programe.C Well, usually, you hook things up so that your processor handles all of that for you. Your peripheral would either be memory mapped, in which case you just need to learn about using the "volatile" tag and absolute hardware address to convince your C compiler to really access the memory. Or else your peripheral is io mapped, in which case you have to use the approrpiate process to access io space. Rarely, someone will map the control signals for a device into registers that are in turn memory mapped or io mapped, and it will be up to software (perhaps a kernel mode driver) to toggle the bits to accomplish the necessary sequence of operations. In that case, you'd just do a bunch of memory or io accesses to accomplish the script you gave. ------- No meaning to personally target you here, but can I ask a general question: what is up with the recent flood of people apparently having no background embedded programming experience playing with soft core FPGA processors? Generally, you want to have some experiencing programming embedded processors before you try to make your own customized embedded processor...Article: 120715
On Jun 13, 4:09 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > jjlind...@hotmail.com wrote: > > Hello, I was wondering if anyone is using Incremental Compilation in > > Quartus 7.1 and if so, could you comment on it. Is it worth the time > > using IC or is doing Full Compilation better. > > I don't mind letting my computer do extra work > as long as it doesn't take too long. > > So far, it doesn't take too long, > so I keep it simple. > > -- Mike Treseler I have a questions about creating design partitions. Altera recommends that the partition be less than 1000 LEs or 1000 ALMs, any ideas what happens if the partitions are small? thanks, joeArticle: 120716
Hello, I'm looking for opinions on using LogicLock in Quartus II, is it useful or a waste of time? What are some of your experiences with LogicLock? thanks, joeArticle: 120717
Joerg wrote: > > That can backfire, big time. Many vendors think that only large > companies matter and fail to see that it's often the little guys like us > consultant who really call the shots. Meaning their (big) client's > engineers trust their decision and stick with it. I've had sales guys > literally beg me to reconsider but in pretty much all cases it was too > late. When the work is done a consultant cannot saddle a client with > more NRE just because a vendor shows remorse about not having supported > what they thought was "only a little guy". > > A lot of companies, including nearly all European semi mfgs, don't even > know what they have missed out on so far. Never will. And if they don't know what they have missed out on, why would you expect them to take these missed opportunities into account??? They can only work with the info they have. That is why it is important for you to explain to the vendors what the potential of a given product is. I have been in this position before. Not only did I get samples, when I had some issues I got very good support (partly to cover some mistakes on the part of the vendor) and I was given very good pricing all things considered. So communicate with your distis and reps. Don't treat them like the enemy, treat them as what they are, a business partner.Article: 120718
> > A lot of companies, including nearly all European semi mfgs, don't even > > know what they have missed out on so far. Never will. > > And if they don't know what they have missed out on, why would you > expect them to take these missed opportunities into account??? They > can only work with the info they have. I agree with Joerg on that. Clearly they can act only based on informaton they have, but if they have not got it in 2007 how the electronics industry works when it comes to designing new products they won't get it/change their attitude no matter what info you give them other than order zillions (which would impress any person from the street, it does not take any qualified personell to act on that). They just have guaranteed busyness and as long as they don't have to fight for survival they won't care. This is valid not only for European, also for American and whatever companies. Not all of them, of course (and I believe the percentage among European is higher as Joerg suggests. Some - many - are really good to deal with, about data, samples and all. > So communicate with your distis and reps. Don't treat them like the > enemy, treat them as what they are, a business partner. Well, while this is a valid point it is also the obvious approach. The question is what happens next when the vendor tells you "make me a $20M/quarter revenue first and we'll consider whether to provide you under NDA with the data you requested"... or something like that. (I know it sounds like a joke but I did get this reply from Xilinx several years ago...). Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ http://www.flickr.com/photos/8359035@N02/sets/72157600228621276/ On Jun 14, 9:24 pm, rickman <gnu...@gmail.com> wrote: > Joerg wrote: > > > That can backfire, big time. Many vendors think that only large > > companies matter and fail to see that it's often the little guys like us > > consultant who really call the shots. Meaning their (big) client's > > engineers trust their decision and stick with it. I've had sales guys > > literally beg me to reconsider but in pretty much all cases it was too > > late. When the work is done a consultant cannot saddle a client with > > more NRE just because a vendor shows remorse about not having supported > > what they thought was "only a little guy". > > > A lot of companies, including nearly all European semi mfgs, don't even > > know what they have missed out on so far. Never will. > > And if they don't know what they have missed out on, why would you > expect them to take these missed opportunities into account??? They > can only work with the info they have. > > That is why it is important for you to explain to the vendors what the > potential of a given product is. I have been in this position > before. Not only did I get samples, when I had some issues I got very > good support (partly to cover some mistakes on the part of the vendor) > and I was given very good pricing all things considered. > > So communicate with your distis and reps. Don't treat them like the > enemy, treat them as what they are, a business partner.Article: 120719
On Jun 14, 11:17 am, "cutemonster" <ckh...@hotmail.com> wrote: > Yes, I tried synchronous and asynchronously to Unblank signal. There are > two problems. The first one is the noise itself with the stroke signal > and the second one is the stroke signal being drawn at the second time > doesn't being drawn at the exact position. It's like one pixel toggling > between frames. > > Do you know which kind of filter fit the best in this situation? > > thanks for you suggestion- Hide quoted text - > > - Show quoted text - Sounds like you capture it as live video or multiple frames. In such case you would need to synchronize or lock the clock to a reference, the unblank may be? Having no idea what the unblank looks like so I can't tell how to do it, how often does the unblank recycling? Having a good synchronized clock with low jitter is, IMHO, much easier than doing the filter to minimize the artifact of pixels toggling positions between frames For the spatial noise, If I was you I would try a high order analog filter infront of the A2D first, before doing any digital filtering Regards,Article: 120720
> Respect to the project you send me, I cannot see the vhdl code related > to the ddr control. Where do I look for?. When you design with EDK you don't normally need to go down to VHDL or Verilog code unless you are designing your own cores. In the case of the design I mentioned, all of the cores are from the Xilinx EDK library (the PLB_DDR core is for sure from the EDK library), so there isn't really any need to look for the code. To see how the cores are connected take a look at the system.mhs file. /MikhailArticle: 120721
J.Ram, There are numerous reasons on why DONE will not go high. If this is happening while you have verify selected and still have not generated a .msk file, then I might expect this. If you have deselected the verify option and DONE is still not going high, then it is time to start debugging. May I recommend the configuration debugger on the Xilinx Web site for starters. http://survey.xilinx.com/ss/wsb.dll/Xilinx/Configuration_Debug_Guide.htm This is a comprehensive step-by-step guide that will start at the common pitfalls and work its way to more complex issues. Go through this and let me know how things progress. -David "J.Ram" <jrgodara@gmail.com> wrote in message news:1181796433.817901.239710@g37g2000prf.googlegroups.com... > On Jun 13, 9:00 pm, "davide" <dav...@xilinx.com> wrote: >> J.Ram, >> >> You have selected to do a verify in iMPACT after configuration. This is >> why >> iMPACT is looking for the .msk file. You have two options here. Either >> deselect the verify operation or have Bitgen create the mask file for you >> when you generate the bitstream. Look to the Bitgen documentation on >> using >> the -m switch for >> this:http://toolbox.xilinx.com/docsan/xilinx9/books/docs/dev/dev.pdf >> >> -David >> >> "J.Ram" <jrgod...@gmail.com> wrote in message >> >> news:1181732731.232269.185750@d30g2000prg.googlegroups.com... >> >> >I have generated a .bit file and try to program xc2v3000 FPGA but >> > through impact gives a message that checking done pin.............done >> > pin do not high , program terminated. >> > so i verify operation in impact and impact gives a error message that >> > top_design.msk does not exist . >> > my qustion is where .msk file will be generated and is it really >> > needed during programming FPGAs. >> > i checked all other probable error possibilities , so please give >> > comment. > > Thanx david, > give comment on why done pin do not go high. >Article: 120722
Pete, I think that you hit the solution right on with the .ise file being on the desktop. The last think I want to do is open up a can of worms regarding spaces in a path, but it apparently still has some issue from this posting. As a rule of thumb, ensure that the directory structure does not contain spaces or use underscores as whitespace. Glad to hear that it is resolved. -David "Pete Fraser" <pfraser@covad.net> wrote in message news:13711n9h0o9pce7@news.supernews.com... > "davide" <davide@xilinx.com> wrote in message > news:f4pvvu$arf2@cnn.xilinx.com... >> Pete, >> >> I can double click on my .ise file and can launch the GUI. A couple of >> things that you may want to check out. Look at the properties of the >> .ise file and verify that Read-only is not selected. > > I checked that. > Assuming you're talking about the Windows properties, that was OK. > >> Also verify that the file type associated with the .ise file is Xilinx >> ISE Project. Let me know how it goes. > > It may be that ProjNav still has a problem with long paths > or spaces in directory names. I moved the folder from the desktop, > and it seems OK now. > > Thanks > > > >Article: 120723
Hi. I am working with Alera Quartus software on FPGA realization of STFT(Short Time Fourier Transform) and I have one problem. I am constantly getting this waring "Warning: Circuit may not operate. Detected 140 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay." Shortly: I create one entity "A", compile it and I don't get this warning (I dont have that "non-operational paths" in this project), but when I use this entity for some other project I get this worning saying me that this "non-operational paths" are in previosly create "A" entity. I am not shure that I know what this non-operational paths are. Could anybody help me about this. Any kind of help would be precious to me. ThanksArticle: 120724
On Jun 14, 10:48 am, motty <mottobla...@yahoo.com> wrote: > Wouldn't it be better to check and make sure it is connected correctly > in the Bus view? And the Port view? You can filter the ports to > display All and see where everything on the FSL is going. Editing the MHS is totally safe. There are ports that do not necessarily show up in the Ports/Bus view. For example, on the V4 the ports for the hard temac's DCR do not show up. They are necessary if you want to simulate the interface, but have nothing to do with synthesis. If you switch to the ALL view, the ports can become impossible to filter to find exactly what you were looking for. I do most of my editing of the MHS directly and then use XPS from the command line to generate my makefiles. I then execute the makefiles from the command line as well. I'm also a huge fan of the console, versus gui :). Yes, you do not want to edit the MHS file, even with EDK, while the project is open inside of EDK. You do not have to close EDK, just the project. The MHS is your Hardware Specification file and will change everytime you make a change in EDK for the Bus/Ports. FTR, the MSS is the Software Specification file and that is changed when you make changes under the Software settings or the Application's tab. FPGA Guy: you can edit the MHS file in your favorite text editor, while the project is not open in EDK. Or, you can make the modifications from Ports view in EDK. Once you expand the pcore for the fsl bus, you should see the Port's listed. You can then add whatever value suits your or heart.... or whatever value will actually work. -- Mike
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