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Hi, I have created a .vcd file using modelsim and am trying to estimate the power consumption for my design. The problem is when I load this vcd file in the XPower it gives warnings as shown below. WARNING:Power:1087 - Can't change frequency of net CLK to 40.00Mhz WARNING:Power:90 - Can't change activity rate of net y1_inst/inst1/BU2/U0/virtex4.pmf.v4pm48/single_dsp.v4_parm_18x18/p_i<23> to 10.0% of CLK_BUFGP. WARNING:Power:90 - Can't change activity rate of net y1_inst/inst1/BU2/U0/virtex4.pmf.v4pm48/single_dsp.v4_parm_18x18/p_i<22> to 10.0% of CLK_BUFGP. WARNING:Power:90 - Can't change activity rate of net y1_inst/inst1/BU2/U0/virtex4.pmf.v4pm48/single_dsp.v4_parm_18x18/p_i<21> to 10.0% of CLK_BUFGP. WARNING:Power:90 - Can't change activity rate of net y1_inst/inst1/BU2/U0/virtex4.pmf.v4pm48/single_dsp.v4_parm_18x18/p_i<20> to 10.0% of CLK_BUFGP. It sets the clock frequency automatically to 10 MHz irrespective of what I use in my simulation. I am using ISE 8.2i. Can anyone pls help me with this? Thanks SaumilArticle: 120851
Hi , Yes I have included this in the periperal analyze order (Pao ) . The problem is When I try to add a coregen IP ( I generated the IP with Verilog becoz I was more comfortable with that) to my EDK , I followed all the necessary steps. EDK defaultly thinks that I have the generated the IP using Coregen using VHDL option and goes to the directory : Fifo_test_v1_00_a/hdl/vhdl/simpl_tx.vhd But It shoud actually go to the directory Fifo_test_v1_00_a/hdl/verilog/simpl_tx.v I dont know which script file to change . Please help me asap. On Jun 19, 12:10 am, motty <mottobla...@yahoo.com> wrote: > Is your pao file implemented correctly? That's the first thing that > popped into my head. > > So is the simpl_tx (that is how you spelled it above - maybe that's > the problem?) a verilog file? As far as I know, the pao needs to > specify that in the analyze order. There's no reason that you can't > have a FIFO core ngc and HDL files in the same IP.Article: 120852
Hi gseegmiller, Do you have an uart16550 or do you use the opb_uartlite? If you are using the uartlite the you have to change the cmd line for the kernel. console=ttys0,9600 is for the uart16550. think it should read this for the uartlite. console=ttyl0,9600 best regards LasseArticle: 120853
are you sure your test bench is correct ? did you purge the projects files ? I have a linux station and webpack ISE9.1.03i, synt. and simul, impact, chipscope... are more stable than the same tools on the same station with windows XP (no freeze while xst or par, impact/usb works fine...) see console and log and add the missing tools / libraries / access rights... On Jun 18, 11:01 pm, Duth <premd...@gmail.com> wrote: > On Jun 18, 1:45 pm, Duth <premd...@gmail.com> wrote: > > > > > On Jun 17, 3:33 pm, Ankit <ankitanand1...@gmail.com> wrote: > > > > Hi guys.. > > > > A few days back I installed xilinxISEwebpack 91i on fedora core 6 > > > everything worked out fine but i have not been able to simulate the > > > testbench using thesimulatorprovided by xilinx..whenever i double > > > click on simulate behavioral model nothing happens..guys do help me > > > out i am in a fix.. > > > > Regards > > > Ankit > > > Hi Ankit, > > > I am afraid that Fedora 6 is not a supported OS for Xilinx SW. > > Although since you are able to get all the other SW to work fine and > > it is onlyISESimulatorthat is giving you trouble, let us see if we > > can come up with a fix. > > > Thanks > > Duth > > Hi Ankit, > > We might have something that could work. Can you try the following: > > mv $XILINX/gnu/gcc/3.2.3/lin/bin/ld $XILINX/gnu/gcc/3.2.3/lin/bin/ > ld.old > ln -s /usr/bin/ld $XILINX/gnu/gcc/3.2.3/lin/bin > mv $XILINX/gcc/3.2.3/lin/i686-pc-linux-gnu/bin/ld $XILINX/gcc/ > 3.2.3/lin/i686-pc-linux-gnu/bin/ld.old > ln -s /usr/bin/ld $XILINX/gcc/3.2.3/lin/i686-pc-linux-gnu/bin > > If this is a 64 bit machine, please use lin64 instead of lin for the > path. > > Please let me know if this does not work. We might have to do the same > for collect2 as well. > > Thanks > DuthArticle: 120854
for edu. purpose, I would like to modify s3astarter_ddr2 design to use it with picoblaze (store some data to ddr2 and read them back later). I understand I have to hack vhdl_xst_bl8_ddr2_test_bench_0 according my needs replacing addr_gen, cmd_fsm,... and connect picoblaze external bus to memory. This is my first memory controller design and a bit too hard. Does anybody have some sample, reference design, guidelines... (this is for spartan 3A starter kit, I am looking for the same design for 3E starter kit DDR sdram) I do not want to use an EDK design. regards, raphArticle: 120855
Hi, I have designed a IP core, how can i add my IP to EDK? Anyone who can help me?Article: 120856
On Jun 19, 10:12 am, rbmm...@gmail.com wrote: > Hi, > I have designed a IP core, how can i add my IP to EDK? > Anyone who can help me? choose the right bus : fsm, opb, (there is a wizard) then map your core, then write the drivers code, then test it...Article: 120857
Alvin Andries wrote: > "Al" <alessandro.basili@cern.ch> wrote in message > news:f52tma$dcc$1@cernne03.cern.ch... > >>Hi everyone, I have a strange behaviour in my implementation even if the >>design is pretty simple (even if it's very dense!). >>I have a decoding block which gets "address" to write data into several >>registers. The decoding block is such that it will produce an enable >>signal for each single register. Then a "write" signal is distributed >>with some latency such that propagation delays are taken into account. >>What I find is that for postsynthesis simulation everything is fine, but >>in my postlayout I have some addresses which are enabled even if the >>address is another one, turning out that I write two registers at once. >>I can't really understand why! >> >>Here is a sketch of my vhdl code: >> >> >>>-- decoding signals >>>p_signal1 <= '1' when addr = x"123" else >>> '0'; >>>p_signal2 <= '1' when addr = x"456" else >>> '0'; >>> >>> >>>-- writing process >>> >>>process (clk, nrst) >>>begin >>> if nrst = '0' then >>> signal1 <= '0'; >>> signal2 <= '0'; >>> elsif rising_edge (clk) then >>> if wr = '1' then >>> if p_signal1 = '1' then >>> signal1 <= data; >>> elsif p_signal2 = '1' then >>> signal2 <= data; >>> ... >>>end process; >> >>So it happens that writing to addr = x"123" it will change signal2 as >>well...how can it be possible??? >> >>I did prefer to have "p_signals" and not use directly the "addr" in the >>process just because in the very beginning I thought about latching the >>"p_signals" to have them stable, but then I realized it wouldn't have >>fit in the logic (I have already an occupancy of 84% and I have more >>than 300 addresses to decode). >>Do you have any explanation of this behaviour? > > > Hi Alessandro, > > What do you mean with postsynthesis and postlayout? Gatelevel with and > without timing? Well, the postlayout is gatelevel with timing of logic elements but not the routes (I think there's just an estimation of which will be the route and timing is computing based on this estimation). Postlayout is considering the actual routes after place&route process and all delays are taken into account. Moreover I had to implement a simulation considering the INDUSTRIAL ranges in temperature and voltage to take into account timing changing according to these two parameters. > > Also, what did you do with your write signal? Normally, you wouldn't have to > delay it in a synchronous environment. > Unfortunately the p_signals are really many, in the order of 300 and, for the Actel chip I'm using, there's a long delay introduced in the decode chain of all this combinatorial logic. That's why, to overcome this, I needed to add some latency in the write signal which will allow me to have the data stable and the p_signal stable when the write signal arrives. > Your code seems ok, even though I would replace the elsif p_signal2 by > regular ifs: the reason is that you're now describing a priority decoded > block, whik this is unnescessary. > I agree with you, even if I thought that the if elsif structure would have been much simpler to write, otherwise I have to implement a process for any register, turning out with a less readable code. But I will try with a case when structure and try to see if there are any differences in the implementation. By the way I did registered the p_signal, fearing that the synthesizer would have put the write signal at the very beginning of the chain instead at the end, but the simulation didn't work either. > Regards, > Alvin. > > -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 120858
Hey Duth..
Hi..Thanx for taking time and replying to my query..I
have been trying to run the command you mentioned in your posts but
this what it says..
[ankit@localhost Xilinx91i]$ mv $XILINX/gnu/gcc/3.2.3/lin/bin/ld
$XILINX/gnu/gcc/3.2.3/lin/bin/
mv: cannot stat `/gnu/gcc/3.2.3/lin/bin/ld': No such file or directory
Plus i am a liitle new to linux so pleas dont mind if 1 of my queries
turn out to be stupid..
I ran these commands in the terminal i am hoping thats where i should
have run them..Or i should have executed these in the TCL shell..
Please do help me out of this dilemma as my mentor is admanat that i
run Xilinx on linux..
Waiting for your reply..
Regards
Ankit
Article: 120859On 19 Jun., 09:58, rpons...@gmail.com wrote: > for edu. purpose, I would like to modify s3astarter_ddr2 design to use > it with picoblaze (store some data to ddr2 and read them back later). > > I understand I have to hack vhdl_xst_bl8_ddr2_test_bench_0 according > my needs replacing addr_gen, cmd_fsm,... and connect picoblaze > external bus to memory. > > This is my first memory controller design and a bit too hard. Does > anybody have some sample, reference design, guidelines... > (this is for spartan 3A starter kit, I am looking for the same design > for 3E starter kit DDR sdram) > > I do not want to use an EDK design. > > regards, raph unfortunatly NO, there is no open free simple easy MIG demo design known. the only way to actually use DDR2 on Spartan-3A board is currently the EDK design Antti From laurent.pinchart@skynet.be Tue Jun 19 04:41:22 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!nx02.iad01.newshosting.com!newshosting.com!newsfeed.icl.net!newsfeed.fjserv.net!newsfeed.freenet.de!feeder.news-service.com!feeder.news-service.com!216.196.110.148.MISMATCH!border1.nntp.ams.giganews.com!nntp.giganews.com!newsfeeder.wxs.nl!kramikske.telenet-ops.be!nntp.telenet.be!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-Id: <4677c0e2$0$13852$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: How to simulate testbenches using the ISE simulator in linux Newsgroups: comp.arch.fpga Date: Tue, 19 Jun 2007 13:41:22 +0200 References: <1182116017.579060.135360@d30g2000prg.googlegroups.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 21 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 48830bda.news.skynet.be X-Trace: 1182253282 news.skynet.be 13852 194.78.198.49:58886 X-Complaints-To: usenet-abuse@skynet.be Bytes: 1570 Xref: prodigy.net comp.arch.fpga:132613 X-Received-Date: Tue, 19 Jun 2007 07:41:23 EDT (newsdbm02.news.prodigy.net) Hi Ankit, Ankit wrote: > Hi guys.. > > A few days back I installed xilinx ISE webpack 91i on fedora core 6 > everything worked out fine but i have not been able to simulate the > testbench using the simulator provided by xilinx..whenever i double > click on simulate behavioral model nothing happens..guys do help me > out i am in a fix.. I've had troubles using the ISE simulator as well under a "non-supported" Linux distribution. As only the GUI components seem to behave badly, I ressorted to writing a bash script to start run a simulation and display the results in the standalone isimwave tool. I can elaborate on that and post the script if anyone is interested. Best regards, Laurent Pinchart From laurent.pinchart@skynet.be Tue Jun 19 04:43:18 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!wns14feed!worldnet.att.net!208.48.142.85!newsfeed.news2me.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-Id: <4677c156$0$13852$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: Enumerated type simulation issue (ISE simulator, 9.1.03i) Newsgroups: comp.arch.fpga Date: Tue, 19 Jun 2007 13:43:18 +0200 References: <4676844b$0$13861$ba620e4c@news.skynet.be> <1182193115.765057.44380@q75g2000hsh.googlegroups.com> <1182198964.522933.240550@q69g2000hsb.googlegroups.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 82 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 48830bda.news.skynet.be X-Trace: 1182253398 news.skynet.be 13852 194.78.198.49:58886 X-Complaints-To: usenet-abuse@skynet.be Xref: prodigy.net comp.arch.fpga:132614 X-Received-Date: Tue, 19 Jun 2007 07:43:19 EDT (newsdbm02.news.prodigy.net) Hi Duth, Duth wrote: > On Jun 18, 12:58 pm, Duth <premd...@gmail.com> wrote: >> On Jun 18, 7:10 am, Laurent Pinchart <laurent.pinch...@skynet.be> >> wrote: >> >> >> >> > Hi everybody, >> >> > I'm having trouble simulating a state machine withISEsimulator(ISE >> > 9.1.03i on Linux). At this point I'm not sure if the issue is in >> > thesimulatoritself or in the waveform viewer (isimwave). >> >> > The following signal type isn't displayed correctly in isimwave : >> >> > type cmd_state_t is ( >> > STATE_IDLE, >> > STATE_START, >> > STATE_INDEX, >> > STATE_ARGUMENT, >> > STATE_CRC, >> > STATE_STOP, >> > STATE_WAIT, >> > STATE_RINDEX, >> > STATE_RARGUMENT, >> > STATE_RCRC >> > ); >> >> > signal cmd_state : cmd_state_t; >> >> > The process transitions from STATE_RINDEX to STATE_RARGUMENT, and then >> > to STATE_RCRC. The waveform viewer shows a transition from STATE_RINDEX >> > to STATE_IDLE, and then to STATE_START. As STATE_RARGUMENT and >> > STATE_RCRC are the 9th and 10th states, I suspect thesimulatoror the >> > wave viewer (probably the later) to use the 3 least significant bits >> > only. >> >> > When replacing the enumerated type with an integer, isimwave displays >> > the correct values : >> >> > constant STATE_IDLE : integer := 0; >> > constant STATE_START : integer := 1; >> > constant STATE_INDEX : integer := 2; >> > constant STATE_ARGUMENT : integer := 3; >> > constant STATE_CRC : integer := 4; >> > constant STATE_STOP : integer := 5; >> > constant STATE_WAIT : integer := 6; >> > constant STATE_RINDEX : integer := 7; >> > constant STATE_RARGUMENT : integer := 8; >> > constant STATE_RCRC : integer := 9; >> >> > signal cmd_state : integer; >> >> > Has anyone run into the same problem ? Is there any workaround other >> > than switching to a non-enumerated type ? Any patch available ? >> >> > Best regards, >> >> > Laurent Pinchart >> >> HI Laurent, >> >> Please open a case with Xilinx Support on this issue. I think this >> might be fixed in 9.2i, that will be coming out soon, although we >> would need to have the testcase in house to confim. >> >> Thanks >> Duth > > Hi Laurent, > > This issue should be fixed in ISE 9.2i SP1. That will be released at > the end of this month. Thanks for your help. Best regards, Laurent PinchartArticle: 120860
I got into FPGA design by filling a need a company had while doing board design. Thats typical unless the company specifically targets junior engineers. Good luck.Article: 120861
If I download ddr_sdr core from Opencore, how could I use it with PowerPC or Microblaze to access memory with C code. Is it enough to load this core in c:\EDK\hw\XilinxProcessorIPLib\pcores? But I need to create mpd and pao files. Must I implement C functions to access to it or it is enough to create a pointer to the memory direction?Article: 120862
On 19 Jun., 14:19, Pablo <pbantu...@gmail.com> wrote: > If I download ddr_sdr core from Opencore, how could I use it with > PowerPC or Microblaze to access memory with C code. Is it enough to > load this core in c:\EDK\hw\XilinxProcessorIPLib\pcores? But I need to > create mpd and pao files. > > Must I implement C functions to access to it or it is enough to create > a pointer to the memory direction? there are things you can do, and thing you should not. "using opencores DDR with EDK" is something you should not do. AnttiArticle: 120863
I've just been debugging mine (XCV2) ... In principle this is what I do: A decrease phase until memory errors occur B increase phase until no errors, note phase (min value) C increase by a number of steps (i used 10) to get out of the edge region D increase phase until memory errors occur, note phase (max value) E set the phase to mid value. All this assumes that I start of in the data eye, or below it. My problems so far were: C is needed, i.e. when leaving the unstable region you really need to take a safe step away from the edge. Secondly I discovered that dcm_status(0) i.e. ps overflow became set when scanning the phase upwards. So I changed "memory errors" to "memory errors OR dcm_status(0)". An early misstake I did was to assume PSDONE staying high, in reality (also stated in the manual) it just pulses for one cycle. Hppe this helps, good luck /PontusArticle: 120864
On Jun 18, 9:27 pm, Maverick <> wrote: > I have a Xilinx design that uses mainly verilog RTL and some .xco file for coregen FIFOs and such. I am using vcs compiler from synopsys. This compiler does not recgonize the xco files. Is there any way I can convert .xco file into verilog file using Xilinx coregen? > > I do not know why this shareware design does not provide the verilog file for coregen fifo and instead it has the .xco file. Is there any advantage in doing so? > > It will be great if I can convert the .xco file into .v for vcs verilog simulation. vcs compiler is able to compile the xilinx primitves .v files provided by Xilinx. > > Thanks for your help. > > Maverick Coregen actually creates a verilog file for simulation. This file does not contain synthesizable code, however. If you only need the verilog for simulation, Coregen should be enough. If you want synthesizable verilog, you'll need to write your own or find another solution. HTH, GaborArticle: 120865
Hi everyone, Could someone with experience or simulation tools provide information on the hardware requirements to interconnect Virtex2pro and Virtex4 with rocketio at 2.5Gb/s. The simpler the better, DC if possible and if not AC. I'd like to know the termination voltages and anything needed on the lines. v2pro<=>v2pro and V4<=>V4 works. I can't get the proper setup to run a bert test V4 to v2pro (v2pro to V4 is easier) so if you have a working setup I'd be glad if you could describe it. Thanks, Best regards, Jeremie PS: If someone feels like describing his V5 setup I'm sure that will be useful for many people.Article: 120866
On Jun 18, 7:48 am, Antti <Antti.Luk...@googlemail.com> wrote: > Antti is still hoping to see how amontec FS device works faster then > HS USB from Xilinx Amontec is claiming "7.9Mbits bit stream) at 2.8 seconds" which works out to 2.82 Mbit/second, well less than the data transfer capability of usb full speed (some 12 mbit/s if I recall correctly). Do you have evidence that xilinx is actually running faster, instead of merely using a usb chip that is theoretically capable of going much faster than it's actually being used in their product?Article: 120867
On 19 Jun., 16:00, cs_post...@hotmail.com wrote: > On Jun 18, 7:48 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > Antti is still hoping to see how amontec FS device works faster then > > HS USB from Xilinx > > Amontec is claiming "7.9Mbits bit stream) at 2.8 seconds" which works > out to 2.82 Mbit/second, well less than the data transfer capability > of usb full speed (some 12 mbit/s if I recall correctly). > > Do you have evidence that xilinx is actually running faster, instead > of merely using a usb chip that is theoretically capable of going much > faster than it's actually being used in their product? so far nobody can actually compare the 2 cables under same condictions because Amontec promised their "2.8 second howto" to be available "next monday" what would be yesterday, and as of the moment of writing Amontec website still has no actual updated info about this claimed "speed improvment" :( if/when Amontec fullfills their promise then it will be possible to compare the speeds AnttiArticle: 120868
On Jun 19, 11:27 am, Ankit <ankitanand1...@gmail.com> wrote: > Hey Duth.. > > Hi..Thanx for taking time and replying to my query..I > have been trying to run the command you mentioned in your posts but > this what it says.. > > [ankit@localhost Xilinx91i]$ mv $XILINX/gnu/gcc/3.2.3/lin/bin/ld > $XILINX/gnu/gcc/3.2.3/lin/bin/ > mv: cannot stat `/gnu/gcc/3.2.3/lin/bin/ld': No such file or directory It seems like your $XILINX variable is not set. It should point to directory where your Xilinx software is installed. So the $XILINX variable expands to something empty and you end up with the path /gnu/ gcc... and mv does not find ld. You can check the (any) variable with the command 'echo $XILINX'. Try 'echo $PATH', it should print you out the search path for executable applications. To set it in a bash shell use the command 'export XILINX=<path-to-ise> A second problem in your command seems to be that you forgot the ld.old for the second parameter of the mv command. Check out 'man mv' in your shell and it will tell you what it is doing. Cheers, GuenterArticle: 120869
Hi all, just for curiousity anyone knows if Actel is working on some tools to include SystemC synthesis in the future for their Libero IDE? This would be a great advantage for some of their developers since most of the are working on System Level at the moment. Kind regards, Vince http://mobile.skynetblogs.beArticle: 120870
On Jun 19, 9:15 am, Antti <Antti.Luk...@googlemail.com> wrote: > > Do you have evidence that xilinx is actually running faster, instead > > of merely using a usb chip that is theoretically capable of going much > > faster than it's actually being used in their product? > > so far nobody can actually compare the 2 cables under same condictions > because > Amontec promised their "2.8 second howto" to be available "next > monday" what > would be yesterday Yes, that's odd, but doesn't bar us from begining a comparison. How fast have you documented the Xilinx cable going?Article: 120871
On 19 Jun., 16:45, cs_post...@hotmail.com wrote: > On Jun 19, 9:15 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > Do you have evidence that xilinx is actually running faster, instead > > > of merely using a usb chip that is theoretically capable of going much > > > faster than it's actually being used in their product? > > > so far nobody can actually compare the 2 cables under same condictions > > because > > Amontec promised their "2.8 second howto" to be available "next > > monday" what > > would be yesterday > > Yes, that's odd, but doesn't bar us from begining a comparison. > > How fast have you documented the Xilinx cable going? yes that ODD and yes it does prevent comparison, actually ;) the USB performance can be influenced by many things, it could be that amontec used FS only hub or root port as example, well, lets wait up the "2.8 second howto" .. AnttiArticle: 120872
On Jun 19, 9:56 am, Antti <Antti.Luk...@googlemail.com> wrote: > > Yes, that's odd, but doesn't bar us from begining a comparison. > > > How fast have you documented the Xilinx cable going? > > yes that ODD > > and yes it does prevent comparison, actually ;) > the USB performance can be influenced by many things, > it could be that amontec used FS only hub or root port as example, So how fast have _you_ gotten the xilinx cable to go? You seem to be having more fun laughing at Larry's calendar challenges than actually seeking to compare performance. The Amontec claimed performance, while yet unverified, doesn't seem unreasble to me, so I'm really curious if you have evidence that the xilinx cable is working faster than that for you?Article: 120873
On 19 Jun., 17:00, cs_post...@hotmail.com wrote: > On Jun 19, 9:56 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > Yes, that's odd, but doesn't bar us from begining a comparison. > > > > How fast have you documented the Xilinx cable going? > > > yes that ODD > > > and yes it does prevent comparison, actually ;) > > the USB performance can be influenced by many things, > > it could be that amontec used FS only hub or root port as example, > > So how fast have _you_ gotten the xilinx cable to go? > > You seem to be having more fun laughing at Larry's calendar challenges > than actually seeking to compare performance. > > The Amontec claimed performance, while yet unverified, doesn't seem > unreasble to me, so I'm really curious if you have evidence that the > xilinx cable is working faster than that for you? you should have realized that I want answer until I have actually compared the 1 cables in comparable environment. I guess its all Larry's "marketing stuff" to promise things and then not deliver as promised. For me I see now reason or excuse to promise something "next monday" and then just ignore this. It sure is nice marketing, I have checked amontec website every few hours ;) AnttiArticle: 120874
On 19 Jun., 17:00, cs_post...@hotmail.com wrote: > On Jun 19, 9:56 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > Yes, that's odd, but doesn't bar us from begining a comparison. > > > > How fast have you documented the Xilinx cable going? > > > yes that ODD > > > and yes it does prevent comparison, actually ;) > > the USB performance can be influenced by many things, > > it could be that amontec used FS only hub or root port as example, > > So how fast have _you_ gotten the xilinx cable to go? > > You seem to be having more fun laughing at Larry's calendar challenges > than actually seeking to compare performance. > > The Amontec claimed performance, while yet unverified, doesn't seem > unreasble to me, so I'm really curious if you have evidence that the > xilinx cable is working faster than that for you? actually as you have asked the same thing question SO MANY times, here is the answer YES, Xilinx Platform cable WORKS FASTER. example: 11MBit bitstream, REDUCED TCK Clock to 12MHz, time : 2.547 seconds On the test board the JTAG chain clock isnt optimal so I can not test at 24MHz TCK, I assume the speed performance would be noticeable. this doesnt mean that Xilinx software and drivers are good, they are not, many JTAG operations could be carried out faster then do, but eh, this is the same thing as with Actel, they changed to use windriver USB drivers, and as result their programming times increased 2 times. but hardware wise the Xilinx Platform USB cable is defenetly capable to get much better performance then any implementation of FT2232 in plastic box (== Amontec jtagkey, etc..) ever can. FT2232 has limitation on max JTAG clock of 6MHz. Antti
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