Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi all, I am experimenting incremental compilation on a design. But the logiclock region assignments are ignored and it doesn't seem to save the compilation time on the second compile. In the first compile I set the netlist type of design partitions to post-sysnthesis, then when it's done I changed it to post-fit and start the second compilation. I wonder which one of the following could be the reason? Or it's something else? 1. I set the logiclock region size as auto and the origin as floating. 2. I used maximum routing and physical thesize effort for timing. Are there any settings that may force the compiler recompile anything? 3. Setting the netlist type to post-fit and set the fitter preservation level to placement will only take effect on the third compilation and later? The second compilation do not preserve anything because the first compilation did not got the information it needs for preservation.... Thanks in advance HuaArticle: 132376
On May 24, 12:54 am, Rob Gaddi <rga...@technologyhighland.com> wrote: > water9...@yahoo.com wrote: > > The unidirection DMA read only or write only of my PCIE NIC controller > > V5-based works fine . > > > However,if DMA read(from host--->ethernet port) is > > progress ,additional i send ping packet continuing from Host or > > client.the NIC will doesn't work.the send/receive is stoppped. > > > But,if DMA write(from ethernet --->host) is progress,additional i send > > ping packet continuing from Host or client. it still works fine. > > > who can provide any clue to debug the issue? > > Probably someone with any information whatsoever about what hardware > you're using, how it's wired up, what tools you're trying to implement > this with, or what cores you're trying to work with. But who that would > be is anyone's guess. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order devleopment board:Xilinx ML555,ISE10.1.1 .i don't use any IP core except for Xilinx PCIE GTP and ethernet PCS/PMA. the river for lnx is ok.Article: 132377
"Symon" <symon_brewer@hotmail.com> wrote in message news:g16680$2fn$1@aioe.org... > "uche" <uraniumore235@hotmail.com> wrote in message > news:2530908c-024f-4c71-9f1d-5d7daa3a2d96@i36g2000prf.googlegroups.com... >>I need some help with this one... >> >> Illegal LOC on IPAD symbol "CLK" or BUFGP symbol "CLK_BUFGP" >> (output signal=DONE_OBUF), IPAD-IBUFG should only be LOCed to >> GCLKIOB site. >> >> What does that mean ? >> >> Thanks > > STFW > http://www.google.com/search?q=Illegal+LOC+on+IPAD+symbol Sorry, I meant STW. Regards, Syms.Article: 132378
I intend to build an fpga programer for the spartan fpgas of xilinx I am not sure about the file that i should send over the jtag to program the fpga. I got conflicting information from 2 different forums. Someone told me that i could either use the .bit or the .bin file. According to him i just had to send one of these files to the jtag programer. Someone else told me that i would have to generate either a .svf or a .xsvf file from the .bit file using iMPACT. According to him i should be specifying the devices in the jtag chain in iMPACT for generating the correct .svf file.Article: 132379
Dear all,
I need to transfer a live video stream from FPGA to let say a
PC(Linux) ,
may you tell the design complexity or how to approach this problem,
I have searched a lot and not finding proper way to do this,
so Please guide in in following points,
1) I am using video starter kit, ML402, Do anybody provide way to
capture frames on DDR memory. Then i will process my frames DDR
memory
2) after my frames on DDR memory , I want to compress (encode) them
with MPEG (or you suggest) -- is there any IP available to do this.
it means i will be getting a compressed mpeg 4 files at this stage,
3) I want to use xaap915 "streaming an MP3 files using RTP" to
streaming a this video file, so,my at thsi stage my live video will be
seen at PC connected to cross cable,
4) As i want to streaming over bluetooth and streaming over IP is
possible in bluetooth stack, streaming over IP over bluetooth can use
LAP profile, so at this stage i want to have a bluetooth stack on
ML402 board. I have bleutooth kit which has layer upto HCI, so I need
to have a upper layer stack for bluetooth on mircoblaze, now I found
lwBT , light weight bluetooth stack. lwBT was created to transport IP
data from lwIP over Bluetooth. EDK support lwIP only. SO at this stage
I need to port lwBT library on microblaze architecture. How i can do
this.
5) at this stage i will be getting RTP packet via bluetooth but how to
receive on another Linux PC. if it was direct internet connection then
it is just writing a url in browser or player. but here IP data is
transferred over bluetoth. Do i need to write any code with blueZ
library or just commands will take care of everything.
This is my final project , I want to work hard , rather then making
some work around to problem, I do not have proper guidance, hope i
will get here,.
May be my whole steps and approaches are wrong,
Best Regards
Narendra Sisodiya
Article: 132380Mike Lewis wrote: (snip) >>The traditional method for ASIC is to divide the number >>of transistors by the number of transistors in a 2 input >>NAND gate. For CMOS, that is four. (snip) > What is your method for determining how many transistors are in the design? > My synthesis tools only give me area. Last I knew, they gave transistors, but that was some time ago. For FPGA it is much harder to give a reliable count, and you are asking in an FPGA newsgroup. If it gives gate counts different types of gates and with a little guessing on transistors/gate. Is this for standard cell, sea of gates, or something else? I thought I used to have pretty detailed information on the standard cell libraries, including transistors for each library element. -- glenArticle: 132381
Hi all , Out product uses the FSL bus to talk to a co-processor. So far I has the I and d cache for microblaze disabled and the FSL bus was working fine. But as soon as I enable I and d cache I start getting invalid reads on FSL Bus. Is there something I am missing out on? BR RateArticle: 132382
Hi, > My guess would be that you have a timing error. That *could* be. > Does your design meet > timing? I have to dig into that on Monday.... > Do you have a timing specification? Nope. I am using the EDK generated .ngc netlists and the EDK generated .ucf file. My design (it's connected via external memory controller) doesn't have critical timing and the synthesis estimate says 140Mhz.... So I didn't care for timing... But what could I do if the EDK design does not meet timing specs? > Are you running from external memory? Yes. DDR > Can you run a memory test on > it? Hm... I have tried the memory test demo application once. Perhaps I have to try it again.... Best regards, Philipp :-)Article: 132383
On May 23, 6:20 am, Philipp Hachtmann <hac...@hachti.de> wrote: > Hi folks, > > I am short before going mad... > > I have a Xilinx ML403 board with a Virtex 4 FX12 FPGA sitting on my desk. > > I use an EDK generated PPC405 design as a submodule. > > My current task is to interface with a simple IIC chip via the Xilinx > IIC core. That works - from time to time. > My software behaves completely strange - hangs, seems to skip parts, > runs into Xilinx' assertion stop code, etc... > > I use the following libs and drivers: > Xilinx intc, iic, uartlite, xil_printf > libc's printf > > I tried to dig into the problem using the Xilinx supplied XMD debugger. > It looks like I am suffering from "side effects": I have seen data going > corrupt (function pointers NULLing) while execution is somewhere else. > I have also seen program exception and machine check exeptions in the > PPC's ESR register :-( > Behavior changes with position of code in memory. Sometimes an inserted > or removed operation completely changes the behaviour... > > So the question is: Does anyone have similar experiences? Is there any > known corrupt driver code in the last EDK revision? > Am I doing something badly wrong? > > If you have some ideas, PLEASE let me know... I can provide more details > on request. > > Thanks a lot, > > Philipp :-) > > -- > You have to reboot your computer after powerfail? Haha!http://h316.hachti.de Hello Philipp, Are you using an operating system, or are you running stand alone code? Your symptoms sound like they could be caused by a stack that is not big enough. If you are using an OS that supports virtual memory, the stack and heap sizes for each process are dealt with for you automatically. If not, than you need to pay some attention to make sure that their default values will work for your program. printf can take a lot of memory resources, and every time you move printfs around to try and debug, the symptoms can change. If you are running stand alone code, check what the stack and heap sizes are set to in EDK. In the Applications tab in the Project Information Area window, select your program, right click, then select Generate Linker Script. That will pop up a window that list the stack and heap sizes and other stuff. The default is 0x400 bytes, or 1k byte. That is big enough for our boot loader that loads Linux from a MiniSD card, and does some stuff with SPI roms. It uses xil_printf, but not libc printf. Try increasing the stack and or heap sizes and see if that makes a difference.c Regards, John McCaskill www.FasterTechnology.com/products.htmlArticle: 132384
Can someone confirm the SDIO CRC7 bits input for the 48 bits command and response and 136 response. For case 1 and 2 the CRC7 is calculated on 40 bits starting from the very first bit - the start bit. For case 3 the first two bits (start and transmission bits) and the six reserved ones, which follow, are skipped. Than 120 bits are fed to the CRC7 module. The issue explained in detail at http://bknpk.no-ip.biz/SDIO/CRC7_cmd_rsp_input_bits.html http://bknpk.no-ip.biz/SDIO/CRC7.htmlArticle: 132385
On May 20, 11:26 am, austin <aus...@xilinx.com> wrote:
> Joseph,
>
> Why bother? Only because all of the 'other' solutions actually exist,
> where H4 is a hyper-active sales pitch for an untested capability that
> hasn't even been taped out yet...
>
> Imagine all those Altera customers who designed in the Stratix III GX:
> all dressed up, and nowhere to go.
>
> Using FPGAs is all about reducing risk. Converting the FPGA to an ASIC
> (structured or otherwise) is all about reducing costs.
>
> No risk: Virtex 5, today, available
>
> Lower Cost: Virtex 5 EasyPath(tm) devices, guaranteed to work, because
> they are IDENTICAL to the FPGA
>
> Austin
ALTERA
XILIXNX
QUARTUS - incremental compile ISE - NO
incremental compile
-
Windows - Linux (for
large chip, 16G of memory)
- Fast compile times -
Very long times (sometimes no fit unknown)
- SOPC - ok to use -
EDK - very hard to use
- NIOS - very easy
- Microblaze - not easy
Engineers get reviewed on progress not one A vs. X
I still don't understand how many questions are posted about X here.
I use can use both. I like The A Company model. I don't agree that X
marketing people have to do damage control here.
Article: 132386Toolset: ISE/ModelSim_PE/VHDL I've been asked to modify one of my designs for another application so decided it was time to parameterize it as much of it as possible. I ran into a roadblock changing configuration of CoreGen devices, so was simply going to force the eventual user to go through the GUI for any modifications. Then I RTFM. ;-) In the Comparator V9.0 Product Specification there an example of direct instantiation (Page 7), which looks like it'll save me a lot of headaches. I can simply use the generics I already have to manipulate the core. My problem is that ISE doesn't find the comparator in the library. I've had the problem (with ModelSim) where the libraries change and I'm pointing to an old copy but I don't know where to tell ISE where the libraries are. I've always used the GUI to generate cores before, but I really like the idea of direct instantiation. I can make my designs far more flexible without a whole lot of work. Anyone with a cluestick? -- KeithArticle: 132387
Hi,
I have encountered a strange problem. Because an adder is called many
times by different width functions, I program one, see bottom, it
supports sign extension according to input width. One routine calls
the adder fine, but it cannot be called by two times. That is the
upper caller use RLOC or not, the following MAP error exists (it is
only one of the many similars). From the error message, I still cannot
understand the reason. It seems should be fine, because a slice does
have two LUT and two CYs. What's the problem? Any suggestion is highly
appreciated.
Section 1 - Errors
------------------
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=hset,
RLOC=X4Y1)
which require the combination of the following symbols into a
single SLICE
component:
LUT symbol "fir_0a/ADDER_3/INST_ADD[1].au_lut" (Output Signal =
fir_0a/ADDER_3/lut_out<1>)
MUXCY symbol "fir_0a/ADDER_3/INST_ADD[1].au_mux" (Output Signal =
fir_0a/ADDER_3/carry<2>)
XORCY symbol "fir_0a/ADDER_3/INST_ADD[1].au_xor" (Output Signal =
fir_0a/MACC_adder_a2<1>)
LUT symbol "fir_0a/ADDER_3/INST_ADD[2].au_lut" (Output Signal =
fir_0a/ADDER_3/lut_out<2>)
MUXCY symbol "fir_0a/ADDER_3/INST_ADD[2].au_mux" (Output Signal =
fir_0a/ADDER_3/carry<3>)
XORCY symbol "fir_0a/ADDER_3/INST_ADD[2].au_xor" (Output Signal =
fir_0a/MACC_adder_a2<2>)
The XORCY symbol fir_0a/ADDER_3/INST_ADD[1].au_xor can't be placed
in the
XORG site because the DI signal doesn't match the output signal of
the
function generator. Please correct the design constraints
accordingly.
...
loop_for0: for i in 0 to WIDTH-WIDTH0-1 generate
array_preceding0(i) <= in_adder0(WIDTH0-1);
end generate;
in_adder0_ex <= array_preceding0 & in_adder0;
loop_for1: for i in 0 to WIDTH-WIDTH1-1 generate
array_preceding1(i) <= in_adder1(WIDTH1-1);
end generate;
in_adder1_ex <= array_preceding1 & in_adder1;
carry(0) <= '0';
INST_ADD : for i in WIDTH-1 downto 0 generate
type bel_lut_type is array (0 to 1) of string (1 to 1);
type bel_xor_type is array (0 to 1) of string (1 to 4);
constant bel_lut:bel_lut_type:= ("F","G");
constant bel_xor:bel_xor_type:= ("XORF","XORG");
--The MUXCY's don't need it because the position is inferred by the
connectivity.
attribute BEL of au_lut : label is bel_lut(i mod 2);
-- attribute BEL of au_mux : label is bel_lut(i mod 2);
attribute BEL of au_xor : label is bel_xor(i mod 2);
attribute RLOC of au_lut : label is "X0" & "Y" &
integer'image(lloc(WIDTH-1-i));
attribute RLOC of au_mux : label is "X0" & "Y" &
integer'image(lloc(WIDTH-1-i));
attribute RLOC of au_xor : label is "X0" & "Y" &
integer'image(lloc(WIDTH-1-i));
attribute INIT of au_lut : label is "6";
begin
au_lut : LUT2
--pragma translate_off
--I0 in_adder0 0 1 0 1 | 0 1 0 1
--I1 in_adder1 0 0 1 1 | 0 0 1 1
--O 0 1 1 0 | 0 1 1 0
--Index 0 1 2 3 4 5 6 7
generic map (INIT => X"6")
--pragma translate_on
port map (
I0 => in_adder0_ex(i),
I1 => in_adder1_ex(i),
O => lut_out(i));
au_mux : MUXCY
port map (
DI => in_adder1_ex(i),
CI => carry(i),
S => lut_out(i),
O => carry(i+1));
au_xor : XORCY
port map (
LI => lut_out(i),
CI => carry(i),
O => out_adder(i));
end generate;
Article: 132388Im a beginer in VHDL and i got some problems regarding Ethernet usage on XST 3.0 Board. I want to send audio trought ethernet to a second XST 3.0 but i have a lot of problems regarding Ethernet interface initialization - I'm not able to sent anything. I will meke some package processing later on but now I cannot even send one frame. Maybe you got some examples of ethernet intercace usage for Xess XST 3.0 ? Kind Regards Scutum612Article: 132389
Hi, Im getting the following error when trying to run the ML505 Standard IP Core Demo project from Xilinx. Im trying with the project that Xilinx gave me,without any modifications. <error starts here> INTERNAL_ERROR:Pack:pktbaplacepacker.c:897:1.139.4.6 - Unable to obey placement request which requires the combination of the following comp blocks into the SLICE_X39Y78 site. comp: mb_plb/N4 comp: mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/ arbctrl_sm_cs_FSM_FFd6 The fragment blocks involved are as follows: LUT symbol "mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/ arbctrl_sm_cs_FSM_FFd6-In_SW0" (Output Signal = mb_plb/N4) FMux symbol "mb_plb/mb_plb/ GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd6- In" (Output Signal = mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/ I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd6-In) FLOP symbol "mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/ arbctrl_sm_cs_FSM_FFd6" (Output Signal = mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/ arbctrl_sm_cs_FSM_FFd6) The top reasons for failure were: -> A legal placement was never found for LUT symbol "mb_plb/mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/ arbctrl_sm_cs_FSM_FFd6-In_SW0". Final packing quit early. </error> The error is solved when I turn on Xplorer script, though the run time goes through the roof. How can I get the issue resolved? Raghu.Article: 132390
On May 24, 3:37 pm, turkey_b...@yahoo.com wrote:
> On May 20, 11:26 am, austin <aus...@xilinx.com> wrote:
>
>
>
> > Joseph,
>
> > Why bother? Only because all of the 'other' solutions actually exist,
> > where H4 is a hyper-active sales pitch for an untested capability that
> > hasn't even been taped out yet...
>
> > Imagine all those Altera customers who designed in the Stratix III GX:
> > all dressed up, and nowhere to go.
>
> > Using FPGAs is all about reducing risk. Converting the FPGA to an ASIC
> > (structured or otherwise) is all about reducing costs.
>
> > No risk: Virtex 5, today, available
>
> > Lower Cost: Virtex 5 EasyPath(tm) devices, guaranteed to work, because
> > they are IDENTICAL to the FPGA
>
> > Austin
>
> ALTERA
> XILIXNX
> QUARTUS - incremental compile ISE - NO
> incremental compile
> -
> Windows - Linux (for
> large chip, 16G of memory)
> - Fast compile times -
> Very long times (sometimes no fit unknown)
> - SOPC - ok to use -
> EDK - very hard to use
> - NIOS - very easy
> - Microblaze - not easy
>
> Engineers get reviewed on progress not one A vs. X
> I still don't understand how many questions are posted about X here.
> I use can use both. I like The A Company model. I don't agree that X
> marketing people have to do damage control here.
Sorry for the garble! the upload messed it up.
XILIXNX
- ISE - NO incremental compile (2 method one from XILINX &
Synplicity)
(UCF's constraints not supported in Synplicity for incremental
compile)
- Linux for large chip, 16GB of memory required, Windows only
supports 4GB
- Very long times (sometimes no fit unknown, FAE's puzzled)
- EDK - very hard to use
- Microblaze - not easy
- EasyPath - chips that failed full MFG tests. Oh yea I'll put a
design in that has reliability requirement.
ALTERA
- QUARTUS - incremental design (it works)
- works on all families in WINDOWS
- Compile times are ok!
- SOPC, can use
- NIOS use a lot (software engineers can plan reliable specification)
- HARDCOPY - great for large chips & reduce cost where high chip
count is in product.
I could go!
Engineer's get reviewed on progress not one A vs. X
I still don't understand how many questions are posted here about X
here.
Why not make X tools obvious and watch the questions go down in
this newsgroup!
I use can use both. I like the Lattice CPLD's with PLL's & LVDS. I
like the ACTEL also!
I like The A Company model.
I put the time into the design not making the design work through
the tool.
I watch the X FAE's struggle to resolve design issues in their
tool. I could go on here about MGT & aurora using a VIRTEX2PRO and it
worked on older versions of ISE and fails on a new version. Of course
I had to use a newer version of ISE and Synplicity. (One of the tools
was ripping something out)
I don't agree that X marketing people have to do damage control here.
Why put the effort into making ISE a repeatable tool (for the same
design on re-compile)!
I normally don't post! But I read this newsgroup to head off bugs. I
lost control!
Article: 132391Please help meArticle: 132392
Thank you XILINX, you list new device package options for Spartan3E: (VQ100 for XC3S500E) http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf and for Spartan3A: (new VQ100 and FT256 options) http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf In the datasheets overview there is a table with device package options and their respective amount of I/O's and inputs only. E.g. the new XC3S200A-4VQG100C has 68 I/O's with 13 input onlies. These numbers do not match with the pinout tables in the datasheets, and ISE 10.1 behaviour. ISE 10 lets me use 61 I/O's in a quick test design. So there are 61 I/O's on a XC3S200A-4VQG100C and 7 input only signals ? Where is the mistake ? MIKE PS: Delivery time for the XC3S500E-4VQG100 is 26 weeks @ Silica ! -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho ! Kontakt: Tel: 08131 339230 Usst.ID: DE130097310Article: 132393
This almost ticks me off! I have been bugging Xilinx for years to support lower pin count packages on larger parts and I have always gotten that argument that they just can't sell enough to justify it, especially in the Spartan line. I guess there are some larger fish asking for that now. I wonder if they will go to the 100 pin package with the 3AN parts? Rick On May 25, 2:00 pm, "M.Randelzhofer" <techsel...@gmx.de> wrote: > Thank you XILINX, > > you list new device package options for Spartan3E: (VQ100 for XC3S500E)http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf > > and for Spartan3A: (new VQ100 and FT256 options)http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf > > In the datasheets overview there is a table with device package options and > their respective amount of I/O's and inputs only. > > E.g. the new XC3S200A-4VQG100C has 68 I/O's with 13 input onlies. > > These numbers do not match with the pinout tables in the datasheets, and ISE > 10.1 behaviour. > ISE 10 lets me use 61 I/O's in a quick test design. > So there are 61 I/O's on a XC3S200A-4VQG100C and 7 input only signals ? > > Where is the mistake ? > > MIKE > PS: Delivery time for the XC3S500E-4VQG100 is 26 weeks @ Silica ! > > --www.oho-elektronik.de > OHO-Elektronik > Michael Randelzhofer > FPGA und CPLD Mini Module > Klein aber oho ! > Kontakt: > Tel: 08131 339230 > Usst.ID: DE130097310Article: 132394
On May 21, 2:07 am, Peter Alfke <al...@sbcglobal.net> wrote: > On May 20, 10:17 pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote: > > > > > > > > > austin wrote: > > > Joseph, > > > > Imagine all those Altera customers who designed in the Stratix III GX: > > > all dressed up, and nowhere to go. > > > Maybe Altera also shares roadmaps like you do to bigger customers, and > > those designers maybe do not exist... Imagine all those V4FX designers > > who wanted working fast tranceivers. > > > I would say all vendors offer surprises to customers who are using > > leading edge devices. > > > > Lower Cost: Virtex 5 EasyPath(tm) devices, guaranteed to work, because > > > they are IDENTICAL to the FPGA > > > My opinion is that EasyPath is the worst of the two worlds. It has > > limitations in flexibility, and the possibilities with price are > > not that great because it is the same silicon. Better to have either > > the full flexibility which costs or then the lowest possible cost > > with no flexibility. > > > --Kim > > Let's not turn this into a marketing slugfest. > It does not take a genius to figure out why Altera was forced to > embark on such a risky gamble... > "We live in interesting times" > Peter Alfke I would say characterizing Altera's step to be "a risky gamble" *IS* making it a marketing slugfest. I remember when Xilinx was touting that they were one of the first adopters the then bleeding edge process geometery on the Spartan 3. They also indicated that the Spartan line would be the new ground breaker because of the need for lowest prices. So when Xilinx uses the most current technology it is "a bold step" while Altera makes "risky gambles"? I seem to recall that Spartan 3 had many, many issues related to the use of the advanced technology and I don't see where the Spartan line is the ground breaker for today's current technology. I guess that didn't pan out in the end, huh? RickArticle: 132395
Someone please help me out. tell me what file am i to use.Article: 132396
On May 26, 12:43 am, cheri...@gmail.com wrote: > Someone please help me out. > tell me what file am i to use. If you want to use the JTAG port, a .BIT file won't do it. A .BIT file is just the raw bits used to configure the part (plus a short header). This can be sent to the FPGA programming port, but not directly to the JTAG port which has its own protocol. I don't know the details of the correct way to program the JTAG port, but I am pretty sure the .SVF or .XSVF files are the right ones to use although the programming software can likely read any of the valid formats to create the appropriate file for downloading. The easiest way to do this is to copy the hardware and use existing software. If you build a programmer that works the same as the vendor's programmer, then you can use their software. I am pretty sure there is info available on how to build your own. Nose around on the Internet. Or do you want to build your own from scratch and create open source software? Even then, I would use compatible hardware. Why reinvent the wheel or have others get new hardware to work with your software? RickArticle: 132397
On May 26, 10:51=A0am, rickman <gnu...@gmail.com> wrote: > On May 26, 12:43 am, cheri...@gmail.com wrote: > > > Someone please help me out. > > tell me what file am i to use. > > If you want to use the JTAG port, a .BIT file won't do it. =A0A .BIT > file is just the raw bits used to configure the part (plus a short > header). =A0This can be sent to the FPGA programming port, but not > directly to the JTAG port which has its own protocol. =A0I don't know > the details of the correct way to program the JTAG port, but I am > pretty sure the .SVF or .XSVF files are the right ones to use although > the programming software can likely read any of the valid formats to > create the appropriate file for downloading. > > The easiest way to do this is to copy the hardware and use existing > software. =A0If you build a programmer that works the same as the > vendor's programmer, then you can use their software. =A0I am pretty > sure there is info available on how to build your own. Nose around on > the Internet. =A0Or do you want to build your own from scratch and > create open source software? =A0Even then, I would use compatible > hardware. =A0Why reinvent the wheel or have others get new hardware to > work with your software? > > Rick hai, Don't get confuse ....Use the .bit file to generate mcs file(programming file) using IMPACT regards, fazArticle: 132398
fazulu deen <fazulu.vlsi@gmail.com> wrote: > On May 26, 10:51 am, rickman <gnu...@gmail.com> wrote: > > On May 26, 12:43 am, cheri...@gmail.com wrote: > > > > > Someone please help me out. > > > tell me what file am i to use. > > > > If you want to use the JTAG port, a .BIT file won't do it. A .BIT > > file is just the raw bits used to configure the part (plus a short > > header). This can be sent to the FPGA programming port, but not > > directly to the JTAG port which has its own protocol. I don't know > > the details of the correct way to program the JTAG port, but I am > > pretty sure the .SVF or .XSVF files are the right ones to use although > > the programming software can likely read any of the valid formats to > > create the appropriate file for downloading. > > > > The easiest way to do this is to copy the hardware and use existing > > software. If you build a programmer that works the same as the > > vendor's programmer, then you can use their software. I am pretty > > sure there is info available on how to build your own. Nose around on > > the Internet. Or do you want to build your own from scratch and > > create open source software? Even then, I would use compatible > > hardware. Why reinvent the wheel or have others get new hardware to > > work with your software? > > > > Rick > hai, > Don't get confuse ....Use the .bit file to generate mcs > file(programming file) using IMPACT xc3sprog know hoe to handle a bit file to programm XC3S and XCF via a bit file. With some understanding of the 1532 bsdl file delivered with Xilinx ISE installation, a plugin for XC2S shopuld be writable. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 132399
Hello John, > Are you using an operating system, or are you running stand alone > code? I am running standalone code. I am using the Xilinx supplied driver framework to get the CPU up and running etc. > Your symptoms sound like they could be caused by a stack that is not > big enough. > If you are using an OS that supports virtual memory, the > stack and heap sizes for each process are dealt with for you > automatically. No, currently no OS :-) > If not, than you need to pay some attention to make > sure that their default values will work for your program. That's an important hint! > Try increasing the stack and or heap sizes and see if that makes a > difference.c I just tried it - it MAKES a difference! But how can I determine the correct stack size? Stopping the program in the "deepest point", look at the stack pointer, add something for interrupt purposes and use that "counted" value? Which of my data goes to the heap? I don't use dynamic memory allocation (btw do the libxil and friends support a working malloc(), free() etc.?). Many thanks for your tip :-) There is a new EDK problem: I tried to change the PPC cpu speed by changing the cpu clock output frequency of the EDK clock generator. Did that via GUI and by editing MHS file. I can do a "make netlist" without any problems. But then, later, PAR gives me an error mentioning a dcm...clk..something<7> signal that has a constraint but doesn't exist. I tried to find the constraint but I don't know where to look. I also grep'ed through the EDK generated netlists (after running ngc2edif) and did not find that signal. And I don't have a clue where I even could have a constraint file mentioning that signal.... Best wishes, Philipp :-)
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z