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Hi , I am new to fpga and I am writing a program for my xilinx virtex 2 xc2v6000 chip. since my ISE software doesn't contain the device in its properties tab . Hence I am unable to synthesise the project for the device .Kindly suggest ways to resolve this problem . Thanks in advance VijayArticle: 115151
Hi guys, Seems like Altera's DSP Builder has undergo a lot of improvements over the past year or so. Trying to connect with other DSP Builder aficionados and to promote more discussion on DSP Builder in general, I have created a google group altera_dspbuilder. There, we can help each other out with: - DSP Builder designs - DSP Builder how-tos - Understanding Altera's DSP related IP cores - Designs with the Video and Image processing IP suites - Or just to discuss DSP algorithms in general. See you there. Regards, -DCArticle: 115152
Matthias Alles <REMOVEallesCAPITALS@NOeit.SPAMuni-kl.de> writes: > I think doing a full featured 3D-Engine (with texturing, z-buffering, > backface-culling, clipping) in an FPGA would be really nice but also a > LOT of work. Some years ago I coded one on a DSP56001 that is used in > the Atari Falcon030 and even that was quite a lot of work (I think > about 3000 lines of assembler code - gives only a 9KB binary!) > Celoxica used to have a raytracing demo which ran without a frame buffer, calculating pixels on the fly. It displayed a rotating Venus de Milo statue in the middle of a room. The room also rotated and had live video from a camera feed mapped onto it. As I recall, the statue was reflective as well. This was years ago, it ran on (IIRC) a spartan II(E?) of about 400k marketing-gates... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 115153
On Jan 31, 9:48 am, "Dennis Yurichev" <Dennis.Yuric...@gmail.com> wrote: > Hi. > Just interesting, does anybody used FPGA to produce real-time graphics > effects, in the spirit of demoscene?http://en.wikipedia.org/w/index.php?title=Demo_%28computer_programmin... Hi Dennis, I've given it some though and I think there is a great potienial to start with a basic spec. card (3-bit VGA + so called Space Invaders Sound) and from there construct Demos for different max sizes for FPGA's. I've been fooling around with basic tests with virtual-colors (4096+ colors on-screen out of 3-bit VGA), FPGA-synths and simple vector- engine and from there everything is possible. It would be nice if it was possible to choose a specific card (my suggestion of it is Xilinx Spartan-3 Starter Kit possibly 200 and 100K variants) but maybe it is possible to make it even wider. Maybe different classes with different MAX Slices/BRAM or something like that! It would be interesting to hear how many people that would be interested in this? Count me in! I'm just a newbie but it would be great to see what others could do! Another very interesing subject would be FPGA-MAME! Somebody had the same thoughs? Already there are versions with PacMan, Space Invaders, Donkey Kong, Pengo and others. just think of the possiblities with Partial Reconfiguration of that was more every-mans business. Today it seem very resource-expensive and hard to do. But maybe the recent updates in ISE 9.1 with Partitions could be used to make Partial Reconfiguration more "open". Or maybe a FPGA-MESS would be even more interesing! Well what do think? /MagnusArticle: 115154
On Jan 31, 12:48 am, "Dennis Yurichev" <Dennis.Yuric...@gmail.com> wrote: > Hi. > Just interesting, does anybody used FPGA to produce real-time graphics > effects, in the spirit of demoscene?http://en.wikipedia.org/w/index.php?title=Demo_%28computer_programmin... While I have not personally done it, I have seen it done on an Altera FPGA. I think I saw a demo that was able to combine the alpha blending mixer megacore (from the VIP suite) with a controller in NIOS to create real time graphics effect.Article: 115155
>It looks like the PC is going to be the real bottleneck in the whole >setup. So assuming a maximum data rate of around 240 Mbits/sec, whats >the best way to interface the PC data stream with the SMA interface. >This is what came to my mind. Cypress FX2 board takes in a data stream >from the PC, and the slave fifo interface sends the data to the FPGA. >The FPGA takes in the data and sends it out through the SMA MGTs. Is >this reasonable? Any pointers on working with FX2-FPGA board setups. >Can a Xilinx ML321 board be used? >As far as requirements: > * Throughout: Maximum possible data rate > * Latency: Would like it to be small, but not critical > * Ease of use: Somewhat important, but not the driving factor > * Ubiquity: Again somewhat important, b/c we would like to >communicate between PC-PC or PC-Smartphone using a USB port. If you can be without USB, why not try 1 Gbps Ethernet or Firewire1394 ..? From fred@n0spam.com Thu Feb 01 04:04:58 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!news.astraweb.com!border2.newsrouter.astraweb.com!transit3.readnews.com!news-out.readnews.com!newspeer1.nwr.nac.net!solnet.ch!solnet.ch!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!iris.uk.clara.net From: "Fred" <fred@n0spam.com> Newsgroups: comp.arch.fpga Subject: PCI Express user group Date: Thu, 1 Feb 2007 12:04:58 -0000 Lines: 13 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 23e6520630c0173a623920d83632100028d7002017e4332ae336102045c1dc13 NNTP-Posting-Date: Thu, 01 Feb 2007 12:24:51 +0000 Message-Id: <1170332691.17553.0@iris.uk.clara.net> Xref: prodigy.net comp.arch.fpga:126557 I know there is a PCI-Express newsgroup but there are very few posts of any relevance to PCI Express itself. Is there another newsgroup more dedicated to the workings of PCI Express? I have the following question: What happens when a mal formed packet is received? The transmitter CC will be incremented but the CL (which is the CA received from the receiver) will not be incremented such that the apparent size of the available space in the receive buffer will decrease with no mechanism to correct itself. Am I correct?Article: 115156
> No, master, sorry, master. What is your next request??? As per usual in this news group when people don't get their way they become cinical. > > -- > Ben Jackson AD7GD > <ben@ben.com> > http://www.ben.com/Article: 115157
> Maybe English is not your native language: > The little word "and" at the beginning of the sentence changes a > slightly pestering question to an obnoxious statement. > If you are as ignorant in this technology as you seem to be, it would > be wise to be more polite. You want me to be polite, going by this answer. My first language is none of your business, this remark could qualify you as something, I won't say to save you the embarassment. > Any answer you get here from anybody is because we want to be helpful. > Keep that in mind! > Peter Alfke > > On Jan 31, 4:52 pm, <carshie> wrote: > > and where did you get the 10C from, did I say I have 10C ? > >Article: 115158
Hello, I have a Spartan 3E and I have implemented a Xilkernel and pthread for threading. Now I want to use "condition variable" (pthread_cond_init, pthread_cond_wait,...) and I think that this is not possible in EDK. Is this true??. How can I use condition variable in FPGA??. Has anyone tried to do this?? Thanks for your help.Article: 115159
carshie wrote: > > You want me to be polite, going by this answer. > My first language is none of your business, this > remark could qualify you as something, I won't say to save > you the embarassment. > Just FYI: it qualifies him as someone whose first language wasn't English, making him particularly sensitive to the issues faced by those who try to communicate on this board with an excellent written word but who miss the more subtle meanings in these newsgroup communications and in technical documentation.Article: 115160
This group is filled with much expertise and most participants are MORE than willing to help in anyway they can. I've seen them give students answers to their homework, and give engineers help with debugging and overcoming design hurdles. The only thing any of the aforementioned SME's expect is that those posting questions would be polite, truthful, and professional. There's a wealth of knowledge on this board that is made available to anyone earnestly seeking answers. There's an old proverb which says that "a wise man will hear, and will increase learning, and a man of understanding shall attain unto wise counsels". You've done properly by contacting this group (wise counsel), but unless you are willing to HEAR and listen to that wisdom you're nothing more than a fool. Here's a piece of advice: stay humble, don't react when filled with emotion, and be willing to take criticism. <carshie> wrote in message news:45c1dbfe$1_3@mk-nntp-2.news.uk.tiscali.com... >> Maybe English is not your native language: >> The little word "and" at the beginning of the sentence changes a >> slightly pestering question to an obnoxious statement. >> If you are as ignorant in this technology as you seem to be, it would >> be wise to be more polite. > > You want me to be polite, going by this answer. > My first language is none of your business, this > remark could qualify you as something, I won't say to save > you the embarassment. > >> Any answer you get here from anybody is because we want to be helpful. >> Keep that in mind! >> Peter Alfke >> >> On Jan 31, 4:52 pm, <carshie> wrote: >> > and where did you get the 10C from, did I say I have 10C ? >> >> > >Article: 115161
Hi Maya,
I'm not sure if you have already tried the approach documented in the
ML403 users manual.
When you download the ML403 reference design you can find a linux
subdirectory. In there you find a shell script that you can run to
create the BSP inluding the .config for a MontaVista Linux 3.1 Linux
kernel (it will most likely also work with kernels from other sources).
With that the steps to successfully build a Linux kernel for the ML403
board are:
0. Download the ML403 reference design from http://www.xilinx.com/ml403
1. Copy the Linux kernel into a working directory.
2. Run XPS with system_linux.xmp and generate the BSP and bitstream
From the command line that is:
$ xps -nw system_linux.xmp
XPS% run libs
XPS% run init_bram
XPS% exit
3. Change to the linux sub-directory of the reference design and run
the script:
$ cd linux
$ ./patch_linux <root directory of the Linux kernel copy>
4. Change to the Linux kernel and build the kernel.
$ make clean
$ make oldconfig
$ make bzImage
5. Download the bitstream and Linux kernel to the board, start a
terminal at 9600 and voila.
$ xps -nw system_linux.xmp
XPS% run download
XPS% exit
$ xmd -nx
XMD% connect ppc hw
XMD% dow arch/ppc/boot/images/zImage.elf
XMD% con
This will boot the kernel from the System ACE CF card shipping with the
board. Now, if that works boot it up and mount the NFS root server manually.
# mount -t nfs <server:/rootdir> /mnt
That will allow you to debug potential problems with the NFS and DHCP
servers (for a start you might want to disable firewalls and SELinux on
your server).
Once NFS and DHCP work, shut down the board and reload the kernel. On
the kernel command line change "ip=off" to "ip=on
nfsroot=<server:/rootdir>" (without the <> brackets). If all goes well
the board will boot from NFS.
- Peter
sh3.m4y4 wrote:
> Hi,
>
> I have been trying to port MontaVista Linux 3.1 to ML403 board. The
> source compilation was successful. I have set up the NFS and DHCP as
> well. However, when trying to run MV on ML403, the kernel hangs on :
> Freeing unused kernel memory: 60k init. Does anybody know how to solve
> this problem? Thanks.
>
> Maya
>
Article: 115162After upgrading to Webpack 9.1 (and then directly to service pack 1) on a Windows XP machine connected to a Diligent Spartan 3 Stater Kit via a parallel cable I am no longer able to program the FPGA. Impact complains that "done did not go high" even though everything else (checking ID and such and the uploading itself) seems to be working fine. The board runs the example in its Flash just fine but is dead after I try to upload anything to it. I have some older .bit files which used to work, so the problem doesn't seem to be that 9.1 is generating a bad bitstream (my initial guess since it was so slow and actually crashed once). Since I had to uninstall the previous version (8.2, I think) before I could install this one I can't check using the old Impact. The computer is a Dell OptiPlex GX1. On a totally different subject, Webpack 7 had compiled the System09 example (an implementation of a 6809 computer) just fine for the Spartan 3 200 while Webpack 8 tried to allocate 13 block rams and failed. Webpack 9 only wants 5 block rams for the same design. I found this much variation a bit suprising, though I suppose this is due to differences in the default settings. -- JecelArticle: 115163
I've tryed ISE9.1 SP1.. and it crash!!! Then I come back with ISE8.2... and I can't open my old projects!!!Article: 115164
Quesito wrote: > I've tryed ISE9.1 SP1.. and it crash!!! > Then I come back with ISE8.2... and I can't open my old projects!!! This is because they changed the format for the project file again. If you start up ISE9.1, it loads your most recent project by default and automatically converts it to the new format, which cannot be read by ISE8. There's a yellow leaflet in the box to warn you about this. Of course, if you use WebPack, there's no box... :) -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 115165
The PowerPC simulation uses Smartmodels which are not supported by ModelSimXE. You either have to purchase a simulator that supports SmartModels, or with 9.1i, you can use the ISE Simulator. Steve <olive_dominguez@yahoo.fr> wrote in message news:1169737852.958434.125120@j27g2000cwj.googlegroups.com... > Hello, > > I am using the Xilinx EDK to perform simulations of the embedded > PowerPC on a Virtex 4 Fx. I have had no success using simply the EDK > (Simgen) with > ModelsimXE. Does anyone know how can I simulate with ModelsimXE ? Is it > possible to simulate PPC > behavorial? > > > Thanks, Olivier. >Article: 115166
Matt, OK, we will work with the mode pins as they are. By default, BitGen will have these pulled low. That puts the FPGA in master serial mode. Here, the FPGA will provide the CCLK so we do not want to configure the xcf32p (MCS file) to use the clkout feature or use an external osc. You should see the default frequency of ~ 4MHz on this pin supplied by the FPGA. From what I have gathered about your layout is that the JTAG pins connect all applicable devices on the board. That's great and you should be able to see and program via JTAG (as per your initial post). Remember that how ever your mode pins are set, you always have JTAG functionality. I also gathered that you have one of the proms tied to the V4FX12 (that's a big prom for a small device). You say that you have the DOUT/BUSY and CS pins connected between the prom the FPGA. These are not required as they are only applicable for parallel and/or daisy chain configurations. At this time, I am not sure if they pose a problem. DOUT of the FPGA will only be an output if the LOUT word is seen in the configuration bitstream and is used for sending configuration data to a downstrem device. Additionally, as the mode pins are in a master serial mode, the CS pin should not be configured as a chip select. Has looking at the scope shots of your configuration pins helped (i.e. compare them then to what you see in the Configuration Users Guide)? Here are some basics to look for: -Upon powerup or PROG pulse, do you see INIT transition from high to low (and stay low until DONE goes high)? -Does DONE go high? -What is the CCLK frequency? -Do you see the synchronization word on the Din pin? -Are the PCB traces connected to the correct pins on the FPGA/prom? -Are the proper pullups in place (i.e. DONE, INIT and PROG)? -David "matteo" <matt.fischler@gmail.com> wrote in message news:1170289738.775595.316490@a34g2000cwb.googlegroups.com... > Thanks for the response, David, > > Unfortunately I'm stuck with unconnected mode pins in this prototype > of the board. > > One of the PROMs has connections to the FPGA with the following pins: > FPGA_DOUT_BUSY > FPGA_PROG_B > FPGA_CCLK > FPGA_INIT > FPGA_CS_B > FPGA_DIN > > I'm assuming that the FPGA can either be programmed with the JTAG pins > (TDI,TCK,TMS,TDO) which I'm currently using in boundary scan mode, or > the pins I listed above. Is the first known as Slave Serial and the > latter known as SelectMAP? Am I hosed without the mode pins? > > Thanks again, > Matt > > >> Matt, >> >> There could be a multitude of scenarios on why a PROG pulse of power-up >> will >> not start the configuration sequence from the prom(s). I will go over >> some >> basics in a logical order and you will have to do some debugging based on >> that and other(s) suggestions. >> >> First, is to not leave the mode pins untied. Pull them up or down >> according >> to the configuration mode you are looking for. The weak pullup/downs on >> these pins are not sufficient to guarantee the proper mode setting >> especially in a noisy environment. >> >> Make sure that you have generated the MCS files correctly especially if >> you >> have multiple proms. You might find that both proms are trying to >> deliver >> configuration bits simultaneously creating contention on the FPGA Din >> pin. >> If the MCS files are generated correctly, one prom will tristate its Dout >> pin preventing any contention. Also make sure that the prom that >> contains >> the configuration data is driving the clkout pin (assuming you are not >> using >> an external osc). I would recommend putting a scope on PROG, INIT, CCLK, >> Din, CE/CEO pins to make sure they are behaving as expected. >> >> Also refer to the PFP Users Guide to make sure that you have the proper >> routing on the various configuration pins that connect the proms to the >> FPGA(s). Verify that the pins requiring pullups have them. >> >> -David >> >> "matteo" <matt.fisch...@gmail.com> wrote in message >> >> news:1170274492.883955.229870@v33g2000cwv.googlegroups.com... >> >> > I'm confused about how to configure the FPGA via the platform flash >> > XCF32P Prom. I have a JTAG serial chain that goes >> >> > connector -> xcf32p -> xcf32p -> Virtex4 FX12 ----- >> >> > ^ | >> > |_____________________________________| >> >> > The connector goes to my platform cable USB and I can successfully >> > program the FPGA and each xcf32p in boundary scan mode. My question is >> > how do I get one of the Proms to auto-configure the FPGA? The mode >> > pins on the FPGA are unconnected, which in the documentation means >> > that it's set to slave serial mode. I've tried taking the bit file for >> > the FPGA and generating an MCS file for the PROM, then writing the MCS >> > to the PROM (tried both external clock setting and use internal >> > clock). I expect the PROM to magically find the FX12 in the chain and >> > configure it. Is there another setting that I'm missing? >> >> > Thanks, >> > Matt > >Article: 115167
Vijay, Is it possible that you are using WebPACK? If so, this explains the problem. There are a limited number of devices that are supported on the free software and are generally the smaller desities. You may have to buy the full ISE software (or use an evaluation version for 90 days free). -David <pcvijay30@gmail.com> wrote in message news:1170316215.079693.219310@m58g2000cwm.googlegroups.com... > Hi , > > I am new to fpga and I am writing a program for my xilinx virtex 2 > xc2v6000 chip. since my ISE software doesn't contain the device in its > properties tab . Hence I am unable to synthesise the project for the > device .Kindly suggest ways to resolve this problem . > > Thanks in advance > > Vijay >Article: 115168
On Feb 1, 3:28 pm, Sean Durkin wrote: > This is because they changed the format for the project file again. If > you start up ISE9.1, it loads your most recent project by default and > automatically converts it to the new format, which cannot be read by ISE8. I think the old version was saved as a .zip somewhere. So it should be possible to recover. > There's a yellow leaflet in the box to warn you about this. Of course, > if you use WebPack, there's no box... :) And the dialog box asks permission before converting the project. It also asks permission to save the old version (I think) and tells you where it put it, but I didn't pay attention to that. I can easily load that particular project from the Internet again if I need to, so I wasn't worried about that.Article: 115169
The Spartan-3E datasheet indicates that the devices only support 2.5V differential output standards (LVDS and LVPECL), and VCCO must be set to 2.5V to use these. We have only two differential "LVPECL_33" outputs that are required, and the rest of the signals from the device are single-ended LVCMOS_33. 1. Can a differential output (OBUFDS, I assume) be safely operated in a bank with VCCO=3.3V? 2. Is there any "legal" way to instantiate this in the schematic editor? I understand that it will only permit LVDS_25 differential outputs, and nothing at 3.3V. Mixing 2.5 and 3.3V standards within a bank will generate an error, as will attempting to set a differential output for a 3.3V standard. 3. If no legal way, is it possible to tell the compiler that the entire bank is 2.5V, (use LVDS_25 for differential I/O, and LVCMOS_25 for single-ended I/O), while really applying 3.3V to the bank's VCCO pins? I wonder if there are any pitfalls to this approach... I don't mind if I need a couple resistors at the output of each differential pair to level-shift things properly to LVPECL levels, but it will be exceedingly inconvenient if we must run the entire bank at a VCCO of 2.5V for the sake of the two differential signals. This will force us to place current limit resistors on all the other input pins (which are driven by 3.3V CMOS) to avoid forcing too much current into the input protection diodes. TIA to anybody who can offer help.Article: 115170
On the Spartan-3E, LVPECL is input only! This may contribute to why you find no 3.3V compliant standards in the data sheet. The issue of running 2.5V standards at 3.3V reliably really should be taken up directly with your FAE rather than with this newsgroup. If it were a "sure, yeah, anyone can do it" issue, wouldn't the parts already be characterized that way? The 3.3V LVPECL standard's last foot in the Spartan series was the Spartan-IIE. The Spartan-3 tried an LVPECL_25 version that wasn't continued into later parts. Odds don't look good in your favor. <LT1Z07@yahoo.com> wrote in message news:1170363546.085815.186430@p10g2000cwp.googlegroups.com... > The Spartan-3E datasheet indicates that the devices only support 2.5V > differential output standards (LVDS and LVPECL), and VCCO must be set > to 2.5V to use these. > > We have only two differential "LVPECL_33" outputs that are required, > and the rest of the signals from the device are single-ended > LVCMOS_33. > > 1. Can a differential output (OBUFDS, I assume) be safely operated in > a bank with VCCO=3.3V? > > 2. Is there any "legal" way to instantiate this in the schematic > editor? I understand that it will only permit LVDS_25 differential > outputs, and nothing at 3.3V. Mixing 2.5 and 3.3V standards within a > bank will generate an error, as will attempting to set a differential > output for a 3.3V standard. > > 3. If no legal way, is it possible to tell the compiler that the > entire bank is 2.5V, (use LVDS_25 for differential I/O, and LVCMOS_25 > for single-ended I/O), while really applying 3.3V to the bank's VCCO > pins? I wonder if there are any pitfalls to this approach... > > > I don't mind if I need a couple resistors at the output of each > differential pair to level-shift things properly to LVPECL levels, but > it will be exceedingly inconvenient if we must run the entire bank at > a VCCO of 2.5V for the sake of the two differential signals. This > will force us to place current limit resistors on all the other input > pins (which are driven by 3.3V CMOS) to avoid forcing too much current > into the input protection diodes. > > TIA to anybody who can offer help. >Article: 115171
On Feb 1, 4:20 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > On the Spartan-3E, LVPECL is input only! Right, the supported output is "LVDS_25". I suspect that the outputs "want" to be symmetrical around VCCO/2, which is the 1.25V VCM of LVDS_25. LVPECL has a different common mode voltage. > This may contribute to why you find no 3.3V compliant standards in the data > sheet. Agreed. What I'm not clear on is what changes are made to the output structure to shift things around. Presumably, a stronger pull-up device and weaker pull-down would give the needed behavior, but I wonder if this couldn't just be done with a resistor network, assuming the swings are sufficient? > The 3.3V LVPECL standard's last foot in the Spartan series was the > Spartan-IIE. The Spartan-3 tried an LVPECL_25 version that wasn't continued > into later parts. Odds don't look good in your favor. We're trying to replace a Spartan-IIE. In that device, the differential outputs seemed to swing rail-to-rail (I think), and you just controlled the output swings and common-mode with output resistors if needed. I'm wondering if I can do this here? Or does the Spartan 3E really control the swings internally? One last thought... Can I simply program the two pins of a differential pair as single- ended LVCMOS_33, and just drive one with an inverted signal? The full- voltage output swing does not bother me at all - five resistors (two up, two down, one across) will get me to LVPECL_33 levels. Only issue is whether I'm taking my chances with skew between the outputs.Article: 115172
On Jan 31, 9:40 am, "Gabor" <g...@alacron.com> wrote: > On Jan 30, 11:48 am, "idp2" <ian.pei...@gmail.com> wrote: > > > Yea, I figured that was the case. However, I have no always > > statements that are not of the form: > > > always @(posedge clk) > > begin > > foo <= bar > > end > > > all of my always statements are driven off of clock. I do have if > > statements within the always statements that depend on rst. will this > > cause it to be seen as a clock? > > If the always block is not a clocked block, i.e. always @* > it is possible to create latches. In the FPGA fabric the > gate input of a latch uses the clock routing. Did you check if > there were any transparent latches created in synthesis? What I was doing wrong was assigning wires to 0 upon rst. This in turn caused rst to be viewed as a global clock. Thanks for all of your help. IanArticle: 115173
I am constantly getting the following warnings when compiling in Xilinx: FF/Latch <thresh_0> (without init value) has a constant value of 0 in block <calibrate> I do not understand why this happens since I set thresh to 0 on rst signal. Here's my code: //determine the threshold value reg[7:0] thresh; always @(posedge clk) begin if(~done & stepCnt==2 & cal_cnt==3 & sampCtr==511) thresh <= mean8*ALPHA; else if(rst) thresh[7:0] <= 8'h00; end Thanks, IanArticle: 115174
On Feb 1, 5:12 pm, "idp2" <ian.pei...@gmail.com> wrote: > I am constantly getting the following warnings when compiling in > Xilinx: > FF/Latch <thresh_0> (without init value) has a constant value of 0 in > block <calibrate> > > I do not understand why this happens since I set thresh to 0 on rst > signal. > Here's my code: > > //determine the threshold value > reg[7:0] thresh; > always @(posedge clk) > begin > if(~done & stepCnt==2 & cal_cnt==3 & sampCtr==511) > thresh <= mean8*ALPHA; > else if(rst) > thresh[7:0] <= 8'h00; > end > > Thanks, > Ian What you describe does not have an asynchronous reset term, which may cause the "without init value", but the real point of the warning is that bit 0 of thresh doesn't ever become nonzero, not that there is no init value. I'm guessing that either mean8 or ALPHA is always even?
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