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On Jan 31, 9:35 am, n...@puntnl.niks (Nico Coesel) wrote: > Be realistic and don't let yourself fooled by succes stories. If you > stay within the timing limits of the FPGA, you'll be just fine. And > remember: there are no free DDR implementations available. So either > roll your own or buy one. Huh? In which sense is the OpenCore DDR controller not free (Thanks to David Ashley it runs just fine on my Spartan 3E kit)? Also ISTR seeing other alternatives, but they may have had slightly more restrictive licences. That said, I think there plenty of room for a clean, simple, and unencumbered (ie., free) DDR controller in Verilog. TommyArticle: 115126
> See Answer Record 1067. It will be able answer all your questions regarding > to part markings: > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=1067 I looked, there is no answer to my question. My xc9536 does not carry the markings mentioned there, all I have is as follows: xc9536 tm pc44amm0521 f3002413a 7c > > -David > > <carshie> wrote in message news:45c0c8d3_3@mk-nntp-2.news.uk.tiscali.com... > >> Did you take a look at the datasheets? > > > > Having looked in the datasheet (belatently) there is another question, > > in the top of the datasheet the pin to pin delay is quoted as 5ns, then > > down below we see also 6ns 7ns 10ns 15ns. So do they mean to > > say that 5ns is the fastest one, but slower one are also available? > > > > Another question, I have here a xc9536 which has the following marking > > > > xc9536 tm > > pc44amm0521 > > f3002413a > > > > 7c > > > > What speed would it be? I can't find the ordering number on the part, > > or should have I made a note of it when I bought it (so how would I > > to know if my supplier did not send me a different spec?) > > > > > >> > >> -- > >> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > >> > >> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > >> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > > > > >Article: 115127
Hello, I have the following VSD (very simple design) module a2v(clka, clkb); input clka; output clkb; buf b1(clkb,clka); endmodule I expect the clock input to come out as the output (with a delay or not/whatever) I then goto simulation waveform, and the output changes to 1 and then stays at 1. Any ideas why that would be so?Article: 115128
Did you actually look at Solution2? You may not be using Virtex-4 but the rest of the lines appear verbatim correct to your description. <carshie> wrote in message news:45c0dca6_2@mk-nntp-2.news.uk.tiscali.com... >> See Answer Record 1067. It will be able answer all your questions > regarding >> to part markings: >> > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=1067 > > > I looked, there is no answer to my question. My xc9536 does not carry > the markings mentioned there, all I have is as follows: > > xc9536 tm > pc44amm0521 > f3002413a > > 7c > > > >> >> -David >> >> <carshie> wrote in message > news:45c0c8d3_3@mk-nntp-2.news.uk.tiscali.com... >> >> Did you take a look at the datasheets? >> > >> > Having looked in the datasheet (belatently) there is another question, >> > in the top of the datasheet the pin to pin delay is quoted as 5ns, then >> > down below we see also 6ns 7ns 10ns 15ns. So do they mean to >> > say that 5ns is the fastest one, but slower one are also available? >> > >> > Another question, I have here a xc9536 which has the following marking >> > >> > xc9536 tm >> > pc44amm0521 >> > f3002413a >> > >> > 7c >> > >> > What speed would it be? I can't find the ordering number on the part, >> > or should have I made a note of it when I bought it (so how would I >> > to know if my supplier did not send me a different spec?) >> > >> > >> >> >> >> -- >> >> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de >> >> >> >> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >> >> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- >> > >> > >> >> > >Article: 115129
On Jan 31, 1:21 pm, <carshie> wrote: > Hello, > > I have the following VSD (very simple design) > > module a2v(clka, clkb); > input clka; > output clkb; > buf b1(clkb,clka); > endmodule > > I expect the clock input to come out as the output (with a delay or > not/whatever) > I then goto simulation waveform, and the output changes to 1 and > then stays at 1. Any ideas why that would be so? Some questions: 1) are you saying that clka is toggling in the simulation, but clkb goes high and stays high? 2) what simulator? 3) did you look at the simulation model for buf? Are you sure the order of the module ports is correct in your instantiation?Article: 115130
carshie wrote: > I can't find any help files about schematic entry, please advise? The best help would be the advice; DON'T DO IT ;) Really, I used schematics for many years, but finally abandoned them completely (except for PC board layout). The main problem is the lack of portability. The schematics formats are all basically proprietary, and every one I have used has become obsolete. I have had projects where we have had to keep an old computer kept stuck in a corner for years, to support an old project that was created with some now obsolete schematic package that only ran on Win3.1 (in the space business, maintaining this support for years is important). With an HDL, tools may come and go, but VHDL and Verilog should remain portable and useful for many years to come.Article: 115131
I checked with our Applications memory interface group, and this is their answer: "It depends on the target frequency and the target FPGA device. He is targeting a DDR SDRAM at 200 MHz which is possible in V5 at any speed grade. In V2Pro and Spartan-3 a template router must be used for data capture using memory strobe and this requires adhering to pin placement rules which makes it less flexible. In V4 we have two techniques, the Direct Clocking technique (does not use the memory strobe instead calibrates to center align data from memory to FPGA clock using the IDELAY) for 240 MHz (-12 device) and below. The other technique uses the ISERDES and the BUFIO clocking resource to route the memory strobe for first stage capture in the strobe domain and transfer to the FPGA clock domain. The ISERDES technique supports up to 300 MHz in a -12 device. In V5 we use the ISERDES also and we support up to 333 MHz in the fastest speed grade device (-3)." All of these designs are "free", no license fees, and Xilinx has several memory-interface evaluation boards. Contact a Xilinx FAE to guide you through these different design approaches. 200 MHz = 400 Mbps is not difficult anymore. Twice that speed is challenging,... Peter Alfke, Xilinx Applications On Jan 31, 10:13 am, "Tommy Thorn" <tommy.th...@gmail.com> wrote: > On Jan 31, 9:35 am, n...@puntnl.niks (Nico Coesel) wrote: > > > Be realistic and don't let yourself fooled by succes stories. If you > > stay within the timing limits of the FPGA, you'll be just fine. And > > remember: there are no free DDR implementations available. So either > > roll your own or buy one. > > Huh? In which sense is the OpenCore DDR controller not free (Thanks to > David Ashley it runs just fine on my Spartan 3E kit)? Also ISTR seeing > other alternatives, but they may have had slightly more restrictive > licences. > > That said, I think there plenty of room for a clean, simple, and > unencumbered (ie., free) DDR controller in Verilog. > > TommyArticle: 115132
I'm confused about how to configure the FPGA via the platform flash
XCF32P Prom. I have a JTAG serial chain that goes
connector -> xcf32p -> xcf32p -> Virtex4 FX12 -----
^ |
|_____________________________________|
The connector goes to my platform cable USB and I can successfully
program the FPGA and each xcf32p in boundary scan mode. My question is
how do I get one of the Proms to auto-configure the FPGA? The mode
pins on the FPGA are unconnected, which in the documentation means
that it's set to slave serial mode. I've tried taking the bit file for
the FPGA and generating an MCS file for the PROM, then writing the MCS
to the PROM (tried both external clock setting and use internal
clock). I expect the PROM to magically find the FX12 in the chain and
configure it. Is there another setting that I'm missing?
Thanks,
Matt
Article: 115133>Clocking the data from the memory is an issue if you use fpga's. >Timing may vary a bit from device to device. The more layers of logic >you add to the data input path, the bigger the variation in timing, >the worse things get (this is why the MIG tool from Xilinx makes such >a kludge of a DDR implementation). Use the flipflops in the IO cell to >clock the data into the fpga. If you take all the timing variations >and jitter into account, you can determine a window (with respect to >the DDR clock) in which the data will be stable. The only thing you >need is a (shifted) clock with an edge inside that window. If you >can't get the window big enough, lower the frequency or use a faster fpga. Is there a minimum transfer speed for ddr & ddr2 memories ..? Ie should you want to clock them at 10 MHz, then you can't etc..Article: 115134
> Some questions: > > 1) are you saying that clka is toggling in the simulation, > but clkb goes high and stays high? Yes!!! > > 2) what simulator? > ISE 8.2 Test Bench Waveform - Generate Expected Simulation > 3) did you look at the simulation model for buf? Are you sure the > order of the module ports is correct in your instantiation? > No I didn't look at this, but I believe with and/or/not/buf the convention is output comes before the input.Article: 115135
> Did you actually look at Solution2? > > You may not be using Virtex-4 but the rest of the lines appear verbatim > correct to your description. Well, if you believe that then you tell me, what is my propagation delay time? > > > <carshie> wrote in message news:45c0dca6_2@mk-nntp-2.news.uk.tiscali.com... > >> See Answer Record 1067. It will be able answer all your questions > > regarding > >> to part markings: > >> > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=1067 > > > > > > I looked, there is no answer to my question. My xc9536 does not carry > > the markings mentioned there, all I have is as follows: > > > > xc9536 tm > > pc44amm0521 > > f3002413a > > > > 7c > > > > > > > >> > >> -David > >> > >> <carshie> wrote in message > > news:45c0c8d3_3@mk-nntp-2.news.uk.tiscali.com... > >> >> Did you take a look at the datasheets? > >> > > >> > Having looked in the datasheet (belatently) there is another question, > >> > in the top of the datasheet the pin to pin delay is quoted as 5ns, then > >> > down below we see also 6ns 7ns 10ns 15ns. So do they mean to > >> > say that 5ns is the fastest one, but slower one are also available? > >> > > >> > Another question, I have here a xc9536 which has the following marking > >> > > >> > xc9536 tm > >> > pc44amm0521 > >> > f3002413a > >> > > >> > 7c > >> > > >> > What speed would it be? I can't find the ordering number on the part, > >> > or should have I made a note of it when I bought it (so how would I > >> > to know if my supplier did not send me a different spec?) > >> > > >> > > >> >> > >> >> -- > >> >> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > >> >> > >> >> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > >> >> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > >> > > >> > > >> > >> > > > > > >Article: 115136
"Tommy Thorn" <tommy.thorn@gmail.com> wrote: >On Jan 31, 9:35 am, n...@puntnl.niks (Nico Coesel) wrote: >> Be realistic and don't let yourself fooled by succes stories. If you >> stay within the timing limits of the FPGA, you'll be just fine. And >> remember: there are no free DDR implementations available. So either >> roll your own or buy one. > >Huh? In which sense is the OpenCore DDR controller not free (Thanks to >David Ashley it runs just fine on my Spartan 3E kit)? Also ISTR seeing >other alternatives, but they may have had slightly more restrictive >licences. The Opencores DDR controller has serious limitations (burst length and IIRC the kludgy clocking scheme for instance). If you want the full version, you're supposed to pay. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 115137
pbFJKD@ludd.invalid wrote: >>Clocking the data from the memory is an issue if you use fpga's. >>Timing may vary a bit from device to device. The more layers of logic >>you add to the data input path, the bigger the variation in timing, >>the worse things get (this is why the MIG tool from Xilinx makes such >>a kludge of a DDR implementation). Use the flipflops in the IO cell to >>clock the data into the fpga. If you take all the timing variations >>and jitter into account, you can determine a window (with respect to >>the DDR clock) in which the data will be stable. The only thing you >>need is a (shifted) clock with an edge inside that window. If you >>can't get the window big enough, lower the frequency or use a faster fpga. > >Is there a minimum transfer speed for ddr & ddr2 memories ..? >Ie should you want to clock them at 10 MHz, then you can't etc.. > Some memories can operate down to 83MHz. A Spartan 3 series speedgrade 4 FPGA can be interfaced with DDR memory at 100MHz without problems. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 115138
hello,
first of all, i apologize for posting this in multiple groups. i
recently start teaching at a university and i am trying to develop a
course in electronic design automation. typically such a course is
offered at the graduate level in most colleges/universities, i am
thinking of developing a two-semester course rather than the
traditional one semester (i.e. 12-14 weeks). the target audience will
be seniors and graduate students since villanova is mainly an
undergraduate institution so far.
i wanted to get some of your opinions on the current course content
that i have in mind (see below), and what you think should be the most
important topics students should know from taking a course in EDA.
clearly it is a very broad area and the amount of time and my
knowledge in EDA limits what I can and cannot teach.
my main goal is to ensure students understand some of the basic
algorithms that are used in EDA tools and be able to program a simple
stand-alone EDA system (a very simple version of SIS - the synthesis
tool from Berkeley) in two semesters. the idea is to help them in
three fronts, algorithms for EDA, EDA programming, general software
development techniques. note that the goal of this course is not to
use EDA tools but to try to see how such tools are developed.
in the first semester I have the following basic topics (and
assignments) in mind. the first semester will consist mainly of
introduction to basic ideas and topics while the second semester will
go in more detail into the algorithms.
first semester
1. CAD/EDA design flow
2. Circuit I/O, Parsing, and Data Structures (a simple BLIF/NetBLIF
format)
HW - write a circuit parser and netlist generator
3. Gate-level logic simulation, threshold logic/majority/minority
logic simulation
- Brute force (one vector at a time)
- Parallel simulation (32/64 vecs at a time)
- Event-driven parallel simulation
HW - write a event-driven logic simulator
4. Representation of Boolean functions
- Truth tables, covers, binary decision diagrams, reduced ordered
binary decision diagrams
- Uses of ROBDDs
HW - write a simple BDD
5. Introduction to Boolean Satisfiability
- CNF representation
- Convering a gate level circuit to CNF
- Use boolean satifiability in circuit verification, mitre
circuits
HW - write a simple SAT solver
6. Introduction to Synthesis and Technology Mapping
- Explain synthesis
- Technology libraries, cost models, technology mapping using tree
covering
- Netlist generation
HW - write a basic technology mapper with a small library (10
gates) and a few cost models
7. Introduction to Static Timing Analysis
- Component/Gate delay calculation, setup/hold/arrival times
HW - write a basic static timing analyzer
8. Introduction to FPGA systems
- Architecture
- LUT
- How synthesis tools are different/same from non-FPGA (i.e. ASIC)
systems
------------------------------------------------------------------------------------------------------------------------------
second semester
1. Two-level synthesis
- quine-mcluskey
- heurisitc based using expand, reduce, irredundant
2. Multi-level synthesis
- albegraic/boolean factorization
- kernels and co-kernels
HW- implement two-level synthesis? (not sure, its not that easy
to program, i.e. significant code..espresso)
3. Introduction to Testing
- Fault models, collapsing
- Fault simulation (types of fault simulation, parallel, concurrent
etc)
HW - Implement a fault simulator
Test Generation
- D/PODEM/FAN
- based on boolean satifiability
HW - Implement PODEM and/or boolean satisfiability (use the SAT
solver we developed earlier)
4. Introduction to Routing
- Partitioning and placement
- Routing
HW - very difficult to give, requires significant code and most
techniques are quite adhoc
5. Introduction to Synthesis of FSM
6. Current research trends in CAD/EDA - CAD for post-CMOS
technologies...
hopefully as the course evolves, new assigments on additional topics
will be created such that they fit in within the entire "example" EDA
system the students will be writing in semester 1/2. from there the
goal would be me to make this entire set of assignments open source so
others who want to learn about EDA can choose to do so by having
access to the program code, skeleton files, etc, lecture slides..
i would appreciate your comments on the course content or any other
suggestions you think would be worthwhile to consider as i start
developing this course. note that i can't teach much about FPGA/
routing/DFM/DSM as i'm not very familiar with them yet. you can email
me at the above address if you don't want to post here. all responses
will be kept confidential.
thanks for your help.
pallav
Article: 115139This is the answer I got from the Xilinx Memory Interface group: It depends on the target frequency and the target FPGA device. He is targeting a DDR SDRAM at 200 MHz which is possible in V5 any speed grade. In V2Pro and Spartan-3 a template router must be used for data capture using memory strobe and this requires adhering to pin placement rules which makes it less flexible. In V4 we have two techniques, the Direct Clocking technique (does not use the memory strobe instead calibrates to center align data from memory to FPGA clock using the IDELAY) for 240 MHz (-12 device) and below. The other technique uses the ISERDES and the BUFIO clocking resource to route the memory strobe for first stage capture in the strobe domain and transfer to the FPGA clock domain. The ISERDES technique supports up to 300 MHz in a -12 device. In V5 we use the ISERDES also and we support up to 333 MHz in the fastest speed grade device (-3). All these designs are free (no fees). I suggest you call a Xilinx FAE to sort out the possibilities. 200 MHz = 400 M reads or writes are not a problem anymore. Peter Alfke, Xilinx Applications On Jan 31, 8:39 am, Mounard Le Fougueux <blinkingCur...@NonEventHorizon.com> wrote: > I'm planning an FPGA design that will be using SDRAM (DDR Winbond > W9425G6DH5) and NAND Flash (ST NAND018W3B2AN6E). I'm not particularly > experienced in DDR memory design and there are other issues that need my > attention other then just DDR RAM design. > > I keep hearing horror stories about engineers getting into trouble with > DDR RAM designs. Do you have any experience integrating DDR to FPGAs and > how do you recommend I kkep out of trouble. > > ThanksArticle: 115140
"Nico Coesel" <nico@puntnl.niks> wrote in message news:45c10209.1209218664@news.kpnplanet.nl... > pbFJKD@ludd.invalid wrote: > <snip> >> >>Is there a minimum transfer speed for ddr & ddr2 memories ..? >>Ie should you want to clock them at 10 MHz, then you can't etc.. >> > > Some memories can operate down to 83MHz. A Spartan 3 series speedgrade > 4 FPGA can be interfaced with DDR memory at 100MHz without problems. <snip> DDR2 memories have a guaranteed bottom end of 125 MHz. In either case, the memory data sheet will show you the minimum frequency your memory device is specified for. If the chip uses a DLL to align the strobes, a minimum frequency spec is necessary. - John_HArticle: 115141
<carshie> wrote in message news:45c1011c$1_1@mk-nntp-2.news.uk.tiscali.com... >> Did you actually look at Solution2? >> >> You may not be using Virtex-4 but the rest of the lines appear verbatim >> correct to your description. > > Well, if you believe that then you tell me, what is my propagation > delay time? > <snip> 7 ns, Commercial grade. Changing the "10C" to "7C" in the illustration to match your part would make the following text applicable: Line 4 Device speed grade (7) and temperature range (C). If a grade is not marked on the package, the product is considered commercial grade. In addition to the mark shown above, Line 4 can contain a few other variations as described below: 7C xxxx The "xxxx" indicates the SCD for the device. An SCD is a special ordering code that is not always marked in the device top mark. 7CES The "ES" indicates an Engineering Sample (as opposed to a production device). 7CESn The "n" is a numeral (1, 2, 3, etc.) The "ES" indicates an Engineering Sample, the "n" indicates an ES revision code. For example, ES1, ES2, ES3, etc. Please see Errata for appropriate information. To obtain Errata, you must register for MySupport, see (Xilinx Answer 21491). 7CESnL or 7CESnR This part marking is used only for Virtex-4 FX engineering sample devices. The "L" indicates that only left (column 0) MGTs are available and the "R" indicates that only the right (column 1) MGTs are available when looking at the device from the "bottom-up."Article: 115142
Matt, There could be a multitude of scenarios on why a PROG pulse of power-up will not start the configuration sequence from the prom(s). I will go over some basics in a logical order and you will have to do some debugging based on that and other(s) suggestions. First, is to not leave the mode pins untied. Pull them up or down according to the configuration mode you are looking for. The weak pullup/downs on these pins are not sufficient to guarantee the proper mode setting especially in a noisy environment. Make sure that you have generated the MCS files correctly especially if you have multiple proms. You might find that both proms are trying to deliver configuration bits simultaneously creating contention on the FPGA Din pin. If the MCS files are generated correctly, one prom will tristate its Dout pin preventing any contention. Also make sure that the prom that contains the configuration data is driving the clkout pin (assuming you are not using an external osc). I would recommend putting a scope on PROG, INIT, CCLK, Din, CE/CEO pins to make sure they are behaving as expected. Also refer to the PFP Users Guide to make sure that you have the proper routing on the various configuration pins that connect the proms to the FPGA(s). Verify that the pins requiring pullups have them. -David "matteo" <matt.fischler@gmail.com> wrote in message news:1170274492.883955.229870@v33g2000cwv.googlegroups.com... > I'm confused about how to configure the FPGA via the platform flash > XCF32P Prom. I have a JTAG serial chain that goes > > connector -> xcf32p -> xcf32p -> Virtex4 FX12 ----- > > ^ | > |_____________________________________| > > The connector goes to my platform cable USB and I can successfully > program the FPGA and each xcf32p in boundary scan mode. My question is > how do I get one of the Proms to auto-configure the FPGA? The mode > pins on the FPGA are unconnected, which in the documentation means > that it's set to slave serial mode. I've tried taking the bit file for > the FPGA and generating an MCS file for the PROM, then writing the MCS > to the PROM (tried both external clock setting and use internal > clock). I expect the PROM to magically find the FX12 in the chain and > configure it. Is there another setting that I'm missing? > > Thanks, > Matt >Article: 115143
hello,
first of all, i apologize for posting this in multiple groups. i
recently start teaching at a university and i am trying to develop a
course in electronic design automation. typically such a course is
offered at the graduate level in most colleges/universities and
generally only involves discussion of algorithms (not too heavy on
implementation, from browsing through courses websites online), i am
thinking of developing a two-semester course rather than the
traditional one semester (i.e. 12-14 weeks). the target audience will
be seniors and graduate students since villanova is mainly an
undergraduate institution so far.
i wanted to get some of your opinions on the current course content
that i have in mind (see below), and what you think should be the most
important topics students should know from taking a course in EDA.
clearly it is a very broad area and the amount of time and my
knowledge in EDA limits what I can and cannot teach.
my main goal is to ensure students understand some of the basic
algorithms that are used in EDA tools and be able to program a simple
stand-alone EDA system (a very simple version of SIS - the synthesis
tool from Berkeley) in two semesters. the idea is to help them in
three fronts, algorithms for EDA, EDA programming, general software
development techniques. note that the goal of this course is not to
use EDA tools but to try to see how such tools are developed.
in the first semester I have the following basic topics (and
assignments) in mind. the first semester will consist mainly of
introduction to basic ideas and topics while the second semester will
go in more detail into the algorithms.
first semester
1. CAD/EDA design flow
2. Circuit I/O, Parsing, and Data Structures (a simple BLIF/NetBLIF
format)
HW - write a circuit parser and netlist generator
3. Gate-level logic simulation, threshold logic/majority/minority
logic simulation
- Brute force (one vector at a time)
- Parallel simulation (32/64 vecs at a time)
- Event-driven parallel simulation
HW - write a event-driven logic simulator
4. Representation of Boolean functions
- Truth tables, covers, binary decision diagrams, reduced ordered
binary decision diagrams
- Uses of ROBDDs
HW - write a simple BDD
5. Introduction to Boolean Satisfiability
- CNF representation
- Convering a gate level circuit to CNF
- Use boolean satifiability in circuit verification, mitre
circuits
HW - write a simple SAT solver
6. Introduction to Synthesis and Technology Mapping
- Explain synthesis
- Technology libraries, cost models, technology mapping using tree
covering
- Netlist generation
HW - write a basic technology mapper with a small library (10
gates) and a few cost models
7. Introduction to Static Timing Analysis
- Component/Gate delay calculation, setup/hold/arrival times
HW - write a basic static timing analyzer
8. Introduction to FPGA systems
- Architecture
- LUT
- How synthesis tools are different/same from non-FPGA (i.e. ASIC)
systems
------------------------------------------------------------------------------------------------------------------------------
second semester
1. Two-level synthesis
- quine-mcluskey
- heurisitc based using expand, reduce, irredundant
2. Multi-level synthesis
- albegraic/boolean factorization
- kernels and co-kernels
HW- implement two-level synthesis? (not sure, its not that easy
to program, i.e. significant code..espresso)
3. Introduction to Testing
- Fault models, collapsing
- Fault simulation (types of fault simulation, parallel, concurrent
etc)
HW - Implement a fault simulator
Test Generation
- D/PODEM/FAN
- based on boolean satifiability
HW - Implement PODEM and/or boolean satisfiability (use the SAT
solver we developed earlier)
4. Introduction to Routing
- Partitioning and placement
- Routing
HW - very difficult to give, requires significant code and most
techniques are quite adhoc
5. Introduction to Synthesis of FSM
6. Current research trends in CAD/EDA - CAD for post-CMOS
technologies...
hopefully as the course evolves, new assigments on additional topics
will be created such that they fit in within the entire "example" EDA
system the students will be writing in semester 1/2. from there the
goal would be me to make this entire set of assignments open source so
others who want to learn about EDA can choose to do so by having
access to the program code, skeleton files, etc, lecture slides..
i would appreciate your comments on the course content or any other
suggestions you think would be worthwhile to consider as i start
developing this course. note that i can't teach much about FPGA/
routing/DFM/DSM as i'm not very familiar with them yet. you can email
me at the above address if you don't want to post here. all responses
will be kept confidential.
thanks for your help.
pallav
Article: 115144Thanks for the response, David, Unfortunately I'm stuck with unconnected mode pins in this prototype of the board. One of the PROMs has connections to the FPGA with the following pins: FPGA_DOUT_BUSY FPGA_PROG_B FPGA_CCLK FPGA_INIT FPGA_CS_B FPGA_DIN I'm assuming that the FPGA can either be programmed with the JTAG pins (TDI,TCK,TMS,TDO) which I'm currently using in boundary scan mode, or the pins I listed above. Is the first known as Slave Serial and the latter known as SelectMAP? Am I hosed without the mode pins? Thanks again, Matt > Matt, > > There could be a multitude of scenarios on why a PROG pulse of power-up will > not start the configuration sequence from the prom(s). I will go over some > basics in a logical order and you will have to do some debugging based on > that and other(s) suggestions. > > First, is to not leave the mode pins untied. Pull them up or down according > to the configuration mode you are looking for. The weak pullup/downs on > these pins are not sufficient to guarantee the proper mode setting > especially in a noisy environment. > > Make sure that you have generated the MCS files correctly especially if you > have multiple proms. You might find that both proms are trying to deliver > configuration bits simultaneously creating contention on the FPGA Din pin. > If the MCS files are generated correctly, one prom will tristate its Dout > pin preventing any contention. Also make sure that the prom that contains > the configuration data is driving the clkout pin (assuming you are not using > an external osc). I would recommend putting a scope on PROG, INIT, CCLK, > Din, CE/CEO pins to make sure they are behaving as expected. > > Also refer to the PFP Users Guide to make sure that you have the proper > routing on the various configuration pins that connect the proms to the > FPGA(s). Verify that the pins requiring pullups have them. > > -David > > "matteo" <matt.fisch...@gmail.com> wrote in message > > news:1170274492.883955.229870@v33g2000cwv.googlegroups.com... > > > I'm confused about how to configure the FPGA via the platform flash > > XCF32P Prom. I have a JTAG serial chain that goes > > > connector -> xcf32p -> xcf32p -> Virtex4 FX12 ----- > > > ^ | > > |_____________________________________| > > > The connector goes to my platform cable USB and I can successfully > > program the FPGA and each xcf32p in boundary scan mode. My question is > > how do I get one of the Proms to auto-configure the FPGA? The mode > > pins on the FPGA are unconnected, which in the documentation means > > that it's set to slave serial mode. I've tried taking the bit file for > > the FPGA and generating an MCS file for the PROM, then writing the MCS > > to the PROM (tried both external clock setting and use internal > > clock). I expect the PROM to magically find the FX12 in the chain and > > configure it. Is there another setting that I'm missing? > > > Thanks, > > MattArticle: 115145
> 7 ns, Commercial grade. > > Changing the "10C" to "7C" in the illustration to match your part would make > the following text applicable: and where did you get the 10C from, did I say I have 10C ?Article: 115146
On 2007-02-01, <carshie> <> wrote: >> 7 ns, Commercial grade. >> >> Changing the "10C" to "7C" in the illustration to match your part would > make >> the following text applicable: > > and where did you get the 10C from, did I say I have 10C ? No, master, sorry, master. What is your next request??? -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 115147
Maybe English is not your native language: The little word "and" at the beginning of the sentence changes a slightly pestering question to an obnoxious statement. If you are as ignorant in this technology as you seem to be, it would be wise to be more polite. Any answer you get here from anybody is because we want to be helpful. Keep that in mind! Peter Alfke On Jan 31, 4:52 pm, <carshie> wrote: > and where did you get the 10C from, did I say I have 10C ?Article: 115148
carshie wrote: >> 7 ns, Commercial grade. >> >> Changing the "10C" to "7C" in the illustration to match your part would > make >> the following text applicable: > > and where did you get the 10C from, did I say I have 10C ? From earlier, referring to the link http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=1067 >> Did you actually look at Solution2? >> > >> > You may not be using Virtex-4 but the rest of the lines appear verbatim >> > correct to your description. > > Well, if you believe that then you tell me, what is my propagation > delay time? I asked if you looked at Solution2 for that Answer record. By the "I couldn't find it no matter *how* hard I looked tone in your response, I figured you had trouble connecting simple images and phrases with the information being conveyed. I thought that if I cut & pasted the quotes for the 10C value USED IN THE ILLUSTRATION IN THE ANSWER RECORD that you would obviously get confused. So I requoted the text to show the "7C" you have on your part. I only mentioned the "10C" to avoid having you say that the text I quoted wasn't in the Answer record. Additionally, the xc9536 data sheet on page 7 http://direct.xilinx.com/bvdocs/publications/ds064.pdf shows the device marking explicitly calling out the "Speed" number. You appear to not bother 1) read the data sheet, 2) read the answer record that was provided to you as a link, and/or 3) prefer to have everything handed to you in such an outrageously clear fashion that a third generation tropical island castaway would understand what the marking on the device meant. We helped. You returned, helpless. You complained. Have you considered herb farming for a career?Article: 115149
Hi, Can anyone confirm if the plb_gemac_v1_01_a in SerDes/MGT mode is supported on the V4-FX family? The datasheet (DS460) and MPD file for the core state only V2-Pro, however XAPP809 updated October last year mentions both V2-Pro and V4-FX. The reference design with this XAPP is for V2-Pro on ML300 however. V2-Pro MGTs used refclk, refclk2, brefclk and brefclk2, while V4-FX uses refclk1, refclk2 and grefclk. It seems unlikely that the gemac core would work with V4-FX without explicit support. The VHDL is encrypted so I can't just go in and look. Thanks, John
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