Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
hi i dont know how to make a top module and create instances of other modules in it. my top module is CHK and other modules are BUFFER1, BUFFER2 and BUFFER3. now i want to create their instances in my top module, moreover i want to know what will be the format of the top module, as in what inputs and outputs will i declare in it, (i/os of all the 3 modules or wat?) this is my buffer1 module: module buffer1(clk,a,led1,led2,sum,sum1,buff1a,buff1b); input clk; input a; output led1; output led2; output [19:0] sum; output [15:0] sum1; output [127:0] buff1a; output [127:0] buff1b; parameter num1 = 15'hFFFF; reg led1; reg led2; reg [19:0] sum; reg [15:0] sum1; reg [127:0] buff1a; reg [127:0] buff1b; always @(clk) begin if(a==1) begin buff1a = 127'hcda9005095209e7d0de2686650101032; buff1b= 127'h1a6f0000c0a806f3453f602800060014;//correct packet sum= (buff1a[3:0]+buff1a[7:4]+buff1a[11:8]+buff1a[15:12]+buff1a[19:16]+buff1a[23:20]+buff1a[27:24]+buff1a[31:28]+buff1a[35:32]+buff1a[39:36]+buff1a[43:40]+buff1a[47:44]+buff1a[51:48]+buff1a[55:52]+buff1a[59:56]+buff1a[63:60]+buff1a[67:64]+buff1a[71:68]+buff1a[75:72] +buff1a[79:76]+buff1a[83:80]+buff1a[87:84]+buff1a[91:88]+buff1a[95:92]+buff1a[99:96]+buff1a[103:100]+buff1a[107:104]+buff1a[111:108]+buff1a[115:112]+buff1a[119:116]+buff1a[123:120]+buff1a[127:124]+buff1b[3:0]+buff1b[7:4]+buff1b[11:8]+buff1b[15:12]+buff1b[19:16]+buff1b[23:20]+buff1b[27:24]+buff1b[31:28]+buff1b[35:32]+buff1b[39:36]+buff1b[43:40]+buff1b[47:44]+buff1b[51:48]+buff1b[55:52]+buff1b[59:56]+buff1b[63:60]+buff1b[67:64]+buff1b[71:68]+buff1b[75:72] +buff1b[79:76]+buff1b[83:80]+buff1b[87:84]+buff1b[91:88]+buff1b[95:92]+buff1b[99:96]+buff1b[103:100]+buff1b[107:104]+buff1b[111:108]+buff1b[115:112]+buff1b[119:116]+buff1b[123:120]+buff1b[127:124]); sum1= (sum[15:0]+sum[19:16]); if(sum1==num1) begin led1=1; end else led2=1; end this is buffer2: module buffer2(clk,b,led1,led2,sum,sum1,buff1a,buff1b); input clk; input b; output led1; output led2; output [19:0] sum; output [15:0] sum1; output [127:0] buff2a; output [127:0] buff2b; parameter num1 = 15'hFFFF; reg led1; reg led2; reg [19:0] sum; reg [15:0] sum1; reg [127:0] buff2a; reg [127:0] buff2b; always @(clk) begin if(b==1) begin //buff2 = 255'hcda9005095209e7d0de26866501010321a7f0000c0a806f3453f602800060014;// incorrect buff2a= 127'hcda9005095209e7d0de2686650101032; buff2b= 127'h1a7f0000c0a806f3453f602800060014; sum= (buff2a[3:0]+buff2a[7:4]+buff2a[11:8]+buff2a[15:12]+buff2a[19:16]+buff2a[23:20]+buff2a[27:24]+buff2a[31:28]+buff2a[35:32]+buff2a[39:36]+buff2a[43:40]+buff2a[47:44]+buff2a[51:48]+buff2a[55:52]+buff2a[59:56]+buff2a[63:60]+buff2a[67:64]+buff2a[71:68]+buff2a[75:72] +buff2a[79:76]+buff2a[83:80]+buff2a[87:84]+buff2a[91:88]+buff2a[95:92]+buff2a[99:96]+buff2a[103:100]+buff2a[107:104]+buff2a[111:108]+buff2a[115:112]+buff2a[119:116]+buff2a[123:120]+buff2a[127:124]+buff2b[3:0]+buff2b[7:4]+buff2b[11:8]+buff2b[15:12]+buff2b[19:16]+buff2b[23:20]+buff2b[27:24]+buff2b[31:28]+buff2b[35:32]+buff2b[39:36]+buff2b[43:40]+buff2b[47:44]+buff2b[51:48]+buff2b[55:52]+buff2b[59:56]+buff2b[63:60]+buff2b[67:64]+buff2b[71:68]+buff2b[75:72] +buff2b[79:76]+buff2b[83:80]+buff2b[87:84]+buff2b[91:88]+buff2b[95:92]+buff2b[99:96]+buff2b[103:100]+buff2b[107:104]+buff2b[111:108]+buff2b[115:112]+buff2b[119:116]+buff2b[123:120]+buff2b[127:124]); sum1= (sum[15:0]+sum[19:16]); if(sum1==num1) begin led1=1; end else led2=1; end endmodule this is buffer3 module: module buffer3(clk,c,led1,led2,sum,sum1,buff3a,buff3b); input clk; input c; output led1; output led2; output [19:0] sum; output [15:0] sum1; output [127:0] buff3a; output [127:0] buff3b; parameter num1 = 15'hFFFF; reg led1; reg led2; reg [19:0] sum; reg [15:0] sum1; reg [127:0] buff3a; reg [127:0] buff3b; always @(clk) begin if(c==1) begin buff3a = 127'h0050cda90de2b8b695209e7e5010005c; //correct buff3b =127'h2a440000453fb028c0a806f300060014; sum= (buff3a[3:0]+buff3a[7:4]+buff3a[11:8]+buff3a[15:12]+buff3a[19:16]+buff3a[23:20]+buff3a[27:24]+buff3a[31:28]+buff3a[35:32]+buff3a[39:36]+buff3a[43:40]+buff3a[47:44]+buff3a[51:48]+buff3a[55:52]+buff3a[59:56]+buff3a[63:60]+buff3a[67:64]+buff3a[71:68]+buff3a[75:72] +buff3a[79:76]+buff3a[83:80]+buff3a[87:84]+buff3a[91:88]+buff3a[95:92]+buff3a[99:96]+buff3a[103:100]+buff3a[107:104]+buff3a[111:108]+buff3a[115:112]+buff3a[119:116]+buff3a[123:120]+buff3a[127:124]+buff3b[3:0]+buff3b[7:4]+buff3b[11:8]+buff3b[15:12]+buff3b[19:16]+buff3b[23:20]+buff3b[27:24]+buff3b[31:28]+buff3b[35:32]+buff3b[39:36]+buff3b[43:40]+buff3b[47:44]+buff3b[51:48]+buff3b[55:52]+buff3b[59:56]+buff3b[63:60]+buff3b[67:64]+buff3b[71:68]+buff3b[75:72] +buff3b[79:76]+buff3b[83:80]+buff3b[87:84]+buff3b[91:88]+buff3b[95:92]+buff3b[99:96]+buff3b[103:100]+buff3b[107:104]+buff3b[111:108]+buff3b[115:112]+buff3b[119:116]+buff3b[123:120]+buff3b[127:124]); sum1= (sum[15:0]+sum[19:16]); if(sum1==num1) begin led1=1; end else led2=1; end endmodule now i just want to create the instances in the top module thats it so what would be the code like? module chk() i want to know the syntax n all endmodule thanksArticle: 133926
On Jul 19, 10:33 am, Subroto Datta <sda...@altera.com> wrote: > > Quartus tries to move a lot > > of small shiftregisters (32-bit x 4) into M4Ks, which is a not the > > best use of my embedded memories... > in the dialog t a set of Maximum Setting entries which look like > Maximm Number of M512 memory blocks. Set it to 0 or any non zero > number other than -1 (which is default). M512's or M4k's? Or to make it use M512's instead of M4k's?Article: 133927
On Sat, 19 Jul 2008 08:48:42 -0700 (PDT), Ambreen Ashfaq Afridi <amboafridi@gmail.com> wrote: >hi >i dont know how to make a top module and create instances of other >modules in it. > >my top module is CHK >and other modules are BUFFER1, BUFFER2 and BUFFER3. > >now i want to create their instances in my top module, moreover i want >to know what will be the format of the top module, as in what inputs >and outputs will i declare in it, (i/os of all the 3 modules or wat?) > >this is my buffer1 module: > > > >module buffer1(clk,a,led1,led2,sum,sum1,buff1a,buff1b); > >input clk; >input a; > >output led1; >output led2; >output [19:0] sum; >output [15:0] sum1; >output [127:0] buff1a; >output [127:0] buff1b; > This is quite easy. Port connections are similar to wires which means you have declare busses of the same width at the higher level and connect them to your ports. For inputs (to lower level modules) the wires should be coming from inputs directly or from drivers at the same level ie: module CHK(input tclk, input ta, output tled, output [19:0] tsum, ...); wire [19:0] tsum = ta ? sum1 : sum2; wiire [19:0] sum1; wire tled = ta ? led11 : led21; buffer1 ubuf1(.clk(tclk), .a(ta), .led1(led11), .sum(sum1),...); buffer2 ubuf2(.clk(tclk), .a(ta), .led1(tled21), .sum(sum2),...); endmoduleArticle: 133928
Hi All, A new version of the TimingAnalyzer, beta 0.87, is now available. The following improvements and changes are new since the last version. 1) Changed the user interface to be more windows like. Click to select objects. Hold Ctrl key down and click to select multiple objects. Click in empty area to deselect all the select objects. 2) Drag the mouse anytime draws a select rectangle to select objects. Previously, you needed to hold down the alt and drag 3) Fixed saving images to selected directory in file chooser dialog. 4) Changed all DTT object references to PulseWidthLabel objects. 5) Fixed all commands that move edges do not move DigitalClocks edges now. 6) Changed Ctrl Up key combination to Alt Up when moving delay, constraint, and PulseWidthLabels up in the diagram. Ctrl Up is used by the JTabbedPane so users can hit Ctrl up and left and right to select a diagram in other tab panes. 7) Save as dialog does not display when just saving (Ctrl-S). When exiting the application, the save as dialog displays for each file that has been modified by not saved. 8) Fixed file needs to be saved when selecting or deselecting objects. 9) Standard Edition Features enabled until 9/13/08 for trail and testing. All beta versions will have the SE features enabled until the final release. 10) Working SE Features currently include savings images in other formats such as eps, pdf, svg, png, and gif, and also the scripting interface. You can download and use it at: www.timing-diagrams.comArticle: 133929
cs_posting@hotmail.com wrote:
> M512's or M4k's? Or to make it use M512's instead of M4k's?
There are separate settings for both, and -1 means unlimited.
But I don't think this will help.
The OP said
> The fitter dies with a message about the design not fitting
> into the device.
> I am using Quartus Webpack version 8.0, build 231 07/10/2008
I expect that quartus was out of LEs
on the specified device,
and the excess shifters did
not match the available blockram.
The quickest way to test this theory
is to spec a larger device.
If this fails I would either break up the design,
revert to version 7.2, or open a case with Altera.
-- Mike Treseler
Article: 133930On Jul 19, 2:11 pm, timinganalyzer <timinganaly...@gmail.com> wrote: > Hi All, > > A new version of the TimingAnalyzer, beta 0.87, is now available. > The following improvements and changes are new since the last version. ...snip... Could I suggest that you add a forum to your web site and announce your product releases there? That is what most projects like yours do. Announcing it in multiple newsgroups is really no different from other spam. How about you give it a rest? Besides, I think you are over estimating the demand for your product. I have only seen a small indication of any interest in this product. If it is any good and there is a need, customers will find you by word of mouth. RickArticle: 133931
On Jul 19, 3:11 pm, rickman <gnu...@gmail.com> wrote: > On Jul 19, 2:11 pm, timinganalyzer <timinganaly...@gmail.com> wrote:> Hi All, > > > A new version of the TimingAnalyzer, beta 0.87, is now available. > > The following improvements and changes are new since the last version. > > ...snip... > > Could I suggest that you add a forum to your web site and announce > your product releases there? That is what most projects like yours > do. Announcing it in multiple newsgroups is really no different from > other spam. > > How about you give it a rest? Besides, I think you are over > estimating the demand for your product. I have only seen a small > indication of any interest in this product. If it is any good and > there is a need, customers will find you by word of mouth. > > Rick Hello Rick, I didn't think it would considered spam if it's related to the subject of the newsgroup but I guess you have a good point. I won't announce updates to the program on the newsgroups anymore. You might be right about the interest level as well. Time will tell. There seems to more interest with ASIC and VLSI design engineers needing ways to document complex interface timing diagrams and generating test vectors. That was why I decided to develop the program in the first place. -Dan -DanArticle: 133932
timinganalyzer wrote:
> rickman <gnu...@gmail.com> wrote:
>> timinganalyzer <timinganaly...@gmail.com> wrote:> Hi All,
>>
>>> A new version of the TimingAnalyzer, beta 0.87, is now
>>> available. The following improvements and changes are new since
>>< the last version.
>>
>> ...snip...
>>
>> Could I suggest that you add a forum to your web site and
>> announce your product releases there? That is what most projects
>> like yours do. Announcing it in multiple newsgroups is really no
>> different from other spam.
>
... snip ...
>
> I didn't think it would considered spam if it's related to the
> subject of the newsgroup but I guess you have a good point. I
> won't announce updates to the program on the newsgroups anymore.
>
> You might be right about the interest level as well. Time will
> tell. There seems to more interest with ASIC and VLSI design
> engineers needing ways to document complex interface timing
> diagrams and generating test vectors. That was why I decided to
> develop the program in the first place.
I don't consider it spam. It is available, free, and pertinent.
Without this sort of announcement interested users will never know
it exists.
--
[mail]: Chuck F (cbfalconer at maineline dot net)
[page]: <http://cbfalconer.home.att.net>
Try the download section.
Article: 133933CBFalconer wrote: > timinganalyzer wrote: >> rickman <gnu...@gmail.com> wrote: >>> timinganalyzer <timinganaly...@gmail.com> wrote:> Hi All, >>> >>>> A new version of the TimingAnalyzer, beta 0.87, is now >>>> available. The following improvements and changes are new since >>> < the last version. >>> >>> ...snip... >>> >>> Could I suggest that you add a forum to your web site and >>> announce your product releases there? That is what most projects >>> like yours do. Announcing it in multiple newsgroups is really no >>> different from other spam. > ... snip ... >> I didn't think it would considered spam if it's related to the >> subject of the newsgroup but I guess you have a good point. I >> won't announce updates to the program on the newsgroups anymore. >> >> You might be right about the interest level as well. Time will >> tell. There seems to more interest with ASIC and VLSI design >> engineers needing ways to document complex interface timing >> diagrams and generating test vectors. That was why I decided to >> develop the program in the first place. > > I don't consider it spam. It is available, free, and pertinent. > Without this sort of announcement interested users will never know > it exists. I don't consider it spam either. Instead of a complete accounting of new features, Rickman might be happier with a brief announcement that alerts the reader to new material on the website. Personally, I don't care. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 133934
On Jul 19, 7:37 pm, Jerry Avins <j...@ieee.org> wrote: > CBFalconer wrote: > > timinganalyzer wrote: > >> rickman <gnu...@gmail.com> wrote: > >>> timinganalyzer <timinganaly...@gmail.com> wrote:> Hi All, > > >>>> A new version of the TimingAnalyzer, beta 0.87, is now > >>>> available. The following improvements and changes are new since > >>> < the last version. > > >>> ...snip... > > >>> Could I suggest that you add a forum to your web site and > >>> announce your product releases there? That is what most projects > >>> like yours do. Announcing it in multiple newsgroups is really no > >>> different from other spam. > > ... snip ... > >> I didn't think it would considered spam if it's related to the > >> subject of the newsgroup but I guess you have a good point. I > >> won't announce updates to the program on the newsgroups anymore. > > >> You might be right about the interest level as well. Time will > >> tell. There seems to more interest with ASIC and VLSI design > >> engineers needing ways to document complex interface timing > >> diagrams and generating test vectors. That was why I decided to > >> develop the program in the first place. > > > I don't consider it spam. It is available, free, and pertinent. > > Without this sort of announcement interested users will never know > > it exists. > > I don't consider it spam either. Instead of a complete accounting of new > features, Rickman might be happier with a brief announcement that alerts > the reader to new material on the website. Personally, I don't care. Are you and CBF OK with *any* vendor of hardware, software, tools, components, boards or materials related to embedded, FPGA, DSP or VHDL/ Verilog posting here to advertise their products? The fact that this software offers a free version with limited features does not make it unique. There are any number of software vendors that do the same thing. Many component manufacturers offer free samples. Even makers of tools, boards, systems and test equipment will let you use their products for evaluation. Is there something special about this vendor and his product? Personally I feel that his posts are not on topic. Selling and marketing is not the topic of any of these groups. RickArticle: 133935
On Jul 19, 2:57 am, Antti <Antti.Luk...@googlemail.com> wrote: > On 19 juuli, 06:07, rickman <gnu...@gmail.com> wrote: > > > > > I may need to add a CPU to a design I am doing. I had rolled my own > > core once with a 16 bit data path and it worked out fairly well. But > > it was 600 LUT/FFs and I would like to use something smaller if > > possible. The target is a Lattice XP3 with about 3100 LUT/FFs and > > about 2000 are currently used. I believe that once I add the CPU > > core, I can take out a lot of the logic since it runs so slowly. The > > fastest parallel data rate is 8 kHz with some at 1 kHz and the rest at > > 100 Hz. I probably would have used a CPU to start with instead of the > > FPGA, but there was a possible need to handle higher speed signals > > which seems to have gone away. > > > I recall that someone had started a thread about serial > > implementations of processors that were supported by a C compiler. I > > don't think any ever turned up. But the OP had some other > > requirements that may have excluded a few very small designs. Are > > there any CPU cores, serial or parallel, that are significantly > > smaller than 600 LUT/FFs? The Lattice part has LUT memory even dual > > port, so that is not a constraint, the LUTs can be used for > > registers. > > > Rick > > im OP > > hi I may have different interests, yes smallest nonserialized CPU > as for your current task is one of the wishes, and here also there > is no one definitive winner > > pico paco blazes and mico8 are out of the question, most others > are too large > > i have used cut AVR core in XP3 but i dont recall the lut count Have you tabulated your findings anywhere? The last time I did a survey of ARM7 processors, I put it all into a spread sheet and posted it on the web. I think it was useful for a while, but the market overtook it and I couldn't keep up! I read your thread about the serial processor and it was interesting. I think my project actually has the time to use such a processor, but I think you never found one that met your requirements. I am not looking for a large address space, but I would like for it to be able to read data from an SD card. My design uses FPGAs both on the application board and the test fixture. Ultimately I want the test fixture to be able to read a programming file from an SD card and configure the target FGPA without a programming cable. Of all the suggestions, so far the PIC sounds like the best one. I couldn't find a C compiler for the picoblaze or the pacoblaze. There is mention of someone creating one, but the web site is no longer accessible. RickArticle: 133936
On Jul 19, 12:23 am, John McCaskill <jhmccask...@gmail.com> wrote: > On Jul 18, 11:09 pm, John McCaskill <jhmccask...@gmail.com> wrote: > > > > > The Xilinx PicoBlaze is less than 100 LUTs plus one block ram. > > That should be less than 100 slices. Still, that's 200 LUTs which is very small. But I can't find a C compiler for it. RickArticle: 133937
rickman wrote: > On Jul 19, 7:37 pm, Jerry Avins <j...@ieee.org> wrote: >> CBFalconer wrote: >>> timinganalyzer wrote: >>>> rickman <gnu...@gmail.com> wrote: >>>>> timinganalyzer <timinganaly...@gmail.com> wrote:> Hi All, >>>>>> A new version of the TimingAnalyzer, beta 0.87, is now >>>>>> available. The following improvements and changes are new since >>>>> < the last version. >>>>> ...snip... >>>>> Could I suggest that you add a forum to your web site and >>>>> announce your product releases there? That is what most projects >>>>> like yours do. Announcing it in multiple newsgroups is really no >>>>> different from other spam. >>> ... snip ... >>>> I didn't think it would considered spam if it's related to the >>>> subject of the newsgroup but I guess you have a good point. I >>>> won't announce updates to the program on the newsgroups anymore. >>>> You might be right about the interest level as well. Time will >>>> tell. There seems to more interest with ASIC and VLSI design >>>> engineers needing ways to document complex interface timing >>>> diagrams and generating test vectors. That was why I decided to >>>> develop the program in the first place. >>> I don't consider it spam. It is available, free, and pertinent. >>> Without this sort of announcement interested users will never know >>> it exists. >> I don't consider it spam either. Instead of a complete accounting of new >> features, Rickman might be happier with a brief announcement that alerts >> the reader to new material on the website. Personally, I don't care. > > Are you and CBF OK with *any* vendor of hardware, software, tools, > components, boards or materials related to embedded, FPGA, DSP or VHDL/ > Verilog posting here to advertise their products? The fact that this > software offers a free version with limited features does not make it > unique. There are any number of software vendors that do the same > thing. Many component manufacturers offer free samples. Even makers > of tools, boards, systems and test equipment will let you use their > products for evaluation. > > Is there something special about this vendor and his product? > > Personally I feel that his posts are not on topic. Selling and > marketing is not the topic of any of these groups. There is something special about this vendor, if not his product. He has made something on his own that he hopes is useful, and has no budget to make it known. He came to us initially for advice, which he heeded despite the criticism that was unfortunately necessary. If nothing else, I'm happy to give him a bye. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 133938
rickman wrote:
> Jerry Avins <j...@ieee.org> wrote:
>> CBFalconer wrote:
>>
... snip ...
>>
>>> I don't consider it spam. It is available, free, and pertinent.
>>> Without this sort of announcement interested users will never
>>> know it exists.
>>
>> I don't consider it spam either. Instead of a complete accounting
>> of new features, Rickman might be happier with a brief
>> announcement that alerts the reader to new material on the
>> website. Personally, I don't care.
>
> Are you and CBF OK with *any* vendor of hardware, software, tools,
> components, boards or materials related to embedded, FPGA, DSP or
> VHDL/ Verilog posting here to advertise their products? The fact
> that this software offers a free version with limited features
> does not make it unique. There are any number of software vendors
> that do the same thing. Many component manufacturers offer free
> samples. Even makers of tools, boards, systems and test equipment
> will let you use their products for evaluation.
>
> Is there something special about this vendor and his product?
>
> Personally I feel that his posts are not on topic. Selling and
> marketing is not the topic of any of these groups.
As far as I can tell the source is available, and there is no
long-term commercial interest. This puts it in the same
classification as Linux. He is not selling - he is offering.
--
[mail]: Chuck F (cbfalconer at maineline dot net)
[page]: <http://cbfalconer.home.att.net>
Try the download section.
Article: 133939On 20 juuli, 06:58, rickman <gnu...@gmail.com> wrote: > On Jul 19, 2:57 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 19 juuli, 06:07, rickman <gnu...@gmail.com> wrote: > > > > I may need to add a CPU to a design I am doing. =A0I had rolled my ow= n > > > core once with a 16 bit data path and it worked out fairly well. =A0B= ut > > > it was 600 LUT/FFs and I would like to use something smaller if > > > possible. =A0The target is a Lattice XP3 with about 3100 LUT/FFs and > > > about 2000 are currently used. =A0I believe that once I add the CPU > > > core, I can take out a lot of the logic since it runs so slowly. =A0T= he > > > fastest parallel data rate is 8 kHz with some at 1 kHz and the rest a= t > > > 100 Hz. =A0I probably would have used a CPU to start with instead of = the > > > FPGA, but there was a possible need to handle higher speed signals > > > which seems to have gone away. > > > > I recall that someone had started a thread about serial > > > implementations of processors that were supported by a C compiler. = =A0I > > > don't think any ever turned up. =A0But the OP had some other > > > requirements that may have excluded a few very small designs. =A0Are > > > there any CPU cores, serial or parallel, that are significantly > > > smaller than 600 LUT/FFs? =A0The Lattice part has LUT memory even dua= l > > > port, so that is not a constraint, the LUTs can be used for > > > registers. > > > > Rick > > > im OP > > > hi I may have different interests, yes smallest nonserialized CPU > > as for your current task is one of the wishes, and here also there > > is no one definitive winner > > > pico paco blazes and mico8 are out of the question, most others > > are too large > > > i have used cut AVR core in XP3 but i dont recall the lut count > > Have you tabulated your findings anywhere? =A0The last time I did a > survey of ARM7 processors, I put it all into a spread sheet and posted > it on the web. =A0I think it was useful for a while, but the market > overtook it and I couldn't keep up! > > I read your thread about the serial processor and it was interesting. > I think my project actually has the time to use such a processor, but > I think you never found one that met your requirements. > > I am not looking for a large address space, but I would like for it to > be able to read data from an SD card. =A0My design uses FPGAs both on > the application board and the test fixture. =A0Ultimately I want the > test fixture to be able to read a programming file from an SD card and > configure the target FGPA without a programming cable. > > Of all the suggestions, so far the PIC sounds like the best one. =A0I > couldn't find a C compiler for the picoblaze or the pacoblaze. =A0There > is mention of someone creating one, but the web site is no longer > accessible. > > Rick Hi Rick here is reply to your post :) http://antti-lukats.blogspot.com/2008/07/rules-of-life.html in short i am doing almost the same as you intend to at the moment AnttiArticle: 133940
CBFalconer <cbfalconer@yahoo.com> writes: > rickman wrote: >> Jerry Avins <j...@ieee.org> wrote: >>> CBFalconer wrote: >>> > ... snip ... >>> >>>> I don't consider it spam. It is available, free, and pertinent. >>>> Without this sort of announcement interested users will never >>>> know it exists. >>> >>> I don't consider it spam either. Instead of a complete accounting >>> of new features, Rickman might be happier with a brief >>> announcement that alerts the reader to new material on the >>> website. Personally, I don't care. >> >> Are you and CBF OK with *any* vendor of hardware, software, tools, >> components, boards or materials related to embedded, FPGA, DSP or >> VHDL/ Verilog posting here to advertise their products? The fact >> that this software offers a free version with limited features >> does not make it unique. There are any number of software vendors >> that do the same thing. Many component manufacturers offer free >> samples. Even makers of tools, boards, systems and test equipment >> will let you use their products for evaluation. >> >> Is there something special about this vendor and his product? >> >> Personally I feel that his posts are not on topic. Selling and >> marketing is not the topic of any of these groups. > > As far as I can tell the source is available, But you are not allowed to look at it <http://www.timing-diagrams.com/license.html> "You may not modify, reverse engineer, decompile, or disassemble the TimingAnalyzer program." > and there is no long-term commercial interest. This puts it in the > same classification as Linux. He is not selling - he is offering. ..."You must buy a license to use TimingAnalyzer Standard Edition(SE)"... It appears to be a commercial program, free for personal, non-commercial use only. So I agree with rickman. -- John DevereuxArticle: 133941
> > Of all the suggestions, so far the PIC sounds like the best one. I > couldn't find a Ccompilerfor thepicoblazeor the pacoblaze. There > is mention of someone creating one, but the web site is no longer > accessible. > > Rick You can find a download link here : http://www.asm.ro/fpga/ Disclaimer : I never used it myself JosepArticle: 133942
On Sun, 20 Jul 2008 00:03:58 -0400, Jerry Avins <jya@ieee.org> wrote: >rickman wrote: >> Are you and CBF OK with *any* vendor of hardware, software, tools, >> components, boards or materials related to embedded, FPGA, DSP or VHDL/ >> Verilog posting here to advertise their products? A salient difference is that the posts were not simply (or even mostly) advertising but rather were part of a conversation about the features, operation, and behaviors of a useful tool that was under development. Boy, it sure would suck if the product development engineers from Xilinx or Atmel or whatever would hang around here and do that, eh? >> The fact that this >> software offers a free version with limited features does not make it >> unique. There are any number of software vendors that do the same >> thing. Many component manufacturers offer free samples. Even makers >> of tools, boards, systems and test equipment will let you use their >> products for evaluation. >> >> Is there something special about this vendor and his product? Other than soliciting and responding to community feedback? >> Personally I feel that his posts are not on topic. Selling and >> marketing is not the topic of any of these groups. Personally, I feel that the joker who keeps littering the groups with "Spam" posts is more of a menace. >There is something special about this vendor, if not his product. He has >made something on his own that he hopes is useful, and has no budget to >make it known. He came to us initially for advice, which he heeded >despite the criticism that was unfortunately necessary. If nothing else, >I'm happy to give him a bye. Indeed. -- Rich Webb Norfolk, VAArticle: 133943
On 19.7.2008 6:07, rickman wrote:
> I may need to add a CPU to a design I am doing. I had rolled my own
> core once with a 16 bit data path and it worked out fairly well. But
> it was 600 LUT/FFs and I would like to use something smaller if
> possible. The target is a Lattice XP3 with about 3100 LUT/FFs and
> about 2000 are currently used. I believe that once I add the CPU
> core, I can take out a lot of the logic since it runs so slowly. The
> fastest parallel data rate is 8 kHz with some at 1 kHz and the rest at
> 100 Hz. I probably would have used a CPU to start with instead of the
> FPGA, but there was a possible need to handle higher speed signals
> which seems to have gone away.
>
> I recall that someone had started a thread about serial
> implementations of processors that were supported by a C compiler. I
> don't think any ever turned up. But the OP had some other
> requirements that may have excluded a few very small designs. Are
> there any CPU cores, serial or parallel, that are significantly
> smaller than 600 LUT/FFs? The Lattice part has LUT memory even dual
> port, so that is not a constraint, the LUTs can be used for
> registers.
>
> Rick
Maybe something worth checking:
http://www.zylin.com/zpu.htm
From the above website:
1. The ZPU is now open source. See ZPU mailing list for more details.
2. BSD license for HDL implementations--no hiccups when using in
proprietary commercial products. Under the open source royalty free
license, there are no limits on what type of technology (FPGA,
anti-fuse, or ASIC) in which the ZPU can be implemented.
3. GPL license for architecture, documentation and tools
4. Completely FPGA brand and type neutral implementation
5. 298 LUT @ 125 MHz after P&R with 16 bit datapath and 4kBytes BRAM
6. 442 LUT @ 95 MHz after P&R with 32 bit datapath and 32kBytes BRAM
7. Codesize 80% of ARM thumb
8. Configurable 16/32 bit datapath
9. GCC toolchain(GDB, newlib, libstdc++)
10. Debugging via simulator or GDB stubs
11. HDL simulation feedback to simulator for powerful profiling
capabilities
12. Eclipse ZPU plug-in
13. eCos embedded operating system support.
Henri
Article: 133944On 20 juuli, 15:21, Henri <h...@s.fi> wrote: > On 19.7.2008 6:07, rickman wrote: > > > > > I may need to add a CPU to a design I am doing. =A0I had rolled my own > > core once with a 16 bit data path and it worked out fairly well. =A0But > > it was 600 LUT/FFs and I would like to use something smaller if > > possible. =A0The target is a Lattice XP3 with about 3100 LUT/FFs and > > about 2000 are currently used. =A0I believe that once I add the CPU > > core, I can take out a lot of the logic since it runs so slowly. =A0The > > fastest parallel data rate is 8 kHz with some at 1 kHz and the rest at > > 100 Hz. =A0I probably would have used a CPU to start with instead of th= e > > FPGA, but there was a possible need to handle higher speed signals > > which seems to have gone away. > > > I recall that someone had started a thread about serial > > implementations of processors that were supported by a C compiler. =A0I > > don't think any ever turned up. =A0But the OP had some other > > requirements that may have excluded a few very small designs. =A0Are > > there any CPU cores, serial or parallel, that are significantly > > smaller than 600 LUT/FFs? =A0The Lattice part has LUT memory even dual > > port, so that is not a constraint, the LUTs can be used for > > registers. > > > Rick > > Maybe something worth checking: > > http://www.zylin.com/zpu.htm > > =A0From the above website: > > =A0 =A0 1. =A0 The ZPU is now open source. See ZPU mailing list for more = details. > =A0 =A0 2. BSD license for HDL implementations--no hiccups when using in > proprietary commercial products. Under the open source royalty free > license, there are no limits on what type of technology (FPGA, > anti-fuse, or ASIC) in which the ZPU can be implemented. > =A0 =A0 3. GPL license for architecture, documentation and tools > =A0 =A0 4. Completely FPGA brand and type neutral implementation > =A0 =A0 5. 298 LUT @ 125 MHz after P&R with 16 bit datapath and 4kBytes B= RAM > =A0 =A0 6. 442 LUT @ 95 MHz after P&R with 32 bit datapath and 32kBytes B= RAM > =A0 =A0 7. Codesize 80% of ARM thumb > =A0 =A0 8. Configurable 16/32 bit datapath > =A0 =A0 9. GCC toolchain(GDB, newlib, libstdc++) > =A0 =A010. Debugging via simulator or GDB stubs > =A0 =A011. HDL simulation feedback to simulator for powerful profiling > capabilities > =A0 =A012. Eclipse ZPU plug-in > =A0 =A013. eCos embedded operating system support. > > Henri eh this is still on my MUST evaluate plan :) 80% of THUMB? that nice also, i just made my first THUMB assembly program Atmel dataflash bootstrap loader, its about 60 bytes of code (thumb) would be fun to compare if that optimized to max thumb code still compacts on zpu :) my code is really funky it loads 1 32 bit constant and constructs all other constants, also uses lower port of io address as mask constant, etc.. AnttiArticle: 133945
On Jul 20, 1:06 am, CBFalconer <cbfalco...@yahoo.com> wrote: > > As far as I can tell the source is available, and there is no > long-term commercial interest. This puts it in the same > classification as Linux. He is not selling - he is offering. Did you actually look at his web page? There is nothing "open" about this program and the only "free" is the limited capability version licensed only for "personal or academic use", not commercial. http://www.timing-diagrams.com/license.html In particular, "You must buy a license to use TimingAnalyzer Standard Edition(SE)" and "You may not modify, reverse engineer, decompile, or disassemble the TimingAnalyzer program." I'm not trying to bust anyone's balls. But this guy has been cluttering up a number of newsgroups, Yahoo groups and who knows where else with his frequent postings. I don't object to his making it known that there is a new product on the market. I get tired of seeing his, sometimes bi-weekly, announcements that a new version is out there. If anyone is looking for a timing analyzer then he will already be easy to find. If anyone wants to know the current status of his program he has a web site. I just think that a lot of people, here and elsewhere, don't so much "think" about a topic like this, they justify what they "feel". How would people "feel" if every vendor came here to advertise, announce new products, new features or even just to solicit comments and advice? I remember awhile back there were some job postings and it was rather contentious whether that was considered acceptable. For the most part people had no logical justification for wanting to allow that sort of post. They just tried to rationalize their feelings, "if you were out of work, you would welcome those posts" sort of thing. Well my feelings are that I get tired of seeing advertising in this group and elsewhere. I moderate multiple Yahoo groups and have made a real effort to exclude the spam. Don't you think these groups would be better served with less spam? RickArticle: 133946
On Jul 20, 8:21 am, Henri <h...@s.fi> wrote: > On 19.7.2008 6:07, rickman wrote: > > > > > I may need to add a CPU to a design I am doing. I had rolled my own > > core once with a 16 bit data path and it worked out fairly well. But > > it was 600 LUT/FFs and I would like to use something smaller if > > possible. The target is a Lattice XP3 with about 3100 LUT/FFs and > > about 2000 are currently used. I believe that once I add the CPU > > core, I can take out a lot of the logic since it runs so slowly. The > > fastest parallel data rate is 8 kHz with some at 1 kHz and the rest at > > 100 Hz. I probably would have used a CPU to start with instead of the > > FPGA, but there was a possible need to handle higher speed signals > > which seems to have gone away. > > > I recall that someone had started a thread about serial > > implementations of processors that were supported by a C compiler. I > > don't think any ever turned up. But the OP had some other > > requirements that may have excluded a few very small designs. Are > > there any CPU cores, serial or parallel, that are significantly > > smaller than 600 LUT/FFs? The Lattice part has LUT memory even dual > > port, so that is not a constraint, the LUTs can be used for > > registers. > > > Rick > > Maybe something worth checking: > > http://www.zylin.com/zpu.htm > > From the above website: > > 1. The ZPU is now open source. See ZPU mailing list for more details. > 2. BSD license for HDL implementations--no hiccups when using in > proprietary commercial products. Under the open source royalty free > license, there are no limits on what type of technology (FPGA, > anti-fuse, or ASIC) in which the ZPU can be implemented. > 3. GPL license for architecture, documentation and tools > 4. Completely FPGA brand and type neutral implementation > 5. 298 LUT @ 125 MHz after P&R with 16 bit datapath and 4kBytes BRAM > 6. 442 LUT @ 95 MHz after P&R with 32 bit datapath and 32kBytes BRAM > 7. Codesize 80% of ARM thumb > 8. Configurable 16/32 bit datapath > 9. GCC toolchain(GDB, newlib, libstdc++) > 10. Debugging via simulator or GDB stubs > 11. HDL simulation feedback to simulator for powerful profiling > capabilities > 12. Eclipse ZPU plug-in > 13. eCos embedded operating system support. > > Henri I'm pretty impressed. Small, fast and with GCC support! RickArticle: 133947
Hi, I have to introduce a DVB Trasnport Stream (Clk + Data + Sync) from a tuner in a fpga. Fpga has a 27 MHz clock with which takes data from the tuner and serializes them to ASI. The serialization works well simulating a Null Packet as input. Now I have to take data from the tuner with unknown clock. I had thought of a async FIFO. The clock of the tuner to the left of fifo, to the right my clock. Checking the level of fifo and inserting Null packet if necessary. But how can clocking the fifo directly by the tuner without problems ? Do you have an example of VHDL code that I could use ? Thanks. Kappa.Article: 133948
rickman wrote:
> CBFalconer <cbfalco...@yahoo.com> wrote:
>
>> As far as I can tell the source is available, and there is no
>> long-term commercial interest. This puts it in the same
>> classification as Linux. He is not selling - he is offering.
>
> Did you actually look at his web page? There is nothing "open"
> about this program and the only "free" is the limited capability
> version licensed only for "personal or academic use", not
> commercial.
No, I admit I didn't. I have limited interest in such a utility.
--
[mail]: Chuck F (cbfalconer at maineline dot net)
[page]: <http://cbfalconer.home.att.net>
Try the download section.
Article: 133949On Jul 20, 9:14 am, rickman <gnu...@gmail.com> wrote: > On Jul 20, 1:06 am, CBFalconer <cbfalco...@yahoo.com> wrote: > > > > > As far as I can tell the source is available, and there is no > > long-term commercial interest. This puts it in the same > > classification as Linux. He is not selling - he is offering. > > Did you actually look at his web page? There is nothing "open" about > this program and the only "free" is the limited capability version > licensed only for "personal or academic use", not commercial. > > http://www.timing-diagrams.com/license.html > > In particular, > > "You must buy a license to use TimingAnalyzer Standard Edition(SE)" > > and > > "You may not modify, reverse engineer, decompile, or disassemble the > TimingAnalyzer program." > > I'm not trying to bust anyone's balls. But this guy has been > cluttering up a number of newsgroups, Yahoo groups and who knows where > else with his frequent postings. I don't object to his making it > known that there is a new product on the market. I get tired of > seeing his, sometimes bi-weekly, announcements that a new version is > out there. If anyone is looking for a timing analyzer then he will > already be easy to find. If anyone wants to know the current status > of his program he has a web site. > > I just think that a lot of people, here and elsewhere, don't so much > "think" about a topic like this, they justify what they "feel". How > would people "feel" if every vendor came here to advertise, announce > new products, new features or even just to solicit comments and > advice? I remember awhile back there were some job postings and it > was rather contentious whether that was considered acceptable. For > the most part people had no logical justification for wanting to allow > that sort of post. They just tried to rationalize their feelings, "if > you were out of work, you would welcome those posts" sort of > thing. > > Well my feelings are that I get tired of seeing advertising in this > group and elsewhere. I moderate multiple Yahoo groups and have made a > real effort to exclude the spam. Don't you think these groups would > be better served with less spam? > > Rick Hello All, I'm sorry to be the cause of this debate. Originally, my intentions were to find some beta testers to help me test the program and at the same time get some visibility to potential customers. Its hard to find experience engineers to help. I have been getting feedback from users of each beta version which has been helpful. rickman, Yes, I have made the announcement on other groups that I thought were relative to digital logic timing analysis and drawing timings. I am not just blindly sendiing frequent postings to any group that are not related. But, I will follow any newsgroup guidelines there are and will not clutter them will frequent announcements anymore if that is considered spam or not good practice. Regards, Dan
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z