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I've been working as a 'consultant' / sub contract engineer with a strong emphasis on FPGA work for about eight years now (after a previous eight stint as a permanent employee with a large Telco). I have come across a couple of odd customer style guide requirements which are... 1) Only one process per clock is allowed per entity (hello Nick). I never understood the thinking behind this. I normally structure my code the way I had partitioned a design, for example a process for low level control with a higher level 'protocol' process in an I2C interface. To me this makes the code easier to read/support but this can't be done with one process. 2) There must be no unconstarined paths in a design. This is madness and only causes problems with support. I was asked to modify a (large) design which I did, only then the P&R was failing. It was a module I hadn't worked on that had failed so I had to dig into the workings of that module to work out what was goign on. It turned out that a constraint of the previous results + 20% had been added, but this was a static area of the design that didn't need to be constrained. It lost me a day or two investigating. Anyone got any strong opinions, especially on 'one process', or come across other oddities? Nial.Article: 128876
Hi all, I have recently just generated HDL netlist from System Generator 9.1 and I have began assigning the pins in PACE for my design. Although I have assigned most pins as well as the clk, I have problem understanding how should I assign the last pin 'ce' which is the clock enable. Do I assign it as an IO pin or is there any constraint as to how to assign it? Thank you for any helpful comments .Article: 128877
http://www.fpga-faq.com/FPGA_Boards.shtmlArticle: 128878
Hi I put a timing constraint in the UCF File where i asked for a minimum frequency of 35 MHz (29 ns) but unfortuatenly XST tells me that the ratio was not met and the actual ratio is 38 ns. I have already optimized for speed, it there any way to tell the tool it should sythesis it for more than 35 MHz forgetting about any area constraints? Thanks!Article: 128879
On Feb 8, 9:25 am, "Symon" <symon_bre...@hotmail.com> wrote: > http://www.fpga-faq.com/FPGA_Boards.shtml Thanks , I did a quick research and couldn't find anything with the ADC and DAC I need. It looks like there aren't these kind of boards around. At least if I could get a footprint it would really help.Article: 128880
On Feb 8, 4:17=A0am, Tricky <Trickyh...@gmail.com> wrote: > > Using the math_real library can do for now. I have had a look at the > > sin and cos functions there. I am also aware on how to conver the real > > format to the format I want. I intend to generate a wave. sin and cos > > in math_real would just generate a value for a particular input. How > > can i generate a sine or cos waveform. I wish to make this function > > parametrized as follows (not sure if this should go into a function or > > process) > > Are you sure you want to go down this path? If you eventually need it > synthesizable, you will have to throw away ALL of the work you have > done with the math_real package, unless you're using it as a model of > the final block. > > The easiest way to implement sin and cosine in and FPGA is using a > look up table (normally a ROM), with the address formed from the angle > coefficient. I want to do a simulation only version right now (some requirements change on the fly :) ). The sin/cos wave has to be implemented in such a way that it can be used as an input to ant UUT. I am not yet sure if this would work by using a function. What other options do I have? I cannot use it as a component. I am making a library of functions so I want to make this as generic as possible. If i implement this using a process, where can this go in a package?Article: 128881
"Alfreeeeed" <Alfredo.Taddei@gmail.com> wrote in message news:0bbcc5a4-0aa4-46f4-96d4-0a4cc22d7129@s13g2000prd.googlegroups.com... > On Feb 8, 9:25 am, "Symon" <symon_bre...@hotmail.com> wrote: >> http://www.fpga-faq.com/FPGA_Boards.shtml > > Thanks , I did a quick research and couldn't find anything with the > ADC and DAC I need. It looks like there aren't these kind of boards > around. At least if I could get a footprint it would really help. Google:- DC890B site:linear.com From your original post, what do you mean by "-ADC <80Msps <10bit"? '<' means 'less than', right? Syms.Article: 128882
Peter Alfke wrote: > Your LUT-RAM-based very big RAM may have long routing delays. > If you believe in trying things out (instead of simulation), then reduce > the clock rate, and see whether that helps. > > In your place, I would still try to rearrange the logic, so as to live > with synchronous BlockRAMs. > Peter Alfke, Xilinx Thanks Peter, you saved my life ;). Reduce clock frequency and now it works which is great news. Anyway, as you suggested I will try and rearrange the logic to make it work with a synchronous BRam Thanks!Article: 128883
On Feb 8, 11:33 am, "Symon" <symon_bre...@hotmail.com> wrote: > "Alfreeeeed" <Alfredo.Tad...@gmail.com> wrote in message > > news:0bbcc5a4-0aa4-46f4-96d4-0a4cc22d7129@s13g2000prd.googlegroups.com... > > > On Feb 8, 9:25 am, "Symon" <symon_bre...@hotmail.com> wrote: > >>http://www.fpga-faq.com/FPGA_Boards.shtml > > > Thanks , I did a quick research and couldn't find anything with the > > ADC and DAC I need. It looks like there aren't these kind of boards > > around. At least if I could get a footprint it would really help. > > Google:- > DC890B site:linear.com > > From your original post, what do you mean by "-ADC <80Msps <10bit"? > '<' means 'less than', right? > Syms. Sorry , Syms I replied only to you. I need at least 80 Msps and 10 bit resolution. I apologize for the inconvenience. AlfredArticle: 128884
mmihai wrote: > On Feb 7, 3:19 pm, Michael Meeuwisse <mickeymeeuw@g_something> wrote: > > >>While debugging my xsvf parser for ft2232 jtag programmers I experience >>some really odd behavior; if I swapped my buffer and then send > > > Did you try xc3sprog? > No I haven't. I tried getting openOCD and UrJTAG but the first didn't even understand the XSVF files completely - and failed to even clock out the idcodes succesfully when it's done using an XSVF file. After a day of fighting with UrJTAG I gave up on that too, it didn't want to select my programmer and it's documentation on ft2232 support is well.. missing afaik. The reason I was asking here is only partly because I want to program the fpga, it's equally important to get the programmer to work. So suggesting a different programmer or piece of software isn't really helping. :) I'll see if I can get xc3sprog to work, if it's capable of programming the fpga at least I know the problem lies in the parser. However if somebody has the patience + windows/cygwin + an Amontec programmer + a xilinx dev board available please drop me a line Back to the XSVF, I did find the culprit in my rambling, the data from 2.xsvf; 40 00 80 06 75 7D 00 00 00000010 00000000 00000001 01100000 10101110 10111110 00000000 00000000 Compensate 1 bit x0000001 00000000 00000000 10110000 01010111 01011111 00000000 00000000 That's in fact correct, but what makes it look wrong is that I'm compensating the shift without first flipping the entire buffer. My code already did that and outputs; 00 00 7D 75 06 80 00 40 00000000 00000000 10111110 10101110 01100000 00000001 00000000 00000010 And if you compensate that 1 bit you get; x0000000 00000000 01011111 01010111 00110000 00000000 10000000 00000001 Which is exactly the same as the original rbt; 00000000 00000000 01011111 01010111 00110000 00000000 10000000 00000001 So iMPACT is right, my programmer is right, but it still doesn't work, which kicks me back to square 1. The status register of the xc3s400 after programming it with above (probably correct) sequence is; 0x0301D000 thus it has GHIGH_B deasserted and INIT high. I don't know what this state is supposed to mean; with GHIGH_B deasserted it seems that there's no configuration loaded at all, and the configuration sequence hasn't completed. Or maybe it did load a configuration correctly (which is why it deasserted GHIGH_B) but it still didn't complete the configuration sequence for some reason. If I flip the bits of every byte (too see if MSB first output might do the trick) just before I output them the xc3s400 jumps to this state; 0x036D0000. GHIGH_B is asserted and the configuration sequence is completed. I have no idea what this means, with GHIGH_B asserted it effectively disables the internal logic afaik, which could mean (again) that no configuration is loaded - but it does start up. I can also get to this state if I shift/swap/mangle the data in other ways - it seems that if you send rubbish to the fpga it jumps to this state after you send an JSTART command. Is anybody recognising these states? What do they mean? Cheers, Mike http://projectvga.orgArticle: 128885
Hi
I came across the following code statement, and here I wonder
what does this integer'image attribute with the loc(i) mean?
This RLOC specifies where to put the stuff on an Xilinx FPGA,
but I really wonder what the second part is doing. In addition,
I have never come across the integer'image attribute.
INST : for i in 0 to WIDTH-1 generate
attribute RLOC of u_lut : label is "R" & integer'image(loc(i)) &
"C0.S1";
attribute RLOC of u_1 : label is "R" & integer'image(loc(i)) &
"C0.S1";
attribute RLOC of u_2 : label is "R" & integer'image(loc(i)) &
"C0.S1";
attribute RLOC of u_3 : label is "R" & integer'image(loc(i)) &
"C0.S1";
attribute INIT of u_lut : label is "C66C";
thanks
C
Article: 128886"Alfreeeeed" <Alfredo.Taddei@gmail.com> wrote in message news:f167a323-f729-46e3-a146-1e98c8f46967@s37g2000prg.googlegroups.com... >> >> Google:- >> DC890B site:linear.com >> >> From your original post, what do you mean by "-ADC <80Msps <10bit"? >> '<' means 'less than', right? >> Syms. > > Sorry , Syms I replied only to you. > > > I need at least 80 Msps and 10 bit resolution. > I apologize for the inconvenience. > Alfred OK, so, maybe the Linear Tech dev. boards will work? You might have to replace the FPGA xc3s200-pq208 with the xc3s500e-pq208 you asked for. Dunno if they're pin compatible... DC851A DC890B Syms.Article: 128887
"Gerry" <Gerry@yahoo.com> wrote in message news:fohqrq$o9s$1@aioe.org... > Peter Alfke wrote: >> Your LUT-RAM-based very big RAM may have long routing delays. >> If you believe in trying things out (instead of simulation), then reduce >> the clock rate, and see whether that helps. >> >> In your place, I would still try to rearrange the logic, so as to live >> with synchronous BlockRAMs. >> Peter Alfke, Xilinx > > Thanks Peter, you saved my life ;). Reduce clock frequency and now it > works which is great news. Anyway, as you suggested I will try and > rearrange the logic to make it work with a synchronous BRam > > Thanks! Hi Gerry, I suggest you make sure you use timing constraints in future. It's all described in the constraints guide. This, used in conjunction with the timing analyser tools, will let you know when things are failing timing. HTH., Syms.Article: 128888
On Feb 8, 10:30=A0am, Clemens <Clemen...@yahoo.com> wrote: > =A0 =A0Hi > > I came across the following code statement, and here I wonder > what does this integer'image attribute with the loc(i) mean? > For scalar types (integer, std_logic, bit, real, time, etc.) the 'image' attribute returns a string. So integer'image(x) will return the string "123" assuming that 'x' is an integer and has the value 123. So the code you posted is generating a set of "RLOC" attributes and building up the string representation of that by concatenating the string "R" with a string representing the integer value of 'loc(i)' and the string "C0.S1". The image attribute doesn't work for vectors though, so you can't say std_logic_vector'image(my_slv)...in case you were wondering about that as well, even though it does not apply to the code you were wondering about. Kevin JenningsArticle: 128889
Clemens wrote:
> I put a timing constraint in the UCF File where i asked for a minimum
> frequency of 35 MHz (29 ns) but unfortuatenly XST tells me that
> the ratio was not met and the actual ratio is 38 ns. I have already
> optimized for speed, it there any way to tell the tool it should
> sythesis it for more than 35 MHz forgetting about any area constraints?
It sounds like synthesis has done its best.
I would find the slow nets and pipeline them.
-- Mike Treseler
Article: 128890
Nial Stewart wrote:
> I have come across a couple of odd customer style guide requirements
> which are...
> 1) Only one process per clock is allowed per entity (hello Nick).
> I never understood the thinking behind this.
It makes synchronization easier to design and test.
I take this one step further and use
one process per entity and one clock per process.
> I normally structure my code the way I had partitioned a design,
> for example a process for low level control with a higher level
> 'protocol' process in an I2C interface.
> To me this makes the code easier to read/support but this can't
> be done with one process.
You have the option of writing and testing
a version in your own style, then using
the same testbench on a restyled version.
> 2) There must be no unconstrained paths in a design.
I would cover this requirement
with Fmax on a synchronous design.
This covers all internal paths.
-- Mike Treseler
Article: 128891
Hi,
My basic requirement is to have a set of commands for a block. This
has been declared as :
TYPE command IS ARRAY (NATURAL range <>) OF NATURAL;
CONSTANT block1_command :command:=
(
-- ('1','0','1',X"0F_0F"),
(16#1F#),
(16#11#),
(16#12#),
(16#15#)
);...follows...
Now I have 5-6 blocks as :
TYPE blocks IS (block1, block2....block5);
I wish to link block1 with block1_command ; block2 with
block2_command.....etc.....i.e. if I pass 'block1' to my entity, it
should get associated with block1_command.
One way of doing this is :
type command_table is array (blocks, command) of blocks; but this
doesnt work since command is not discrete....
Can anyone help me with some other method ?
Help appreciated.
Thanks,
Vijayant
Article: 128892Symon wrote: > OK, so, maybe the Linear Tech dev. boards will work? You might have to > replace the FPGA xc3s200-pq208 with the xc3s500e-pq208 you asked for. Dunno > if they're pin compatible... > Nope, not at all; http://www.opencircuits.com/Xilinx_XC3S400_and_XC3S500E_pin_comparison Cheers, Mike http://projectvga.orgArticle: 128893
Michael Meeuwisse wrote: > mmihai wrote: >> Did you try xc3sprog? > > No I haven't. I have now, had to patch it somewhat to get it working with the D2XX drivers but it programmed the FPGA correctly while using the bit file. So it's definitely a software issue. > Is anybody recognising these states? What do they mean? > I noticed I misread the status register, the states look like; 0x031D0000 - 0011 0001 1011 0 0x036D8000 - 0011 0110 1011 1 Anybody seen this before? Cheers, Mike http://projectvga.orgArticle: 128894
On Feb 8, 12:57 pm, Michael Meeuwisse <mickeymeeuw@g_something> wrote: > Michael Meeuwisse wrote: > > mmihai wrote: > >> Did you try xc3sprog? > > > No I haven't. > > I have now, had to patch it somewhat to get it working with the D2XX > drivers but it programmed the FPGA correctly while using the bit file. > So it's definitely a software issue. Good news! From your posts it looked like you had a new board and new software. Hard do debug, what's wrong, sw or hw? Now you know were to look for problems. -- mmihaiArticle: 128895
Michael Meeuwisse <mickeymeeuw@g_something> wrote: ... > I'll see if I can get xc3sprog to work, if it's capable of programming > the fpga at least I know the problem lies in the parser. Go to the xc3prog sourceforge site and look for the pending patches there. These are my changes to get my FT2232 layout running to programm XC3S and XCF. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 128896
Not much compared to the "norm" around here, but... http://www.delorie.com/electronics/bin2seven/Article: 128897
On Feb 8, 4:55 pm, DJ Delorie <d...@delorie.com> wrote: > Not much compared to the "norm" around here, but... > > http://www.delorie.com/electronics/bin2seven/ Neat. Some great things grow from small beginnings. Here's what I've been hacking on: http://repo.or.cz/w/yari.git Cheers, TommyArticle: 128898
On Feb 8, 11:05 am, Mike Treseler <mike_trese...@comcast.net> wrote: > Clemens wrote: > > I put a timing constraint in the UCF File where i asked for a minimum > > frequency of 35 MHz (29 ns) but unfortuatenly XST tells me that > > the ratio was not met and the actual ratio is 38 ns. I have already > > optimized for speed, it there any way to tell the tool it should > > sythesis it for more than 35 MHz forgetting about any area constraints? > > It sounds like synthesis has done its best. > I would find the slow nets and pipeline them. > > -- Mike Treseler There are other things that can be done. One of the first ones is to use the Timing Analyzer from ISE. This tool will give you some good ideas to try and make your design work. It will also let you see exactly how you're failing the timing on that clock. Another option is to try multi-pass map/place-and-route. I say both because as of the 9.1 version of the tools, you have to perform MAP and PAR at the same cost-table value for it to work as expected. If you're solely using ISE, this can be enabled from one of the menu's, somewhere. I do most of my work in EDK and I have a script that I use to perform multi-pass place and route. If you're interested, I could post it. Another option that was introduced in the 9.1 version of the ISE tools is called the xplorer script. This is a more advanced version of multi- pass place and route (aka mppr). Previously, mppr just changed the cost table value and as such the placing of the design was affected. Now with the new xplorer script, it not only performs cost table changes, but trying advanced options for different types of algorithms for specific problems. Odds are using timing analyzer is all you need to do, and hopefully won't need to start worrying about mppr or xplorer yet. Those are usually used when trying to achieve higher frequencies than the one you mentioned (>100MHz fabric speeds). -- MikeArticle: 128899
Alfredo I'm not sure you will find a product like this. Most of the DSP orientated boards with ADC/DAC at this level tend be lined up with Virtex level FPGAs. I would also make the observation that the PQ208 package relatively poor at handling high speed I/O compared to BGA based parts and if we were designing a development board of this specification we certainly would not be using the PQ208 package. Not quite what you want and not a pretty solution but some of the Linear Tech ADC demo boards can plug into our Broaddown2 Spartan-3 Development, with minor mods, on the edge connector Alternatively you might also to be able to wire something like our Drigmorn1/Craignell boards (fitted with either XC3S100E-4CPG132C or XC3S500E-4CPG132C) on a high quality breadboard together with Linear Technology boards. Longer term we do have plans for middle end ADC/DAC modules to support all of our products that have DIL headers on them and for the very high end ADC/DAC there will be a Moel-Bryn module/s and another format(to be announced) that will support the forthcoming Hollybush2 product. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 PCI Development Board. On 8 Feb, 10:51, Alfreeeeed <Alfredo.Tad...@gmail.com> wrote: > Hi everybody , I am looking for a development board. My intention is > to devolp a DSP application so ideally should contain : > > -xc3s500e-pq208 > -ADC <80Msps <10bit > -DAC same specifications. > > -The PROM and JTAG interface is not an issue . I have a JTAG > programmer for PROMS. > > I would reaaly appreciate your help. > > Alfredo Taddei
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