Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 154325

Article: 154325
Subject: JTAG access from user design in Altera FPGAs
From: =?UTF-8?B?THVkd2lnIEjDvGdlbHNjaMOkZmVy?= <spamtrap-lh-0506@gmx.de>
Date: Fri, 28 Sep 2012 11:40:40 +0200
Links: << >>  << T >>  << A >>
Hi,

does somebody know, how to access the JTAG port from a user design
(VHDL) in Altera FPGA (cyclone 4)?

TIA

Ludwig

Article: 154326
Subject: Re: Replacing Logic with an FPGA/CPLD in a 510K device.
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Fri, 28 Sep 2012 09:42:41 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Thu, 27 Sep 2012 21:59:34 -0400, Gabor wrote:

> On 9/27/2012 5:26 PM, hamilton wrote:
>> Does anyone have some good links on FDA requirements for replacing TTL
>> logic with an FPGA/CPLD ?
>>
>> This is for a Class 3 device.
>>
>> Does the FPGA/CPLD design files constitute "firmware" and needs to be
>> tested the same way as firmware ?

> http://www.mentor.com/resources/techpubs/upload/mentorpaper_68961.pdf
> 
> It talks about a lack of specific standards in the hardware development
> process, and how to go about ensuring quality using techniques borrowed
> from other hi-rel fields like aerospace.  It no doubt recommends an
> approach that requires plenty of their verification tools...
> 
> -- Gabor

My first thought was DO-254, and I'm glad to see the paper discusses it.
Only 2 pages focus on how many of Mentor's expensive tools you need ;-)

But I think her case that it is radically different from software best 
practice is weak; in particular, formal methods and parallelism are also 
a concern in software best practice, hence tools like SPARK and the 
Ravenscar profile.

In contrast, I believe DO-254 is actually a development of the DO-178 
process for software (which the paper doesn't even mention), and the two 
have a lot in common. 
http://www.atego.com/services/training-course/avionics-certification/
covers both in a single course.

http://www.open-do.org/ has quite a lot of information and open tools on 
the software side of best practice.
http://www.open-do.org/projects/hi-lite/
http://www.open-do.org/projects/geneautoada/
the latter covering model-based design, e.g. in Simulink.

It is also interesting how much in common there is between the 
synthesisable subset of VHDL, and the SPARK subset of Ada. Apparently the 
transformations between RTL and gates(or LUTs,FFs) and between software 
and proof conditions have a lot of the same limitations (e.g. no dynamic 
allocation...)

It may not be the case that FDA accept DO178 or DO254 wholesale, but it 
is likely that following these approaches would make for a good safety 
case and simplify the approval process.

In short, if you meant "can FPGA firmware be tested the same way as 
typical embedded C code", ... errr, no.

But if you meant "... following software best practice, like SPARK or 
DO-178b," you would be a long way towards the goal.

- Brian

Article: 154327
Subject: Re: JTAG access from user design in Altera FPGAs
From: Frank Buss <fb@frank-buss.de>
Date: Fri, 28 Sep 2012 12:44:10 +0200
Links: << >>  << T >>  << A >>
Ludwig Hügelschäfer wrote:
> 
> does somebody know, how to access the JTAG port from a user design
> (VHDL) in Altera FPGA (cyclone 4)?

I don't know, if you can use the JTAG port as normal pins, as you can do
with some of the configuration pins after configuration, but you can use
a megafunction to communicate over the JTAG protocol with your entities:

http://www.altera.com/literature/ug/ug_virtualjtag.pdf

-- 
Frank Buss, http://www.frank-buss.de
electronics and more: http://www.youtube.com/user/frankbuss

Article: 154328
Subject: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
From: "langwadt@fonz.dk" <langwadt@fonz.dk>
Date: Fri, 28 Sep 2012 04:51:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 28, 2:54=A0am, n...@puntnl.niks (Nico Coesel) wrote:
> Tim Wescott <t...@seemywebsite.com> wrote:
> >On Thu, 27 Sep 2012 19:54:08 +0000, Nico Coesel wrote:
>
> >> Tim Wescott <t...@seemywebsite.com> wrote:
>
> >>>On Wed, 26 Sep 2012 23:06:03 +0000, Nico Coesel wrote:
>
> >>>> "nba83" <3224@embeddedrelated> wrote:
>
> >>>>>>On Mon, 24 Sep 2012 06:00:15 -0500
> >>>>>>"nba83" <3224@embeddedrelated> wrote:
>
> >>>>>>> >On 09/24/2012 08:09 AM, nba83 wrote:
>
> >>>>>>> >> I want to feed data in parallel (8bit) to CPLD, buffer it for
> >>>>>>> >> about
> >>>>>100
> >>>>>>> >> bytes, and then start to drive SPI Out. I am some how concerne=
d
> >>>>>about
> >>>>>>> the
>
> >>>> Still, given your project requirements you probably could get by wit=
h
> >>>> a small FIFO (maybe 4 bytes deep). You need to get enough data from
> >>>> the microcontroller. OTOH it sounds like a lot of fuss to keep the
> >>>> microcontroller. If you switch to an ARM device (NXP for instance) y=
ou
> >>>> can reach >30MHz SPI easely and use DMA.
>
> >>>He's using an STM32F107 which _is_ an ARM Cortex, and he's claiming to
> >>>need more than 35MHz.
>
> >> I guess ST is still making mediocre controllers. After an adventure wi=
th
> >> the STR700 series I switched to NXP and never looked back at ST.
> >> Appearantly a good choice :-)
>
> >35MHz clock at the peripheral -- the ST chip he's looking at is rated fo=
r
> >70 or 72MHz or some such.
>
> AFAIK most ST devices can't run from flash at their rated clock
> speeds. NXP's can and some go up to 120MHz (180MHz is on its way)!
>

STM32F4 has a flash accelerator similar to NXP and run at full speed
168MHz

the stm32f107 looks to have 2x I2S that can run at pclk/2 the ad1933
can run
dual line so I think it should be possible

-Lasse


Article: 154329
Subject: Re: Xilinx CPLD XC95144 for Driving Sigma Delta DAC
From: Tim Wescott <tim@seemywebsite.please>
Date: Fri, 28 Sep 2012 11:10:29 -0500
Links: << >>  << T >>  << A >>
On Fri, 28 Sep 2012 00:54:34 +0000, Nico Coesel wrote:

> Tim Wescott <tim@seemywebsite.com> wrote:
> 
>>On Thu, 27 Sep 2012 19:54:08 +0000, Nico Coesel wrote:
>>
>>> Tim Wescott <tim@seemywebsite.com> wrote:
>>> 
>>>>On Wed, 26 Sep 2012 23:06:03 +0000, Nico Coesel wrote:
>>>>
>>>>> "nba83" <3224@embeddedrelated> wrote:
>>>>> 
>>>>>>>On Mon, 24 Sep 2012 06:00:15 -0500 "nba83" <3224@embeddedrelated>
>>>>>>>wrote:
>>>>>>>
>>>>>>>> >On 09/24/2012 08:09 AM, nba83 wrote:
>>>>>>>> >
>>>>>>>> >> I want to feed data in parallel (8bit) to CPLD, buffer it for
>>>>>>>> >> about
>>>>>>100
>>>>>>>> >> bytes, and then start to drive SPI Out. I am some how
>>>>>>>> >> concerned
>>>>>>about
>>>>>>>> the
>>>>> 
>>>>> Still, given your project requirements you probably could get by
>>>>> with a small FIFO (maybe 4 bytes deep). You need to get enough data
>>>>> from the microcontroller. OTOH it sounds like a lot of fuss to keep
>>>>> the microcontroller. If you switch to an ARM device (NXP for
>>>>> instance) you can reach >30MHz SPI easely and use DMA.
>>>>
>>>>He's using an STM32F107 which _is_ an ARM Cortex, and he's claiming to
>>>>need more than 35MHz.
>>> 
>>> I guess ST is still making mediocre controllers. After an adventure
>>> with the STR700 series I switched to NXP and never looked back at ST.
>>> Appearantly a good choice :-)
>>
>>35MHz clock at the peripheral -- the ST chip he's looking at is rated
>>for 70 or 72MHz or some such.
> 
> AFAIK most ST devices can't run from flash at their rated clock speeds.
> NXP's can and some go up to 120MHz (180MHz is on its way)!

Yes, good point.  And part of my point to the OP is that once he solves 
his ADC throughput problem, is he going to be able to generate the data?

Depending on his application, a teeny bit of code running out of RAM in 
the '107 may be enough.  Or, the app may self-destruct on a ton of code 
running at 120MHz on your NXP.

-- 
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com

Article: 154330
Subject: Need Terasic LTM Module
From: "Abby" <abbybrown@charter.net>
Date: Sun, 30 Sep 2012 10:50:50 -0400
Links: << >>  << T >>  << A >>
Hi,

I delayed too long in ordering a Terasic LTM touchscreen module and now they 
are listed as phased out with no substitute shown.  Anyone know where I can 
get one?  Or equivalent?

Thanks,
Gary


Article: 154331
Subject: Re: JTAG access from user design in Altera FPGAs
From: =?UTF-8?B?THVkd2lnIEjDvGdlbHNjaMOkZmVy?= <spamtrap-lh-0506@gmx.de>
Date: Mon, 01 Oct 2012 10:45:48 +0200
Links: << >>  << T >>  << A >>
On 28.09.2012 12:44, Frank Buss wrote:
> Ludwig Hügelschäfer wrote:
>>
>> does somebody know, how to access the JTAG port from a user design
>> (VHDL) in Altera FPGA (cyclone 4)?
> 
> I don't know, if you can use the JTAG port as normal pins, as you can do
> with some of the configuration pins after configuration, but you can use
> a megafunction to communicate over the JTAG protocol with your entities:
> 
> http://www.altera.com/literature/ug/ug_virtualjtag.pdf

Thanks a lot, that's exactly what I have looked for!

Ludwig


Article: 154332
Subject: Re: New(?) fast binary counter for FPGAs without carry logic (e.g.
From: robotron <hefaistos@gmail.com>
Date: Mon, 1 Oct 2012 08:03:42 -0700 (PDT)
Links: << >>  << T >>  << A >>
Dear colleagues,

thank you for the pointers to prior art.
I have included link to this newsgroup thread to the project page.

Best regards,
Marek

Article: 154333
Subject: Re: Just gloating
From: Bart Fox <bartfox@gmx.net>
Date: Tue, 02 Oct 2012 07:10:44 +0200
Links: << >>  << T >>  << A >>
Am 25.09.12 02:32, schrieb Rob Gaddi:
> I've got a VHDL design in which I use record types as a convenient way
> of wiring up my internal buses.  This design is a single-master,
> multiple slave bus.  The default assignment to all of the slaves puts
> don't cares ('X', actually) on the data and address lines for any slave
> not currently in use, it's only the control signals that get specific
> assignments that tell the slave it's not in use.
[...]
> The last time I tried this, under ISE 12.3, this was not the case, and
Maybe you used an not so actual architecture last time (like Spartan 3)?
Xilinx did improvements on xst, but only for the newer chip families.
But you can try "-use_new_parser yes" on xst.

See the solutio section: http://www.xilinx.com/support/answers/41013.htm

regards,
Bart

Article: 154334
Subject: fft in fpga using polar form
From: jack.pett.son@gmail.com
Date: Wed, 3 Oct 2012 10:11:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
i understand that representing large number of twiddle factors that are req=
uired in a fft with large number of points is an issue when using fixed poi=
nt scheme. To my understanding (which could be very wrong as i am new to th=
is),the issue is large dynamic range that is needed to represent real and i=
maginary parts of the complex numbers. Would the use of polar form to repre=
sent them solve this problem, as for all twiddle factors, the absolute valu=
e will be one and the argument will change from 0 to 360? (or should the ar=
gument be specified in radians always?)

Article: 154335
Subject: Re: fft in fpga using polar form
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 3 Oct 2012 17:39:50 +0000 (UTC)
Links: << >>  << T >>  << A >>
jack.pett.son@gmail.com wrote:
> i understand that representing large number of twiddle factors 
> that are required in a fft with large number of points is an 
> issue when using fixed point scheme. 

As far as I know, that isn't a problem. 

> To my understanding 
> (which could be very wrong as i am new to this),the issue is 
> large dynamic range that is needed to represent real and 
> imaginary parts of the complex numbers. 

No matter how you do it, you can't have a large dynamic
range with the FFT. (Or, even worse usually, the non-fast
DFT.) Enough addition and subtraction is done that the 
dynamic range is pretty much whatever precision the computation
is done at.

> Would the use of 
> polar form to represent them solve this problem, as for 
> all twiddle factors, the absolute value will be one and 
> the argument will change from 0 to 360? 

I don't believe that helps. For the usual twiddle factors,
all you need is a small (or big) lookup table. In polar
coordinates, with any angular measure, you need to compute
sines and cosines at each step.

Well, if all you needed to do was rotations in polar 
coordinates, then yes. But you also have to add and subtract
values at different rotations.

> (or should the argument be specified in radians always?)

More obvious to me, binary fractions of a whole rotation.

-- glen

Article: 154336
Subject: Trigonometry in degrees, was: fft in fpga using polar form
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 3 Oct 2012 17:51:06 +0000 (UTC)
Links: << >>  << T >>  << A >>
jack.pett.son@gmail.com wrote:
> Would the use of polar form to represent them solve this problem?

Which reminds me of a different question I have wondered
about for a while: 

Why do so few high-level languages provede trigonometric
functions in degrees in their math libraries?

The only one I know of is PL/I, not so commonly used these days.

I know the reasons for doing trigonometry in radians, and have
no complaint against doing it in radians, but reasonably often it
is convenient to do in a unit that is a rational fraction of a 
whole rotation.

Now, the same arguments against degrees could be used against
supplying a log10 function, but many systems do supply that one.

Usually the first thing that non-inverse trigonometric routines
do is argument reduction after dividing by some multiple of pi.
If one actually wants a nice fraction of a whole circle, it is
extra work and precision loss to multiply by some multiple of pi
just before the routine divides by a multiple of pi.

-- glen

Article: 154337
Subject: FPGA-Board for Ethernet
From: bankoo <bln5320@googlemail.com>
Date: Thu, 4 Oct 2012 07:38:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
I am searching a FPGA board for a project where i have to connect an twiste=
d pair cable to a FPGA and send&receive packages on a pc. So it will look l=
ike this
switch <-> FPGA Board <-> PC
UDP will be enough because I dont need any further information from the pac=
kages.
It will be a 100Mbit/s Ethernet but no standard ethernet like 100base-T. (d=
ifferent coding PAM-3)=20
Do you think a normal Board with Spartan-3 will be enough? Its shameful to =
say but, I=B4ve never worked with FPGAs so I am asking here.

Thank you very much.
best regards,
banko

Article: 154338
Subject: Re: FPGA-Board for Ethernet
From: Gabor <gabor@szakacs.org>
Date: Thu, 04 Oct 2012 18:24:27 -0400
Links: << >>  << T >>  << A >>
On 10/4/2012 10:38 AM, bankoo wrote:
> Hi,
> I am searching a FPGA board for a project where i have to connect an twisted pair cable to a FPGA and send&receive packages on a pc. So it will look like this
> switch <-> FPGA Board <-> PC
> UDP will be enough because I dont need any further information from the packages.
> It will be a 100Mbit/s Ethernet but no standard ethernet like 100base-T. (different coding PAM-3)
> Do you think a normal Board with Spartan-3 will be enough? Its shameful to say but, Ive never worked with FPGAs so I am asking here.
>
> Thank you very much.
> best regards,
> banko
>

   If you don't want to spend a lot of money on tools, I'd recommend
any board (with Ethernet) that comes with a device-locked license
for the Embedded Edition of ISE.  This gives you access to LWIP
(light-weight IP) and is likely to come with enough demo apps to
make your life easier, whether you intended to use an embedded
processor or not.

-- Gabor

Article: 154339
Subject: Re: FPGA-Board for Ethernet
From: jonesandy@comcast.net
Date: Thu, 4 Oct 2012 16:07:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
You might look at Arrow Electronics' BeMicro SDK with usb, 10/100 enet, SD =
card, MDDR RAM, and a 22K LE Cyclone 4E FPGA, for the peasantly sum of $79.=
 All in a "memory stick" form factor, with an expansion connector on the en=
d. It is intended for developing applications around their NIOS soft proces=
sor, but is perfectly useable as an ordinary FPGA.

Andy

Article: 154340
Subject: Re: FPGA-Board for Ethernet
From: darol.klawetter@gmail.com
Date: Mon, 8 Oct 2012 06:29:39 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Thursday, October 4, 2012 10:38:04 AM UTC-4, bankoo wrote:
> Hi,
>=20
> I am searching a FPGA board for a project where i have to connect an twis=
ted pair cable to a FPGA and send&receive packages on a pc. So it will look=
 like this
>=20
> switch <-> FPGA Board <-> PC
>=20
> UDP will be enough because I dont need any further information from the p=
ackages.
>=20
> It will be a 100Mbit/s Ethernet but no standard ethernet like 100base-T. =
(different coding PAM-3)=20
>=20
> Do you think a normal Board with Spartan-3 will be enough? Its shameful t=
o say but, I=B4ve never worked with FPGAs so I am asking here.
>=20
>=20
>=20
> Thank you very much.
>=20
> best regards,
>=20
> banko

Spartan 3 or Spartan 6 will work. Try digilentinc.com

Darol Klawetter

Article: 154341
Subject: modelsim SE 10.0C SystemC bug about initializing sc_signal
From: "homeless" <3749@embeddedrelated>
Date: Tue, 09 Oct 2012 08:10:29 -0500
Links: << >>  << T >>  << A >>
I am very disappointed that I get different results from the same
initializing code in SC_CTOR from 6.6 and 10.0 versions of ModelsimSE. In
ModelsimSE6.6 I can initialize the sc_signal vector (array) as it has to be
but in ModelsimSE10.0c all the chProcPos elements are "posLeft" which is
zero, since the compiler starts with zero to my "position" enumaration
type. I believe this is a bug in ModelsimSE10.0c.
PS: I also tried initializing with .write() member function.

I have a code like this:

typedef enum position_tag {posLeft, posRight, posUp, posDown, posLeftUp,
posRightUp, posLeftDown, posRightDown, posInner} position;

/*****/
sc_signal<position> chProcPos[NODES_IN_ROW][NODES_IN_COL];

SC_CTOR(..)
{
/*...*/
for (int i = 0; i < NODES_IN_ROW; i++)
 for (int k = 0; k < NODES_IN_COL; k++) {
   if (i == 0)
     if (k == 0)
       chProcPos[i][k] = posLeftUp;
     else if (k == NODES_IN_COL - 1)
       chProcPos[i][k] = posRightUp;
     else
       chProcPos[i][k] = posUp;
   else if (i == NODES_IN_ROW - 1)
     if (k == 0)
       chProcPos[i][k] = posLeftDown;
     else if (k == NODES_IN_COL - 1)
       chProcPos[i][k] = posRightDown;
     else
       chProcPos[i][k] = posDown;
   else
     if (k == 0)
       chProcPos[i][k] = posLeft;
     else if (k == NODES_IN_COL - 1)
       chProcPos[i][k] = posRight;
     else
       chProcPos[i][k] = posInner;
}
/*...*/
}


                    


	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 154342
Subject: Re: modelsim SE 10.0C SystemC bug about initializing sc_signal
From: HT-Lab <hans64@htminuslab.com>
Date: Tue, 09 Oct 2012 15:37:53 +0100
Links: << >>  << T >>  << A >>
I assume you are using the same compiler version as that sometimes can 
also cause issues. If you are not using gcc 4.3.3/4.2.1 (recommended 
versions for Linux/win32) then I would try that first.

If it still fails then try the latest Modelsim SE 10.1c release (gcc 
4.5.0/4.2.1) and if that also fails then package up a small testcase 
with your code and raise a Service Request.

You could also try the 2.2 reference simulator just to add some weight 
to your SR.

Good luck,
Hans
www.ht-lab.com


On 09/10/2012 14:10, homeless wrote:
> I am very disappointed that I get different results from the same
> initializing code in SC_CTOR from 6.6 and 10.0 versions of ModelsimSE. In
> ModelsimSE6.6 I can initialize the sc_signal vector (array) as it has to be
> but in ModelsimSE10.0c all the chProcPos elements are "posLeft" which is
> zero, since the compiler starts with zero to my "position" enumaration
> type. I believe this is a bug in ModelsimSE10.0c.
> PS: I also tried initializing with .write() member function.
>
> I have a code like this:
>
> typedef enum position_tag {posLeft, posRight, posUp, posDown, posLeftUp,
> posRightUp, posLeftDown, posRightDown, posInner} position;
>
> /*****/
> sc_signal<position> chProcPos[NODES_IN_ROW][NODES_IN_COL];
>
> SC_CTOR(..)
> {
> /*...*/
> for (int i = 0; i < NODES_IN_ROW; i++)
>   for (int k = 0; k < NODES_IN_COL; k++) {
>     if (i == 0)
>       if (k == 0)
>         chProcPos[i][k] = posLeftUp;
>       else if (k == NODES_IN_COL - 1)
>         chProcPos[i][k] = posRightUp;
>       else
>         chProcPos[i][k] = posUp;
>     else if (i == NODES_IN_ROW - 1)
>       if (k == 0)
>         chProcPos[i][k] = posLeftDown;
>       else if (k == NODES_IN_COL - 1)
>         chProcPos[i][k] = posRightDown;
>       else
>         chProcPos[i][k] = posDown;
>     else
>       if (k == 0)
>         chProcPos[i][k] = posLeft;
>       else if (k == NODES_IN_COL - 1)
>         chProcPos[i][k] = posRight;
>       else
>         chProcPos[i][k] = posInner;
> }
> /*...*/
> }
>
>
>
>
>
> 	
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com
>


Article: 154343
Subject: Re: FPGA-Board for Ethernet
From: bln5320@googlemail.com
Date: Tue, 9 Oct 2012 07:40:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
Sorry I was not at work the last days. Thank you very much for the answers =
and your care. =20
I will do as you say and look for a board with Xilinx ISE.=20
The Diligent Boards are looking good.=20
I think it will be the Spartan 3E Starter Board:
http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,400,792&Prod=3DS=
3EBOARD
Or the Atlys=99 Spartan-6 FPGA Development Board
http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,400,836&Prod=3DA=
TLYS

Do I need an Gigabit-Ethernet PHY?
Do I need 2 RJ-45 Interfaces? Or can I connect the UTP Cable directly the t=
he FPGA pins. Or something like UTP to RJ-45 and the PC with usb?
For further Information about the used ethernet  you can look at the Figure=
 5 its the Broadcom Ethernet
http://itersnews.com/?p=3D10541


Thank you very much=20
Banko

Article: 154344
Subject: Spartan 6 MCB refresh timing
From: Stefan Huebner <stefan@huebner-informationselektronik.de>
Date: Wed, 10 Oct 2012 00:33:28 +0200
Links: << >>  << T >>  << A >>
Hi there,

I'm designing a memory solution with a Spartan 6 talking to 2 128MByte 
16-bit-wide DDR3 RAMs.
As my application is timing critical I can most probably not use auto 
refresh, so my question is how long the refresh command issued to the 
MCB takes and which parameters do influence this timing parameter.

regards
Stefan Huebner

Article: 154345
Subject: Re: Spartan 6 MCB refresh timing
From: Tim Wescott <tim@seemywebsite.com>
Date: Wed, 10 Oct 2012 23:59:32 -0500
Links: << >>  << T >>  << A >>
On Wed, 10 Oct 2012 00:33:28 +0200, Stefan Huebner wrote:

> Hi there,
> 
> I'm designing a memory solution with a Spartan 6 talking to 2 128MByte
> 16-bit-wide DDR3 RAMs.
> As my application is timing critical I can most probably not use auto
> refresh, so my question is how long the refresh command issued to the
> MCB takes and which parameters do influence this timing parameter.
> 
> regards
> Stefan Huebner

While you're pondering, check the data sheet carefully: the old 4116 
style DRAM would refresh on _any_ access (either row or column, I can't 
remember which); so all you had to do was cycle through the correct 
subset of memory and you'd never have to do an explicit refresh.

But: I dunno if SDRAM does that.

-- 
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

Article: 154346
Subject: Re: Spartan 6 MCB refresh timing
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 11 Oct 2012 06:17:25 +0000 (UTC)
Links: << >>  << T >>  << A >>
Tim Wescott <tim@seemywebsite.com> wrote:
> On Wed, 10 Oct 2012 00:33:28 +0200, Stefan Huebner wrote:

>> I'm designing a memory solution with a Spartan 6 talking to 2 128MByte
>> 16-bit-wide DDR3 RAMs.
>> As my application is timing critical I can most probably not use auto
>> refresh, so my question is how long the refresh command issued to the
>> MCB takes and which parameters do influence this timing parameter.

> While you're pondering, check the data sheet carefully: the old 4116 
> style DRAM would refresh on _any_ access (either row or column, I can't 
> remember which); so all you had to do was cycle through the correct 
> subset of memory and you'd never have to do an explicit refresh.

Yes. Especially convenient if the RAM was used for both video
display and computer memory, as the raster scan would get through
all rows (or columns).

> But: I dunno if SDRAM does that.

I am pretty sure it is true of all DRAM forms if you can find
out the refresh pattern.

DRAM does a destructive read, so it has to rewrite after read.

The usual geometry reads the data from one column (I believe)
into a register, gives you the bit(s) from the appropriate row,
then writes back the whole column.

In the 4116 days it was really a whole column. Now, at higher
densities, it is usually closer to an array of much smaller
squares, each of which has rows and columns. 

If you can't be sure of the access pattern, though, you have
to refresh.

-- glen


Article: 154347
Subject: Re: Spartan 6 MCB refresh timing
From: Gabor <gabor@szakacs.invalid>
Date: Thu, 11 Oct 2012 09:10:37 -0400
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:
> Tim Wescott <tim@seemywebsite.com> wrote:
>> On Wed, 10 Oct 2012 00:33:28 +0200, Stefan Huebner wrote:
> 
>>> I'm designing a memory solution with a Spartan 6 talking to 2 128MByte
>>> 16-bit-wide DDR3 RAMs.
>>> As my application is timing critical I can most probably not use auto
>>> refresh, so my question is how long the refresh command issued to the
>>> MCB takes and which parameters do influence this timing parameter.
> 
>> While you're pondering, check the data sheet carefully: the old 4116 
>> style DRAM would refresh on _any_ access (either row or column, I can't 
>> remember which); so all you had to do was cycle through the correct 
>> subset of memory and you'd never have to do an explicit refresh.
> 
> Yes. Especially convenient if the RAM was used for both video
> display and computer memory, as the raster scan would get through
> all rows (or columns).
> 
>> But: I dunno if SDRAM does that.
> 
> I am pretty sure it is true of all DRAM forms if you can find
> out the refresh pattern.
> 
> DRAM does a destructive read, so it has to rewrite after read.
> 
> The usual geometry reads the data from one column (I believe)
> into a register, gives you the bit(s) from the appropriate row,
> then writes back the whole column.
> 
> In the 4116 days it was really a whole column. Now, at higher
> densities, it is usually closer to an array of much smaller
> squares, each of which has rows and columns. 
> 
> If you can't be sure of the access pattern, though, you have
> to refresh.
> 
> -- glen
> 
Refresh is by row, not column, but otherwise as Glen says.  For SDRAM
there are multiple "banks" which behave like multiple chips, i.e.
any access refreshes a row from the selected bank only.  Auto-refresh
refreshes one row of each bank using an internal row counter.  DDR
SDRAM added a condition that you must run auto-refresh at a minimum
rate so the chip can use this time to update its DLL while the data
lines are not active.  Micron says its chips don't really need this,
but it's in the JEDEC spec, so memory controllers generally abide by
it.  By the way, you don't actually need to read or write to refresh
a row, the minimum requirement is just row activate followed by row
precharge.

My first question would be why are you using DDR3 for a random-access
application?  Do you really need the 128 MBytes?  If you're only using
a small portion of the memory, you might want to think of using a
static RAM, or even a single-data-rate SDRAM, which is much simpler
to interface and wouldn't require the MCB or SSTL I/O.  Otherwise I
think you're going to need to spend a lot of time with the simulator
finding out how the MCB works at a level lower than what you read
in the documents.

-- Gabor

Article: 154348
Subject: fixed point fft butterfly stage testing help
From: jack.pett.son@gmail.com
Date: Thu, 11 Oct 2012 09:42:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
I am new to verilog/hardware arithmetic and seeking good advice on testing a fft butterfly stage that I have written.

module butterfly #(parameter size=16, Q=4)
	(input signed[size-1:0] a_real,
	 input signed[size-1:0] a_imag,
	 input signed[size-1:0] b_real,
	 input signed[size-1:0] b_imag,	 
	 input signed[size-1:0] w_real,
	 input signed[size-1:0] w_imag,
	 output reg signed[size-1:0] x_real,
	 output reg signed[size-1:0] x_imag,
	 output reg signed[size-1:0] y_real,
	 output reg signed[size-1:0] y_imag	  
    ); 
 
   
	 
	reg signed[size-1:0] w_b_real;
	reg signed[size-1:0] w_b_imag;	
	
	always @(a_real or a_imag or b_real or b_imag or w_real or w_imag) begin

		w_b_real = b_real*w_real - b_imag*w_imag;
		w_b_imag = b_real*w_imag - b_imag*w_real;	
		
		w_b_real = w_b_real >> Q;	
		w_b_imag = w_b_imag >> Q;	

		x_real = a_real + w_b_real;
		x_imag = a_imag + w_b_imag;
		y_real = a_real - w_b_real;
		y_imag = a_imag - w_b_imag;
	
	end

endmodule

When writing the test bench, I came across several problems which I have no prior experience. 
1. How to create fixed point signed numbers that can be fed as input which will not create overflows inside butterfly module
2. How to create the expected results to compare

Greatly appreciate any help on these regard.



Article: 154349
Subject: ise 32b or 64b?
From: mmihai <iiahim@yahoo.com>
Date: Thu, 11 Oct 2012 15:57:54 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi!

Using Xilinx flow (command line, ISE 13.4)... 32b version vs 64b (under Linux, 64b OS)... memory usage:

||       |   32b   |   64b   |
 |  xst  |  1614M  |  2986M  |
 |  map  |  1563M  |  2889M  |
 |  par  |  1365M  |  2404M  |

Also the 32b runtime is faster than 64b....

The above table is from a Kintex-7 target running on a i5 machine, 8G RAM.

Similar numbers are seen for a Virtex-6 target, i7 machine, 24G RAM, different Linux flavor.

Does this look normal? Looks like if the design fits the memory space available for 32b binaries they are a much better choice.

---
mmihai



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search