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posedge52@yahoo.com wrote: > On 31 Jan, 00:01, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> > wrote: > > If you run on anything non-Redhat/Windows, be prepared to get the answer > > "Not a supported platform" all the time :-( > > for every problem you report/webcase you open, as unrelated to any > > distribution the problem can be. It takes persistance to get Xilinx > > first level support to realize the problem... > So far I have solved problems without help from Xilinx. And should it > be needed one can always employ helpdesk engineering :) Beside the silly use of WinDriver, I also have no real problems when running on Linux/Suse. And with Michaels work http://www.rmdir.de/~michael/xilinx there is no more need for WinDriver to run Impact. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 128601
Hi All, I am trying to see the power consumption of some design using XPower with ModelSim generated .vcd file I get this message : WARNING:Power:1087 - Can't change frequency of net clk to 100.00Mhz It sets the clock frequency automatically to 10 MHz irrespective of what I use in my simulation. Is it a problem related to the option that I used to generate the VCD file? Anybody got same experience? Thanks, CharlesArticle: 128602
On Jan 30, 7:47 pm, Amit <amit.ko...@gmail.com> wrote: > Hello group, > > Recently I have started to learn NIOS. I will appreciate it if > somebody knows any good online resource or book that I can use. > > Thanks, > Amit Have you tried a google search? My one search on the subject got 17,400 hits, and a good weeks worth of reading/learning on the 1st page of hits. G.Article: 128603
>I am curious what are main applications of FPGA in >Telecommunications? one application is in wavelength switching. A routing label comes in on a common wavelength, followed by a packet on a designated wavelength. An FPGA decodes the routing label, looks up the destination, and sets an optical router so the packet goes to the right link. This requires the FPGA to respond while the packet is in flight, before it hits the optical switch. -- mac the naïfArticle: 128604
> >I am curious what are main applications of FPGA in Telecommunications? > Just guessing, but these days anything in the fixed infrastructure part of the network that used to be done in ASICs, which are now only viable for the hand-sets.Article: 128605
>Hi all, > >Has anyone ever tried to improve the security for the old Xilinx FPGA >devices, which doesn't have the 3-DES encryption? If so what's the >feasible approach ? So far I have no clue > >TIA, > I am not a Xilinx expert, but I think the answer is "cannot be done". Use something else if you don't want the bitstream snooped upon.Article: 128606
>> Recently I have started to learn NIOS. I will appreciate it if >> somebody knows any good online resource or book that I can use. >Have you tried a google search? My one search on the subject got >17,400 hits, and a good weeks worth of reading/learning on the 1st >page of hits. After that, he can try the copious Nios documentation (free on the Altera web site). Then there's the Nios forum: http://www.niosforum.com/ If that isn't enough, give up.Article: 128607
HT-Lab wrote: > "Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote >> If you run on anything non-Redhat/Windows, be prepared to get the answer >> "Not a supported platform" all the time :-( > > Unfortunately that seem to apply to most EDA tools. I would recommend to use > one of the Redhat clones like CentOS/WhiteBox/StarCom assuming of course you > can't afford to buy a Redhat EL license. Well, if you can afford the EDA tools (and if you are getting support, then you probably paid for them), then I think you can afford REL ;) But that said, I think that you will not have problems on other platforms with most tools. I run all kinds of EDA tools on Fedora 7 without problems. Well, ok, I will have to admit I have not gotten Impact to work yet, even with Michael's Windriver replacement. And Aldec at least does not care that I am using F7 when I need support.Article: 128608
hi i'm just working on a project where i need to create an fsl interface for my custom ip core. i used the "create and import" peripheral wizard from the edk. the wizard gives me the following options to choose from : "number of input/output 32 bit words" and two pages later "number of input arguments". whats the difference between those two things? when i look into the driver and vhdl code i still get 1 32 bit bus. the only thing is that depending on the values i choose the driver template for example creates one variable "input_0" (which in case of 8 32 bit input words and 1 input argument" is an array of 8. is there any speed advantage of creating a large array or is it better to create more input arguments. when i look at the selftest source code the macro is called for every entry of the array anyway..... or did i misunderstand something here? thanks urbanArticle: 128609
I'm working on a Low Pin Count (LPC) bus interface and would like to double check my design with an existing implementation. Does anyone have an existing design they could share? Verilog source would be great. The LPC bus is a protocol developed by Intel to supplant the ISA bus. Thanks! John ProvidenzaArticle: 128610
On Jan 31, 9:47 am, waltherz <walther.za...@gmx.de> wrote: > Hello all, > > i have a design finished a few month ago, that is working fine on a > xc2s200-pq208, but when i port it to a xc3s400-tq144, it ain't work > most of the time (depends on the synthesis process) even with lowest > frequencies for a single clock and a given period constraint. > > Now, i wonder, if this is due to wrong regulators. Are there any other > good guys here, using those? > (If yes, please, tell me Package and Size of Fpga too. :-) > > much thanks in advance > walther I don't know what you mean by "wrong regulators". You do know that the S2 (Spartan II) power supply voltages are not the same as the S3 (Spartan 3) power voltages, don't you? For example, the S2's Vccint is 2.5v and the S3's Vccint is 1.2v. Check the Xilinx web site for documentation. -Dave PollumArticle: 128611
Multiple port memories come down to scheduling issues. On occasions you may need multiple modules to access the same memory at the same time. If you only have a single port, one of the modules will have to stall until the memory is available. If these modules are frequently in contention, your performance goes right out the window. Thus a memory that has multiple ports. Multiple ports allow simultanious access to the memory. Less contention. Better performance. "merche" <dorama2@gmail.com> wrote in message news:ae3f9b08-ed83-4feb-a79f-6077709ca9b7@k2g2000hse.googlegroups.com... thanks a lot, i´m looking the controller on these page and it´s seem easy to understand. Other thing, why for a dual port to SDRAM controller? i suppose it´s faster.Article: 128612
RCIngham wrote: >> Hi all, >> >> Has anyone ever tried to improve the security for the old Xilinx FPGA >> devices, which doesn't have the 3-DES encryption? If so what's the >> feasible approach ? So far I have no clue >> >> TIA, >> > > I am not a Xilinx expert, but I think the answer is "cannot be done". Use > something else if you don't want the bitstream snooped upon. > Actually there are alternatives using external and/or internal features. This is marketing piece, but informative on the subject: http://www.xilinx.com/publications/prod_mktg/DesignSecurity_ssht.pdf And this white paper describes how to implement a CipherStream protocol: http://www.xilinx.com/support/documentation/white_papers/wp197.pdf An application note for copy protection using a secure EEPROM: http://www.xilinx.com/support/documentation/application_notes/xapp780.pdf And this landing page holds a whole lot more on this subject: http://www.xilinx.com/products/design_resources/security/ Ed McGettigan -- Xilinx Inc.Article: 128613
Use a drop in replacement. The security hole is snooping the bitstream. www.quicklogic.com has drop in replacements. You program once at the factory and then you don't have to worry about snooping done out in the field. If you need to reprogram the fpga at the customer site, and are worried about the security. You will need to go with the newer chips. "Marlboro" <ccon67@netscape.net> wrote in message news:a385b5f2-c073-4d3e-9890-efa5baa8b2cb@k39g2000hsf.googlegroups.com... > Hi all, > > Has anyone ever tried to improve the security for the old Xilinx FPGA > devices, which doesn't have the 3-DES encryption? If so what's the > feasible approach ? So far I have no clue > > TIA,Article: 128614
About the following code :
[1] Verilog, not VHDL. But treat it as a reference design.
[2] DRAM controllers are not especially daunting.
Yes ... the data sheets are large, but the actual
functions that need to occur (initialization,
write block, read blocks, and refresh cycles) are
pretty limited, and well documented.
[3] What is a challenge is getting the parts (more an
issue with the later DDR devices, and yet speedier
interfaces) to run at higher speeds. I have not
used ACTEL, but Xilinx has IOB FFs that are the
secret to running at high clock rates.
[4] This design is largely uncommented, and
undocumented. But it is free, and like I said can
be used as a design reference.
[5] When you are debugging .... if you have an easy
way to write/read blocks and verify data, then
use it, ie an embedded processor. Otherwise,
try to build a test block around your block,
which initiates a write block, then verifies
with a read block, and then allows you to
view (??) the read back data. If this were
a Xilinx design, chipscope is a good candidate
to view read back data. Otherwise, you may need
to add a uart to your code, and some logic to
dump read back data to RS232 port.
--
Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.
Colorado Based Xilinx Consultant
phone : 303.926.0068
email : jretta@rtc-inc.com
web : www.rtc-inc.com
> module tb_tx_dram_ctl (
> clk_ad9857_pd_drate,
> clk_ad9857_pd_drate_stable,
> clk_33mhz,
> ck_pci_reset_n,
>
> pci_dc_start_add_ld,
> pci_dc_block_cnt_ld,
> pci_dc_sdram_fifo_ld,
> pci_dc_sdram_fifo_rdnxt,
> pci_dc_sdram_wrdata,
> dc_pci_sdram_rddata,
> dc_pci_init_done,
> dc_pci_block_write_done,
> dc_pci_block_rd_done,
>
> dc_xt_sdram_ras,
> dc_xt_sdram_cas,
> dc_xt_sdram_we,
> dc_xt_sdram_cke,
> dc_xt_sdram_so_n,
> dc_xt_sdram_dqmb,
> dc_xt_sdram_ba,
> dc_xt_sdram_a,
> dc_sdram_dq_outen_n,
> dc_xt_sdram_dq_out,
> xt_dc_sdram_dq_in,
> dram_debug,
>
> dc_du_wr_next_line,
> dc_du_next_line_data,
> dc_du_reset_gnb,
> du_dc_get_next_blk,
> du_dc_blk_size,
> du_dc_blk_start_add,
> dc_pci_set_blkxfer_int,
>
> dc_pci_debug_1,
> dc_pci_debug_2,
> debug_write_last
>
> );
>
> input clk_ad9857_pd_drate;
> input clk_ad9857_pd_drate_stable;
> input clk_33mhz;
> input ck_pci_reset_n;
> input pci_dc_start_add_ld;
> input pci_dc_block_cnt_ld;
> input pci_dc_sdram_fifo_ld;
> input pci_dc_sdram_fifo_rdnxt;
> input [31:0] pci_dc_sdram_wrdata;
> output [31:0] dc_pci_sdram_rddata;
> output dc_pci_init_done;
> output dc_pci_block_write_done;
> output dc_pci_block_rd_done;
>
> output dc_xt_sdram_ras, dc_xt_sdram_cas, dc_xt_sdram_we;
> output [1:0] dc_xt_sdram_cke; // static
> output [3:0] dc_xt_sdram_so_n;
> output [7:0] dc_xt_sdram_dqmb; // static
> output [1:0] dc_xt_sdram_ba;
> output [12:0] dc_xt_sdram_a;
> output dc_sdram_dq_outen_n;
> output [63:0] dc_xt_sdram_dq_out;
> input [63:0] xt_dc_sdram_dq_in;
>
> output [47:0] dram_debug;
>
> output dc_du_wr_next_line;
> output [63:0] dc_du_next_line_data;
> output dc_du_reset_gnb;
> input du_dc_get_next_blk;
> input [7:0] du_dc_blk_size;
> input [29:0] du_dc_blk_start_add;
> output dc_pci_set_blkxfer_int;
> output [31:0] dc_pci_debug_1;
> output [31:0] dc_pci_debug_2;
> output debug_write_last;
>
> parameter DLY_7US_AT_PDCLK = 9'h15E;
>
> // **************************************************************************
> // wire and reg Defs
> // **************************************************************************
> reg [31:0] dc_pci_sdram_rddata;
> reg block_write_done, block_read_done;
> reg dc_pci_init_done, dc_pci_block_rd_done;
> reg fifo_room_for_40h_q, decrement_by_40_on_read;
> reg [2:0] blk_read_sequence_q;
> reg end_of_read_blk_handle_q;
>
> reg [1:0] bwr_done_q, brd_done_q;
> wire bwr_done_led = ~bwr_done_q[1] & bwr_done_q[0];
> reg clr_dram_afc;
> reg [63:0] sdram_fifo_drport_wr_data;
> reg [7:0] pipeline_rddata_val_q;
> reg [3:0] dc_xt_sdram_so_n;
> reg dc_xt_sdram_ras;
> reg dc_xt_sdram_cas;
> reg dc_xt_sdram_we;
> reg [1:0] dc_xt_sdram_ba;
> reg [12:0] dc_xt_sdram_a;
>
> reg pci_read_block_req;
> reg pci_write_block_rdy;
> reg [29:3] sdram_start_address_reg;
> reg pci_block_write_read_n;
> reg [8:0] pci_port_add_ctr;
> reg [10:0] pci_block_transfer_ctr, pci_dword_fetch_ctr;
> reg [8:0] sdram_block_transfer_ctr;
> reg [7:0] sdram_fifo_drport_add_ctr;
> reg [31:0] pci_low32_hr, pci_upper32_hr;
>
> reg [3:0] sdram_256mb_id;
> reg [1:0] sdram_ba;
> reg [12:0] sdram_a;
> reg [3:0] dram_ctl;
> reg [12:0] dram_delay_ctr;
> reg [5:0] dram_seq_state;
> reg [7:0] dram_loopcnt;
> reg dram_ctl_wr_blk_done;
> wire sblk_xfer_cnt_dec;
> reg pipeline_rddata_val;
> reg dc_sdram_dq_outen_n;
> reg dram_iq_semaphore;
> wire sdram_fifo_pci_wr = pci_dc_sdram_fifo_ld & pci_port_add_ctr[0];
> wire [63:0] sdram_fifo_wr_data = {pci_dc_sdram_wrdata[31:0], pci_low32_hr};
> wire [63:0] sdram_fifo_rd_data;
> wire [63:0] sdram_fifo_drport_rd_data;
> wire sblk_xfer_cnt_tc = (sdram_block_transfer_ctr == 9'h001);
>
> assign dc_xt_sdram_cke = 2'b11;
> assign dc_xt_sdram_dqmb = 8'b0000_0000;
> assign dc_xt_sdram_dq_out = sdram_fifo_drport_rd_data;
>
> reg dram_afc_tc_q;
> reg [8:0] dram_auto_refresh_ctr;
> wire dram_auto_refresh_ctr_tc = (dram_auto_refresh_ctr == DLY_7US_AT_PDCLK);
>
> reg get_next_blk_q, dc_du_wr_next_line, dc_du_reset_gnb;
> reg [63:0] dc_du_next_line_data;
> reg [29:3] iq_unpack_start_address_reg;
> reg [7:0] iq_unpack_block_transfer_ctr;
> reg fifo_room_for_40h;
> reg [1:0] dec_by_40_on_read_q;
>
> wire get_next_blk_led = ~get_next_blk_q & du_dc_get_next_blk;
> wire iq_unpack_xfer_cnt_tc = (iq_unpack_block_transfer_ctr == 8'h01);
>
> reg [47:0] dram_debug;
>
> // ********************************************************************
> // SDRAM Interface Signals
> // ********************************************************************
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> dc_xt_sdram_so_n <= ~({4{~dram_ctl[3]}} & sdram_256mb_id);
> dc_xt_sdram_ras <= dram_ctl[2];
> dc_xt_sdram_cas <= dram_ctl[1];
> dc_xt_sdram_we <= dram_ctl[0];
> dc_xt_sdram_ba <= sdram_ba;
> dc_xt_sdram_a <= sdram_a;
> dc_sdram_dq_outen_n <= (|pipeline_rddata_val_q[5:0]);
> end
>
> // ********************************************************************
> // 33 Mhz Domain
> // ********************************************************************
> reg [31:0] local_pci_dat_hr;
> reg pci_dc_start_add_ld_q, pci_dc_block_cnt_ld_q;
> reg pci_mode_blk_wr_rd_n;
> reg ld_last_word_of_xfer_q, ld_modulo_40_word_q, pci_inc_block_ctr_q;
> reg [6:0] pci_dwrd_ctr;
> reg [1:0] sdram_block_read_done_q, sdram_block_write_done_q;
> reg [1:0] pci_blkxer_ctr_tc_q;
> reg dc_pci_set_blkxfer_int;
> reg [6:0] pci_40_dword_detect_ctr;
>
> wire pci_blkxer_ctr_tc_q_led = ~pci_blkxer_ctr_tc_q[1] & pci_blkxer_ctr_tc_q[0];
>
> wire local_pci_hr_wr = pci_dc_start_add_ld | pci_dc_block_cnt_ld;
> wire pci_wr_rd_cycle = pci_block_write_read_n & pci_dc_sdram_fifo_ld | ~pci_block_write_read_n & pci_dc_sdram_fifo_rdnxt;
> wire ld_last_word_of_xfer = ((pci_block_transfer_ctr == 11'h001) & pci_dc_sdram_fifo_ld);
> wire ld_mod_40_word_on_write = ((pci_port_add_ctr[6:0] == 7'h7F) & pci_dc_sdram_fifo_ld);
> wire ld_mod_40_word_on_read = blk_read_sequence_q[0] & (pci_dword_fetch_ctr[10:0] >= 11'h040);
> wire ld_modulo_40_word = ld_mod_40_word_on_write | ld_mod_40_word_on_read;
>
>
> wire ld_last_blk_of_read_xfer = blk_read_sequence_q[0] & (pci_dword_fetch_ctr[10:0] < 11'h040);
> wire start_of_read_seq = pci_dc_block_cnt_ld & ~pci_dc_sdram_wrdata[30];
> wire initiate_blk_read = start_of_read_seq | (end_of_read_blk_handle_q & ~(pci_dword_fetch_ctr == 11'h000));
> wire sdram_blk_rd_done_led = ~sdram_block_read_done_q[1] & sdram_block_read_done_q[0];
> wire sdram_blk_wr_done_led = ~sdram_block_write_done_q[1] & sdram_block_write_done_q[0];
>
> assign dc_pci_block_write_done = sdram_blk_wr_done_led;
>
> always @(posedge clk_33mhz)
> begin
> dc_pci_sdram_rddata <= ~pci_port_add_ctr[0] ? pci_upper32_hr : sdram_fifo_rd_data[31:0];
> pci_block_write_read_n <= pci_dc_block_cnt_ld ? pci_dc_sdram_wrdata[30] : pci_block_write_read_n; // xfer direction control
> pci_low32_hr <= (pci_dc_sdram_fifo_ld & ~pci_port_add_ctr[0]) ? {pci_dc_sdram_wrdata[31:0]} : pci_low32_hr;
> pci_upper32_hr <= (pci_dc_sdram_fifo_rdnxt & pci_port_add_ctr[0]) ? sdram_fifo_rd_data[63:32] : pci_upper32_hr;
> local_pci_dat_hr <= local_pci_hr_wr ? pci_dc_sdram_wrdata : local_pci_dat_hr;
> pci_dc_start_add_ld_q <= pci_dc_start_add_ld;
> pci_dc_block_cnt_ld_q <= pci_dc_block_cnt_ld;
> ld_last_word_of_xfer_q <= ld_last_word_of_xfer;
> ld_modulo_40_word_q <= ld_modulo_40_word;
> pci_inc_block_ctr_q <= (ld_last_word_of_xfer | ld_modulo_40_word);
> sdram_block_write_done_q <= {sdram_block_write_done_q[0], block_write_done};
> sdram_block_read_done_q <= {sdram_block_read_done_q[0], block_read_done};
> pci_blkxer_ctr_tc_q <= {pci_blkxer_ctr_tc_q[0], (pci_block_transfer_ctr == 11'h000)};
> dc_pci_set_blkxfer_int <= pci_block_write_read_n ? sdram_blk_wr_done_led : pci_blkxer_ctr_tc_q_led;
> dc_pci_block_rd_done <= block_read_done;
> fifo_room_for_40h_q <= fifo_room_for_40h;
> decrement_by_40_on_read <= (pci_40_dword_detect_ctr == 7'h7F) & pci_wr_rd_cycle & ~pci_block_write_read_n;
> blk_read_sequence_q <= {blk_read_sequence_q[1:0], initiate_blk_read};
> end_of_read_blk_handle_q <= sdram_blk_rd_done_led;
> end
>
> always @(posedge clk_33mhz)
> begin
> if (~ck_pci_reset_n)
> pci_block_transfer_ctr <= 11'h000;
> else if (pci_dc_block_cnt_ld)
> pci_block_transfer_ctr <= {pci_dc_sdram_wrdata[9:0], 1'b0};
> else if (pci_wr_rd_cycle)
> pci_block_transfer_ctr <= pci_block_transfer_ctr - 1'b1;
> end
>
> always @(posedge clk_33mhz)
> begin
> if (~ck_pci_reset_n | pci_dc_block_cnt_ld)
> pci_port_add_ctr <= 9'h000;
> else if (pci_wr_rd_cycle)
> pci_port_add_ctr <= pci_port_add_ctr + 1'b1;
> end
>
> always @(posedge clk_33mhz)
> begin
> if (~ck_pci_reset_n )
> pci_dwrd_ctr <= 7'h00;
> else if (ld_modulo_40_word_q)
> pci_dwrd_ctr <= 7'h40;
> else if (ld_last_word_of_xfer_q)
> pci_dwrd_ctr <= {1'b0, pci_port_add_ctr[6:1]};
> else if (ld_last_blk_of_read_xfer)
> pci_dwrd_ctr <= pci_dword_fetch_ctr[6:0];
> end
>
> always @(posedge clk_33mhz)
> begin
> if (~ck_pci_reset_n)
> pci_dword_fetch_ctr <= 11'h000;
> else if (pci_dc_block_cnt_ld)
> pci_dword_fetch_ctr <= pci_dc_sdram_wrdata[10:0];
> else if (sdram_blk_rd_done_led) // on read block done decrement
> pci_dword_fetch_ctr <= pci_dword_fetch_ctr - pci_dwrd_ctr;
> end
>
> always @(posedge clk_33mhz)
> begin
> if (~ck_pci_reset_n | pci_dc_block_cnt_ld)
> pci_40_dword_detect_ctr <= 7'h00;
> else if (pci_wr_rd_cycle & ~pci_block_write_read_n) //
> pci_40_dword_detect_ctr <= pci_40_dword_detect_ctr + 1'b1;
> end
>
> // ********************************************************************
> // PDCLK Domain
> // ********************************************************************
> reg debug_write_last;
>
> reg pending_read_block_req;
> reg [1:0] srbr_q, start_add_ld_q, block_cnt_ld_q, inc_block_ctr_q;
> reg [1:0] inc_block_ctr_led_q;
> reg [6:0] inc_value_reg;
> reg [8:0] sdram_fifo_depth_ctr;
> reg [9:0] dword_blk_cnt_ctr;
> reg [1:0] dword_blk_cnt_ctr_tc_q;
>
> wire sdram_write_for_pci, sdram_read_for_pci;
> wire serve_pci_write_blk, serve_pci_read_blk;
>
> wire set_rbr = ~srbr_q[1] & srbr_q[0];
> wire start_add_ld_led = ~start_add_ld_q[1] & start_add_ld_q[0];
> wire block_cnt_ld_led = ~block_cnt_ld_q[1] & block_cnt_ld_q[0];
> wire inc_block_ctr_led = ~inc_block_ctr_q[1] & inc_block_ctr_q[0];
> wire dec_by_40_on_read_led = ~dec_by_40_on_read_q[1] & dec_by_40_on_read_q[0];
> wire sdram_event_for_pci = (sdram_write_for_pci | sdram_read_for_pci);
> wire sdram_fifo_depth_ctr_tc = (sdram_fifo_depth_ctr == 9'h000);
> wire dword_blk_cnt_ctr_tc = (dword_blk_cnt_ctr == 10'h000);
> wire dword_blk_cnt_ctr_tc_led = ~dword_blk_cnt_ctr_tc_q[1] & dword_blk_cnt_ctr_tc_q[0];
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> sdram_fifo_drport_wr_data <= xt_dc_sdram_dq_in;
> pipeline_rddata_val_q <= {pipeline_rddata_val_q[6:0], pipeline_rddata_val};
> debug_write_last <= (pci_mode_blk_wr_rd_n & ~dram_iq_semaphore & sblk_xfer_cnt_dec | ~pci_mode_blk_wr_rd_n & ~dram_iq_semaphore & pipeline_rddata_val_q[7]);
> dram_debug <= {
> // pci_blkxer_ctr_tc_q[0], dc_pci_set_blkxfer_int,
> // pci_read_block_req, pci_write_block_rdy,dram_seq_state, 1'b0, // 9 48
> // bwr_done_led, start_add_ld_q[0], block_cnt_ld_q[0], inc_block_ctr_q[0], // 4
> // inc_block_ctr_led_q, // 1 inc_value_reg,
> // sdram_block_transfer_ctr[8:0], // 9
> // ld_last_word_of_xfer_q, ld_modulo_40_word_q, 1'b0, dram_seq_state, // pci_dwrd_ctr,
> // pci_blkxer_ctr_tc_q_led, // 1 39 sdram_fifo_drport_add_ctr[7:0],
> // 4'h0, block_cnt_ld_led, pci_dc_sdram_fifo_ld, // 6 38
> // dc_pci_set_blkxfer_int, pci_mode_blk_wr_rd_n, // 2 32 sdram_fifo_depth_ctr
> // pci_dc_block_cnt_ld, pci_block_transfer_ctr, // 12 30
> // inc_block_ctr_led_q[1], sdram_fifo_depth_ctr[8:0], // 10 18
> // inc_block_ctr_led_q[0], inc_value_reg[6:0] // 8
> 2'b00, dram_seq_state, // 8 48
> fifo_room_for_40h_q, 1'b0, decrement_by_40_on_read, // 3 40
> blk_read_sequence_q[2], end_of_read_blk_handle_q, pending_read_block_req, // 3 37
> dec_by_40_on_read_q[1], fifo_room_for_40h, // 2 34
> pci_dc_block_cnt_ld, pci_block_transfer_ctr, // 12 32
> pci_read_block_req, dec_by_40_on_read_led, sdram_read_for_pci, sdram_fifo_depth_ctr[8:0], // 12 20
> set_rbr, inc_value_reg[6:0] // 8
>
> // pci_port_add_ctr[8:1],
> // sdram_fifo_rd_data[15:0]
>
> };
> pending_read_block_req <= set_rbr | (pending_read_block_req & clk_ad9857_pd_drate_stable & ~(pipeline_rddata_val & ~dram_iq_semaphore));
> pci_read_block_req <= pending_read_block_req & fifo_room_for_40h & ~(pipeline_rddata_val & ~dram_iq_semaphore);
> pci_write_block_rdy <= ~sdram_fifo_depth_ctr_tc & pci_mode_blk_wr_rd_n;
> pci_mode_blk_wr_rd_n <= pci_block_write_read_n;
> srbr_q <= { srbr_q[0], blk_read_sequence_q[2]};
> start_add_ld_q <= { start_add_ld_q[0], pci_dc_start_add_ld_q };
> block_cnt_ld_q <= { block_cnt_ld_q[0], pci_dc_block_cnt_ld_q };
> inc_block_ctr_q <= { inc_block_ctr_q[0], pci_inc_block_ctr_q };
> inc_block_ctr_led_q <= {inc_block_ctr_led_q[0], inc_block_ctr_led};
> dec_by_40_on_read_q <= {dec_by_40_on_read_q[0], decrement_by_40_on_read};
> inc_value_reg <= (set_rbr | inc_block_ctr_led_q[0]) ? pci_dwrd_ctr : inc_value_reg;
> fifo_room_for_40h <= ~sdram_fifo_depth_ctr[7] | ~sdram_fifo_depth_ctr[6];
> dword_blk_cnt_ctr_tc_q <= {dword_blk_cnt_ctr_tc_q[0], dword_blk_cnt_ctr_tc};
> end
>
> // reg [15:0] blk_cnt_ld_ctr, set_int_ctr;
> // assign dc_pci_ctr_debug = {blk_cnt_ld_ctr, set_int_ctr};
> reg [31:0] blk_cnt_ld_ctr, set_int_ctr;
> assign dc_pci_debug_1 = blk_cnt_ld_ctr;
> assign dc_pci_debug_2 = set_int_ctr;
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> if (~clk_ad9857_pd_drate_stable)
> blk_cnt_ld_ctr <= 32'h0000;
> // else if (block_cnt_ld_led)
> else if (pci_mode_blk_wr_rd_n & ~dram_iq_semaphore & sblk_xfer_cnt_dec)
> blk_cnt_ld_ctr <= blk_cnt_ld_ctr + 1'b1;
> end
>
> // always @(posedge clk_ad9857_pd_drate)
> always @(posedge clk_33mhz)
> begin
> if (~clk_ad9857_pd_drate_stable)
> set_int_ctr <= 32'h0000;
> // else if (( bwr_done_q[0] | brd_done_q[0]) & pci_blkxer_ctr_tc_q[0])
> else if (pci_blkxer_ctr_tc_q_led)
> // else if (pci_wr_rd_cycle)
> set_int_ctr <= set_int_ctr + 1'b1;
> end
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> if (~clk_ad9857_pd_drate_stable | block_cnt_ld_led)
> sdram_fifo_depth_ctr <= 9'h000;
> else if (inc_block_ctr_led_q[1] & sdram_write_for_pci & pci_mode_blk_wr_rd_n)
> sdram_fifo_depth_ctr <= sdram_fifo_depth_ctr + inc_value_reg - 1'b1;
> else if (inc_block_ctr_led_q[1] & ~sdram_write_for_pci & pci_mode_blk_wr_rd_n)
> sdram_fifo_depth_ctr <= sdram_fifo_depth_ctr + inc_value_reg;
> else if (~inc_block_ctr_led_q[1] & sdram_write_for_pci & pci_mode_blk_wr_rd_n)
> sdram_fifo_depth_ctr <= sdram_fifo_depth_ctr - 1'b1 ;
> else if (dec_by_40_on_read_led & sdram_read_for_pci & ~pci_mode_blk_wr_rd_n)
> sdram_fifo_depth_ctr <= sdram_fifo_depth_ctr - 7'h3F ;
> else if (dec_by_40_on_read_led & ~sdram_read_for_pci & ~pci_mode_blk_wr_rd_n)
> sdram_fifo_depth_ctr <= sdram_fifo_depth_ctr - 7'h40 ;
> else if (~dec_by_40_on_read_led & sdram_read_for_pci & ~pci_mode_blk_wr_rd_n)
> sdram_fifo_depth_ctr <= sdram_fifo_depth_ctr + 7'h01 ;
> end
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> if (~clk_ad9857_pd_drate_stable)
> sdram_start_address_reg <= 27'h000_0000;
> else if (start_add_ld_led)
> sdram_start_address_reg <= local_pci_dat_hr[29:3];
> else if (sdram_event_for_pci )
> sdram_start_address_reg <= sdram_start_address_reg + 1'b1 ;
> end
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> if (~clk_ad9857_pd_drate_stable)
> sdram_block_transfer_ctr <= 9'h000;
> else if (serve_pci_write_blk)
> sdram_block_transfer_ctr <= sdram_fifo_depth_ctr;
> else if (serve_pci_read_blk)
> sdram_block_transfer_ctr <= {2'b00, inc_value_reg};
> else if (sdram_event_for_pci)
> sdram_block_transfer_ctr <= sdram_block_transfer_ctr - 1'b1;
> end
>
> reg sdram_write_for_pci_q;
> always @(posedge clk_ad9857_pd_drate)
> begin
> sdram_write_for_pci_q <= sdram_write_for_pci;
> end
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> if (~clk_ad9857_pd_drate_stable | block_cnt_ld_led )
> sdram_fifo_drport_add_ctr <= 8'h00;
> else if (sdram_write_for_pci_q |
> ~pci_mode_blk_wr_rd_n & ~dram_iq_semaphore & pipeline_rddata_val_q[7])
> sdram_fifo_drport_add_ctr <= sdram_fifo_drport_add_ctr + 1'b1;
> end
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> if (~clk_ad9857_pd_drate_stable | block_cnt_ld_led)
> dword_blk_cnt_ctr <= pci_block_transfer_ctr[10:1];
> else if (sdram_write_for_pci)
> dword_blk_cnt_ctr <= dword_blk_cnt_ctr - 1'b1;
> end
>
>
> RAMB4_S16_S16 sdram_fifo_bits15_00 ( // 256x16
> .CLKA (clk_33mhz), // Port A - PCI side
> .RSTA (1'b0),
> .WEA (sdram_fifo_pci_wr),
> .ENA (1'b1),
> .ADDRA (pci_port_add_ctr[8:1]),
> .DIA (sdram_fifo_wr_data[15:0]),
> .DOA (sdram_fifo_rd_data[15:0]),
> .CLKB (clk_ad9857_pd_drate),
> .RSTB (1'b0),
> .WEB (~dram_iq_semaphore & pipeline_rddata_val_q[7]),
> .ENB (1'b1),
> .ADDRB (sdram_fifo_drport_add_ctr),
> .DIB (sdram_fifo_drport_wr_data[15:0]),
> .DOB (sdram_fifo_drport_rd_data[15:0])
> );
>
> RAMB4_S16_S16 sdram_fifo_bits31_16 ( // 256x16
> .CLKA (clk_33mhz), // Port A - PCI side
> .RSTA (1'b0),
> .WEA (sdram_fifo_pci_wr),
> .ENA (1'b1),
> .ADDRA (pci_port_add_ctr[8:1]),
> .DIA (sdram_fifo_wr_data[31:16]),
> .DOA (sdram_fifo_rd_data[31:16]),
> .CLKB (clk_ad9857_pd_drate),
> .RSTB (1'b0),
> .WEB (~dram_iq_semaphore & pipeline_rddata_val_q[7]),
> .ENB (1'b1),
> .ADDRB (sdram_fifo_drport_add_ctr),
> .DIB (sdram_fifo_drport_wr_data[31:16]),
> .DOB (sdram_fifo_drport_rd_data[31:16])
> );
>
> RAMB4_S16_S16 sdram_fifo_bits47_32 ( // 256x16
> .CLKA (clk_33mhz), // Port A - PCI side
> .RSTA (1'b0),
> .WEA (sdram_fifo_pci_wr),
> .ENA (1'b1),
> .ADDRA (pci_port_add_ctr[8:1]),
> .DIA (sdram_fifo_wr_data[47:32]),
> .DOA (sdram_fifo_rd_data[47:32]),
> .CLKB (clk_ad9857_pd_drate),
> .RSTB (1'b0),
> .WEB (~dram_iq_semaphore & pipeline_rddata_val_q[7]),
> .ENB (1'b1),
> .ADDRB (sdram_fifo_drport_add_ctr),
> .DIB (sdram_fifo_drport_wr_data[47:32]),
> .DOB (sdram_fifo_drport_rd_data[47:32])
> );
>
> RAMB4_S16_S16 sdram_fifo_bits63_48 ( // 256x16
> .CLKA (clk_33mhz), // Port A - PCI side
> .RSTA (1'b0),
> .WEA (sdram_fifo_pci_wr),
> .ENA (1'b1),
> .ADDRA (pci_port_add_ctr[8:1]),
> .DIA (sdram_fifo_wr_data[63:48]),
> .DOA (sdram_fifo_rd_data[63:48]),
> .CLKB (clk_ad9857_pd_drate),
> .RSTB (1'b0),
> .WEB (~dram_iq_semaphore & pipeline_rddata_val_q[7]),
> .ENB (1'b1),
> .ADDRB (sdram_fifo_drport_add_ctr),
> .DIB (sdram_fifo_drport_wr_data[63:48]),
> .DOB (sdram_fifo_drport_rd_data[63:48])
> );
> // ********************************************************************
> // IQ Unpack RD SDRAM Interface
> // ********************************************************************
> reg [7:0] iq_gated_rddata_val_q;
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> get_next_blk_q <= du_dc_get_next_blk;
> iq_gated_rddata_val_q <= {iq_gated_rddata_val_q[6:0], dram_iq_semaphore & pipeline_rddata_val};
> dc_du_wr_next_line <= iq_gated_rddata_val_q[7];
> dc_du_next_line_data <= sdram_fifo_drport_wr_data;
> dc_du_reset_gnb <= dram_iq_semaphore;
> end
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> if (~clk_ad9857_pd_drate_stable)
> iq_unpack_block_transfer_ctr <= 8'h00;
> else if (get_next_blk_led)
> iq_unpack_block_transfer_ctr <= du_dc_blk_size;
> else if (sblk_xfer_cnt_dec & dram_iq_semaphore)
> iq_unpack_block_transfer_ctr <= iq_unpack_block_transfer_ctr - 1'b1;
> end
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> if (~clk_ad9857_pd_drate_stable)
> iq_unpack_start_address_reg <= 27'h000_0000;
> else if (get_next_blk_led)
> iq_unpack_start_address_reg <= du_dc_blk_start_add[29:3];
> else if (sblk_xfer_cnt_dec & dram_iq_semaphore)
> iq_unpack_start_address_reg <= iq_unpack_start_address_reg + 1'b1 ;
> end
>
>
> // ********************************************************************
> // SDRAM Control State Machine
> // ********************************************************************
> parameter DRAM_DELAY_100_US = 13'h1900; // actually about 102.4 us
> parameter DRAM_DELAY_TMRD = 13'h0002; // delay from mode reg load to active
> parameter DRAM_DELAY_TRCD = 13'h0002; // delay from active to WRITE
> parameter DRAM_DELAY_TRP = 13'h0001; // delay from precharge to autorefresh
> parameter DRAM_DELAY_TRFC = 13'h0004; // delay from autorefresh to active
> // DRAM control states
> parameter DRAM_COMMAND_INHIBIT = 4'b1000; // 8H
> parameter DRAM_NOP = 4'b0111; // 7H
> parameter DRAM_ACTIVE = 4'b0011; // 3H
> parameter DRAM_READ = 4'b0101; // 5H
> parameter DRAM_WRITE = 4'b0100; // 4H
> parameter DRAM_BURST_TERMINATE = 4'b0110; // 6H
> parameter DRAM_PRECHARGE = 4'b0010; // 2H
> parameter DRAM_AUTO_REFRESH = 4'b0001; // 1H
> parameter DRAM_LOAD_MODE_REG = 4'b0000; // 0H
>
> // DRAM states definitions
> parameter DRAM_INIT_0 = 6'h00;
> parameter DRAM_100US_NOP_0 = 6'h01;
> parameter DRAM_PRECHARGE_ALL_0 = 6'h02;
> parameter DRAM_PRECHARGE_ALL_1 = 6'h03;
> parameter DRAM_AUTOREFRESH_0 = 6'h04;
> parameter DRAM_AUTOREFRESH_1 = 6'h05;
> parameter DRAM_MODEREG_WR_0 = 6'h06;
> parameter DRAM_MODEREG_WR_1 = 6'h07;
> parameter DRAM_IDLE_0 = 6'h08;
> parameter DRAM_WRLOOP_0 = 6'h0B;
> parameter DRAM_WRLOOP_1 = 6'h0C;
> parameter DRAM_WRLOOP_2 = 6'h0D;
> parameter DRAM_WRLOOP_3 = 6'h0E;
> parameter DRAM_WRLOOP_4 = 6'h0F;
> parameter DRAM_RDLOOP_0 = 6'h11;
> parameter DRAM_RDLOOP_1 = 6'h12;
> parameter DRAM_RDLOOP_2 = 6'h13;
> parameter DRAM_RDLOOP_3 = 6'h14;
> parameter DRAM_RDLOOP_4 = 6'h15;
> parameter DRAM_AUTOREFRESH_OP_0 = 6'h16;
> parameter DRAM_AUTOREFRESH_OP_1 = 6'h17;
>
> assign sdram_write_for_pci = ((dram_seq_state == DRAM_WRLOOP_2));
> assign sdram_read_for_pci = ((dram_seq_state == DRAM_RDLOOP_2) & ~sblk_xfer_cnt_tc);
> assign serve_pci_write_blk = (dram_seq_state == DRAM_IDLE_0) & ~du_dc_get_next_blk & pci_write_block_rdy;
> assign serve_pci_read_blk = (dram_seq_state == DRAM_IDLE_0) & ~du_dc_get_next_blk & pci_read_block_req;
> assign sblk_xfer_cnt_dec = (((dram_seq_state == DRAM_WRLOOP_2) & ~sblk_xfer_cnt_tc) |
> (dram_seq_state == DRAM_RDLOOP_2) & (dram_iq_semaphore ? ~iq_unpack_xfer_cnt_tc : ~sblk_xfer_cnt_tc));
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> bwr_done_q <= {bwr_done_q[0], dword_blk_cnt_ctr_tc_led};
> brd_done_q <= {brd_done_q[0], (dram_seq_state == DRAM_RDLOOP_4) & ( dram_delay_ctr == 13'h0000) & ~dram_iq_semaphore} ;
> clr_dram_afc <= (dram_ctl == DRAM_AUTO_REFRESH);
> dram_afc_tc_q <= dram_auto_refresh_ctr_tc;
> dc_pci_init_done <= ((dram_seq_state == DRAM_IDLE_0) | dc_pci_init_done) & clk_ad9857_pd_drate_stable;
> block_write_done <= | bwr_done_q; // pulse stretch
> block_read_done <= | brd_done_q; // pulse stretch
> end
> // DAC RAM Bank Select
>
> always @(posedge clk_ad9857_pd_drate)
> begin
> if (~clk_ad9857_pd_drate_stable)
> dram_auto_refresh_ctr <= DLY_7US_AT_PDCLK;
> else if (clr_dram_afc)
> dram_auto_refresh_ctr <= 9'h000;
> else if (~dram_auto_refresh_ctr_tc)
> dram_auto_refresh_ctr <= dram_auto_refresh_ctr + 1'b1;
> end
>
> always @ (posedge clk_ad9857_pd_drate)
> begin
> if (~clk_ad9857_pd_drate_stable) begin
> dram_seq_state <= DRAM_INIT_0;
> dram_delay_ctr <= DRAM_DELAY_100_US;
> dram_ctl <= DRAM_COMMAND_INHIBIT;
> sdram_256mb_id <= 4'hF;
> sdram_ba <= 2'b00;
> sdram_a <= 13'h0000;
> dram_loopcnt <= 8'h00;
> pipeline_rddata_val <= 1'b0;
> dram_ctl_wr_blk_done <= 1'b0;
> dram_iq_semaphore <= 1'b0;
> end
> else begin
> case(dram_seq_state)
> DRAM_INIT_0 : begin
> dram_seq_state <= DRAM_100US_NOP_0;
> dram_delay_ctr <= DRAM_DELAY_100_US;
> dram_ctl <= DRAM_COMMAND_INHIBIT;
> sdram_256mb_id <= 4'hF;
> sdram_ba <= 2'b00;
> sdram_a <= 13'h0000;
> dram_loopcnt <= 8'h00;
> pipeline_rddata_val <= 1'b0;
> dram_ctl_wr_blk_done <= 1'b0;
> dram_iq_semaphore <= 1'b0;
> end
> DRAM_100US_NOP_0 : begin
> if ( dram_delay_ctr == 13'h0000) begin
> dram_seq_state <= DRAM_PRECHARGE_ALL_0;
> end
> else begin
> dram_seq_state <= DRAM_100US_NOP_0;
> dram_delay_ctr <= dram_delay_ctr - 1;
> end
> end
> DRAM_PRECHARGE_ALL_0 : begin
> dram_seq_state <= DRAM_PRECHARGE_ALL_1;
> dram_ctl <= DRAM_PRECHARGE;
> sdram_a <= 13'h0400;
> dram_delay_ctr <= DRAM_DELAY_TRP;
> end
> DRAM_PRECHARGE_ALL_1 : begin
> dram_ctl <= DRAM_NOP;
> sdram_a <= 13'h0000;
> if ( dram_delay_ctr == 13'h0000) begin
> dram_seq_state <= DRAM_AUTOREFRESH_0;
> dram_loopcnt <= 8'h01;
> end
> else begin
> dram_seq_state <= DRAM_PRECHARGE_ALL_1;
> dram_delay_ctr <= dram_delay_ctr-1;
> end
> end
> DRAM_AUTOREFRESH_0 : begin
> dram_seq_state <= DRAM_AUTOREFRESH_1;
> dram_ctl <= DRAM_AUTO_REFRESH;
> dram_delay_ctr <= DRAM_DELAY_TRFC;
> end
> DRAM_AUTOREFRESH_1 : begin
> dram_ctl <= DRAM_NOP;
> if ( dram_delay_ctr == 13'h0000)
> if ( dram_loopcnt == 8'h00)
> dram_seq_state <= DRAM_MODEREG_WR_0;
> else begin
> dram_seq_state <= DRAM_AUTOREFRESH_0;
> dram_loopcnt <= dram_loopcnt-1;
> end
> else begin
> dram_seq_state <= DRAM_AUTOREFRESH_1;
> dram_delay_ctr <= dram_delay_ctr-1;
> end
> end
> DRAM_MODEREG_WR_0 : begin
> dram_seq_state <= DRAM_MODEREG_WR_1;
> dram_ctl <= DRAM_LOAD_MODE_REG;
> sdram_a <= 13'h0230;
> dram_delay_ctr <= DRAM_DELAY_TMRD;
> end
> DRAM_MODEREG_WR_1 : begin
> dram_ctl <= DRAM_NOP;
> sdram_a <= 13'h0000;
> if (dram_delay_ctr == 13'h0000) begin
> dram_seq_state <= DRAM_IDLE_0;
> end
> else begin
> dram_seq_state <= DRAM_MODEREG_WR_1;
> dram_delay_ctr <= dram_delay_ctr-1;
> end
> end
> DRAM_IDLE_0 : begin
> sdram_256mb_id <= 4'h0;
> if (du_dc_get_next_blk) begin
> dram_iq_semaphore <= 1'b1;
> dram_seq_state <= DRAM_RDLOOP_0;
> end
> else if (pci_write_block_rdy)
> dram_seq_state <= DRAM_WRLOOP_0;
> else if (pci_read_block_req)
> dram_seq_state <= DRAM_RDLOOP_0;
> else if (dram_afc_tc_q)
> dram_seq_state <= DRAM_AUTOREFRESH_OP_0;
> end
> DRAM_WRLOOP_0 : begin
> dram_seq_state <= DRAM_WRLOOP_1;
> dram_ctl <= DRAM_ACTIVE;
> sdram_ba <= sdram_start_address_reg[27:26];
> sdram_a <= sdram_start_address_reg[25:13];
> dram_delay_ctr <= DRAM_DELAY_TRCD;
> case(sdram_start_address_reg[29:28])
> 2'b00 : begin sdram_256mb_id <= 4'h1; end
> 2'b01 : begin sdram_256mb_id <= 4'h2; end
> 2'b10 : begin sdram_256mb_id <= 4'h4; end
> 2'b11 : begin sdram_256mb_id <= 4'h8; end
> endcase
> end
> DRAM_WRLOOP_1 : begin
> dram_ctl <= DRAM_NOP;
> if (dram_delay_ctr == 13'h0000) begin
> dram_seq_state <= DRAM_WRLOOP_2;
> end
> else begin
> dram_seq_state <= DRAM_WRLOOP_1;
> dram_delay_ctr <= dram_delay_ctr-1;
> end
> end
> DRAM_WRLOOP_2 : begin
> dram_ctl <= DRAM_WRITE;
> sdram_a <= {3'b000, sdram_start_address_reg[12:3]};
> dram_seq_state <= sblk_xfer_cnt_tc ? DRAM_WRLOOP_3 : DRAM_WRLOOP_2;
> end
> DRAM_WRLOOP_3 : begin // post-WRITE burst precharge
> dram_seq_state <= DRAM_WRLOOP_4;
> dram_ctl <= DRAM_PRECHARGE;
> sdram_a <= 13'h0400;
> dram_delay_ctr <= DRAM_DELAY_TRP;
> dram_ctl_wr_blk_done <= 1'b1;
> end
> DRAM_WRLOOP_4 : begin
> dram_ctl <= DRAM_NOP;
> sdram_a <= 13'h0000;
> dram_ctl_wr_blk_done <= 1'b0;
> if ( dram_delay_ctr == 13'h0000) begin
> dram_seq_state <= DRAM_IDLE_0;
> end
> else begin
> dram_seq_state <= DRAM_WRLOOP_4;
> dram_delay_ctr <= dram_delay_ctr-1;
> end
> end
> DRAM_RDLOOP_0 : begin
> dram_seq_state <= DRAM_RDLOOP_1;
> dram_ctl <= DRAM_ACTIVE;
> sdram_ba <= dram_iq_semaphore ? iq_unpack_start_address_reg[27:26] : sdram_start_address_reg[27:26];
> sdram_a <= dram_iq_semaphore ? iq_unpack_start_address_reg[25:13] : sdram_start_address_reg[25:13];
> dram_delay_ctr <= DRAM_DELAY_TRCD;
> case(dram_iq_semaphore ? iq_unpack_start_address_reg[29:28] : sdram_start_address_reg[29:28])
> 2'b00 : begin sdram_256mb_id <= 4'h1; end
> 2'b01 : begin sdram_256mb_id <= 4'h2; end
> 2'b10 : begin sdram_256mb_id <= 4'h4; end
> 2'b11 : begin sdram_256mb_id <= 4'h8; end
> endcase
> end
> DRAM_RDLOOP_1 : begin
> dram_ctl <= DRAM_NOP;
> if (dram_delay_ctr == 13'h0000) begin
> dram_seq_state <= DRAM_RDLOOP_2;
> pipeline_rddata_val <= 1'b1;
> end
> else begin
> dram_seq_state <= DRAM_RDLOOP_1;
> dram_delay_ctr <= dram_delay_ctr-1;
> end
> end
> DRAM_RDLOOP_2 : begin
> dram_ctl <= DRAM_READ;
> sdram_a <= {3'b000, (dram_iq_semaphore ? iq_unpack_start_address_reg[12:3] : sdram_start_address_reg[12:3])};
> if (dram_iq_semaphore ? iq_unpack_xfer_cnt_tc : sblk_xfer_cnt_tc) begin
> dram_seq_state <= DRAM_RDLOOP_3;
> pipeline_rddata_val <= 1'b0;
> end
> else begin
> dram_seq_state <= DRAM_RDLOOP_2;
> pipeline_rddata_val <= 1'b1;
> end
> end
> DRAM_RDLOOP_3 : begin // post-READ burst precharge
> pipeline_rddata_val <= 1'b0;
> dram_seq_state <= DRAM_RDLOOP_4;
> dram_ctl <= DRAM_PRECHARGE;
> sdram_a <= 13'h0400;
> dram_delay_ctr <= DRAM_DELAY_TRP;
> end
> DRAM_RDLOOP_4 : begin
> dram_ctl <= DRAM_NOP;
> sdram_a <= 13'h0000;
> if ( dram_delay_ctr == 13'h0000) begin
> dram_seq_state <= DRAM_IDLE_0;
> dram_iq_semaphore <= 1'b0;
> end
> else begin
> dram_seq_state <= DRAM_RDLOOP_4;
> dram_delay_ctr <= dram_delay_ctr-1;
> end
> end
> DRAM_AUTOREFRESH_OP_0 : begin
> dram_seq_state <= DRAM_AUTOREFRESH_OP_1;
> dram_ctl <= DRAM_AUTO_REFRESH;
> dram_delay_ctr <= DRAM_DELAY_TRFC;
> sdram_256mb_id <= 4'hF;
> end
> DRAM_AUTOREFRESH_OP_1 : begin
> dram_ctl <= DRAM_NOP;
> if ( dram_delay_ctr == 13'h0000)
> dram_seq_state <= DRAM_IDLE_0;
> else begin
> dram_seq_state <= DRAM_AUTOREFRESH_OP_1;
> dram_delay_ctr <= dram_delay_ctr-1;
> end
> end
> endcase
> end
> end
>
Article: 128615On Jan 31, 5:21 pm, Marlboro <cco...@netscape.net> wrote: > Hi all, > > Has anyone ever tried to improve the security for the old Xilinx FPGA > devices, which doesn't have the 3-DES encryption? If so what's the > feasible approach ? So far I have no clue > > TIA, We have used this great solution : http://www.maxim-ic.com/appnotes.cfm/an_pk/3826 This is a generic solution, not dedicated to any FPGA maker ! Regards, Laurent http://www.amontec.comArticle: 128616
Interesting. I am definitely behind in the times for fpga security. "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:fnt5lb$2h72@cnn.xsj.xilinx.com... > RCIngham wrote: >>> Hi all, >>> >>> Has anyone ever tried to improve the security for the old Xilinx FPGA >>> devices, which doesn't have the 3-DES encryption? If so what's the >>> feasible approach ? So far I have no clue >>> >>> TIA, >>> >> >> I am not a Xilinx expert, but I think the answer is "cannot be done". Use >> something else if you don't want the bitstream snooped upon. >> > Actually there are alternatives using external and/or internal features. > This is marketing piece, but informative on the subject: > http://www.xilinx.com/publications/prod_mktg/DesignSecurity_ssht.pdf > > And this white paper describes how to implement a CipherStream protocol: > http://www.xilinx.com/support/documentation/white_papers/wp197.pdf > > An application note for copy protection using a secure EEPROM: > http://www.xilinx.com/support/documentation/application_notes/xapp780.pdf > > And this landing page holds a whole lot more on this subject: > http://www.xilinx.com/products/design_resources/security/ > > Ed McGettigan > -- > Xilinx Inc.Article: 128617
I'm implementing a 36 bit x 36 bit multiplier with a 72 bit output in a Xilinx Spartan 3E. I've tried to poke down into the RTL schematic, but I'm unable to push down into the multiplier block. Could you please explain architecturally why this requires 9 multipliers? Thanks, DaleArticle: 128618
Vagant <vladimir.v.korostelev@rambler.ru> wrote: >Hello All, > >I am curious what are main applications of FPGA in >Telecommunications? > >It's well known (well, at least for some smart chaps :) ) that DSPs >(Digital Signal Processing Systems) can be implemented on FPGAs, but >what about their use in Telecommunications? > >What are main directions, nowdays, for applications of FPGAs in >telecommunications? One company I worked for is leading in voice recorder technology. In order to support a broad range of different telephone sets with the same hardware they use FPGAs. Every switch manufacturer uses a different proprietary protocol which needs to be dissected to retrieve audio and dialed numbers. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 128619
On Jan 31, 3:04 pm, Dale <dale.prat...@gmail.com> wrote: > I'm implementing a 36 bit x 36 bit multiplier with a 72 bit output in > a Xilinx Spartan 3E. I've tried to poke down into the RTL schematic, > but I'm unable to push down into the multiplier block. > > Could you please explain architecturally why this requires 9 > multipliers? > > Thanks, > Dale Just a guess, but I imagine the multipliers are signed 18x18, so you can't use all 18 bits when you try to extend them?Article: 128620
On Jan 31, 11:44 am, Charles Wagner <charles.wag...@irisa.fr> wrote: > Hi All, > > I am trying to see the power consumption of some design using XPower > with ModelSim generated .vcd file > > I get this message : > WARNING:Power:1087 - Can't change frequency of net clk to 100.00Mhz > It sets the clock frequency automatically to 10 MHz irrespective of what > I use in my simulation. > > Is it a problem related to the option that I used to generate the VCD > file? Anybody got same experience? > > Thanks, > > Charles This warning seemed familiar, so I searched the Xilinx forums, and it would seem you're not alone. Unfortunately no one answered the question on that thread... http://forums.xilinx.com/xlnx/board/message?board.id=ISE&message.id=750&query.id=21375#M750 Regards, GaborArticle: 128621
Nico Coesel schrieb: >> What are main directions, nowdays, for applications of FPGAs in >> telecommunications? I did a redesign once, where a bunch of ICs where completely replaced by one single, not even medium size FPGA. The boards was something like an A4 sheet, with two ASCIs, twos Altera FPGAs (Flex10K) and a Xilinx FPGA (XC2S30). This board was redesigned before, since some ICs went out of production. After this second (and last) redesign, ICs with a proce of ~400 Euro were replaces by a single 20 Euro FPGA, a Cyclone. ;-) Regards FalkArticle: 128622
U can't get security within chips that are provided for the mass market. everyone who has at least $10000 can backengineer these. It's better to work on own solutions. Marlboro schrieb: > Hi all, > > Has anyone ever tried to improve the security for the old Xilinx FPGA > devices, which doesn't have the 3-DES encryption? If so what's the > feasible approach ? So far I have no clue > > TIA,Article: 128623
Dave Pollum schrieb: > On Jan 31, 9:47 am, waltherz <walther.za...@gmx.de> wrote: > > Hello all, > > > > i have a design finished a few month ago, that is working fine on a > > xc2s200-pq208, but when i port it to a xc3s400-tq144, it ain't work > > most of the time (depends on the synthesis process) even with lowest > > frequencies for a single clock and a given period constraint. > > > > Now, i wonder, if this is due to wrong regulators. Are there any other > > good guys here, using those? > > (If yes, please, tell me Package and Size of Fpga too. :-) > > > > much thanks in advance > > walther > > I don't know what you mean by "wrong regulators". You do know that > the S2 (Spartan II) power supply voltages are not the same as the S3 > (Spartan 3) power voltages, don't you? For example, the S2's Vccint > is 2.5v and the S3's Vccint is 1.2v. Check the Xilinx web site for > documentation. > > -Dave Pollum Hi Dave, of course, i read the xilinx papers very often. I only need to know if they are well suited to get closer to my issue. waltherArticle: 128624
Dale wrote: > I'm implementing a 36 bit x 36 bit multiplier with a 72 bit output in > a Xilinx Spartan 3E. I've tried to poke down into the RTL schematic, > but I'm unable to push down into the multiplier block. > > Could you please explain architecturally why this requires 9 > multipliers? > > Thanks, > Dale You can do a 35x35 multiplier with four DSP48s, but doing a 36x36 takes more because you can't use the 18th (sign) bit in the LSB DSP48s. See fig 1-21 of this doc: http://www.xilinx.com/bvdocs/userguides/ug073.pdf (This is for V4 designs but I think the concept is the same.) I don't know what you used to design this and why you can't look inside the RTL schematic, but maybe you can try the technology schematic. -Kevin
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