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On Sun, 27 Jan 2008 00:28:53 -0600, hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > >>A worthwhile analysis would begin with knowing the current waveforms >>that the fpga pulls on its various supplies. That would then be dumped >>into the measured or estimated impedance of the bypassed power pours. >>Does such current waveform info exist for your part, in your >>application? If not, it's back to thumps. > >Has anybody tried writing nasty test code? > >My straw man would toggle a lot of FFs for X cycles, then >do nothing for X cycles. Loop. Scan through various X >to see what happens. > >Many years ago, there was a whole branch of hardware geeks >that did nothing but write memory tests. I wonder if that >sort of technology would be useful for FPGAs. A gated clock would be a severe bypassing test, since the "DC" current draw would jump as the clock started and stopped, which would stress the low-frequency transient response of the caps and the regulators. This could easily be a bigger hazard than the GHz stuff. We've recently done some gated clock things, with switching supplies, without problems. A lot of bulk low-esr capacitance is a good idea here, if your regulator stays stable. JohnArticle: 128476
On Sun, 27 Jan 2008 13:58:11 -0500, "KJ" <kkjennings@sbcglobal.net> wrote: > >"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message >news:X-idnQg32c4zUwHanZ2dnUVZ_sbinZ2d@megapath.net... >> >>>> Has anybody tried writing nasty test code? >>>> >>>> My straw man would toggle a lot of FFs for X cycles, then >>>> do nothing for X cycles. Loop. Scan through various X >>> >>>Not sure why doing nothing for X cycles is of any use. >> >> I was trying to draw current at a lower frequency. >> Adjusting X changes the frequency of the load. >> >OK, but so does simply changing the clock frequency. Sweeping the clock >frequency from DC to light will gather the information. Burst clocking will generate, potentially, amps of low-frequency transient loading on the power supply. Slowing down a constant clock will not have that effect, since the average Vcc current will fall as the clock frequency falls. This current waveform... | | | | | | | | --------------------------------------------------- is a heap different from this one: |||||||||||||| ||||||||||||| |||||||| |||||||||||||| ||||||||||||| |||||||| ----------------------------------------------------------- JohnArticle: 128477
FoolsGold wrote: > I've got major issues here. I've installed Xilinx 9.2i with the latest > updates and service packs, and am trying to get Synplify 8.9 to actually > work with it. The problem is that although I can compile my code fine, > when it comes time to start the Place and Route state, nothing happens. > I know my project files are OK because I ran the same project on another > machine which had the same software except for an earlier version of > Xilinx. I even created a test project from scratch to test this, and the > same problem occured - Xilinx just won't take over after compilation in > Synplicity (both Premier and Pro suffer the same problem). > > It should *just work*, it has so in the past. I have the par > implementation ticked and XILINX & PATH env settings all enabled > properly. I would have though if Synplicity couldn't activate that it > would complain with an error message, but it's as if it's not even > trying to load the xilinx tools to continue. > > Since the only difference between this machine and the one that works is > a newer version of Xilinx, I'm guessing it's too new for Synplify 8.9. I > have no idea what to do. Because we have floating licenses at work, I'm used to working with Xilinx and Synplify separately. The EDIF is generated by the first tool and - very important - the Xilinx tool switched to the EDIF input file type. I think both tools can launch the other. Do you use Xilinx to launch Synplify or do you use the Synplicity tool to run the Xilinx flow? If you just want to get going, I'd recommend running the tools separately. With a valid EDIF for your Xilinx tool with an EDIF flow, you should get your P&R fine. As far as getting the tools to work cohesively? It's hard to figure out which vendor has the interface problem when everything should flow. But please let us know what flow you use. If you ARE running the tools separately, look at the EDIF file yourself and see if everything looks like it should. Then if it gets through MAP but doesn't hit PAR, check the MAP report for anything that might indicate a serious hiccup. If you're scripting everything, it's easy to lose track of errors that are blatantly obvious within the GUI; run the GUI once. - John_HArticle: 128478
On 2008-01-26, mmihai <iiahim@yahoo.com> wrote:
> On Jan 25, 12:24 am, taco <trala...@joepie.nl> wrote:
>
>> Right now I'm running an opencore 8051 which works fine and can be
>> programmed in C, but for the project I'm doing it could be that this runs
>> too slow and cannot handle to dataflow entering a FIFO. microblaze would
>> certainly solve it unless I have to add hardware.
>
> What is the complexity of your code?
>
> If you want to minimize the code to fit inside block RAMs the 8051
> might not be your best choice.
> You can find some comparison data on my proc4 web page: http://www.delajii.net/proc4
I took a quick look at your webpage [1] and have a few questions:
Do you have a C-compiler for your processor? (You only say that it is
programmable in a high-level language on your webpage.)
Do you know if commercial compilers for Z80 and 8051 will produce better
results than sdcc?
I also note that the 8051 results were done with 6 clocks per machine
cycle. AFAIK there are much faster 8051 cores available.
/Andreas
[1] Initially I expected something to download there but I guess I was
somewhat too optimistic there... still an interesting page though.
Article: 128479i need the equivalent Xilinx FPGA for the following altera devices. - Altera Stratix II GX-60 - Altera Stratix II GX-90 in terms of the resources available in these devices (logic, block ram, dcms, global clock etc) with those available in Xilinx FPGAs. thanksArticle: 128480
"Sean Durkin" <news_jan08@durkin.de> wrote in message news:603pbrF1p9i4dU1@mid.individual.net... > > Question is: Why? > Hi Sean, It's because they're not clever enough to have one of your designs in their regression test suite. Perhaps you could donate them one? They clearly need it. Please let us know how you resolve this, I've used this on designs also. ISTR I usually lie to it about the bank's VCCO. As to why the chip designers didn't power the DIFF_TERM from VCCAUX, I'd like an answer to that. Cheers, Syms.Article: 128481
I generally work by using Synplicity to run the Xilinx flow, although if necessary I can just convert to using scripts. Synplicity has a nice big "Run" button which makes things quite simple though. :) Anyway, I've determined something's gone wrong with my licenses which seems to have been fixed after switching to an alternative license server. Thanks for your help. John_H wrote: > Because we have floating licenses at work, I'm used to working with > Xilinx and Synplify separately. The EDIF is generated by the first tool > and - very important - the Xilinx tool switched to the EDIF input file > type. > > I think both tools can launch the other. Do you use Xilinx to launch > Synplify or do you use the Synplicity tool to run the Xilinx flow? > > If you just want to get going, I'd recommend running the tools > separately. With a valid EDIF for your Xilinx tool with an EDIF flow, > you should get your P&R fine. > > As far as getting the tools to work cohesively? It's hard to figure out > which vendor has the interface problem when everything should flow. But > please let us know what flow you use. > > If you ARE running the tools separately, look at the EDIF file yourself > and see if everything looks like it should. Then if it gets through MAP > but doesn't hit PAR, check the MAP report for anything that might > indicate a serious hiccup. If you're scripting everything, it's easy to > lose track of errors that are blatantly obvious within the GUI; run the > GUI once. > > - John_HArticle: 128482
Hi all, I started a book witht that titled in 2006, but never finished, as I found the sources now, well it is still unfinished, but maybe it brings some smiles onto the faces of some FPGA developers, so am making the "unfinished" version available for direct download. http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdf eh, I wanted todo this, so now already instantly feeling better! and I do have a smile :) on my face right now. Antti Lukats P.S. I make no promise or commitment to finish this book. I do have the source codes and projects described in the book though and I have worked some more with Flash FPGA's since 2006Article: 128483
On 24 Sty, 18:14, piotr.nowa...@gmail.com wrote: > > Try to import the EDK project from Win (ISE 9.1) into > > your Linux (ISE 9.2) and see what happens. > > I did it and it's working, so where is the catch? > There is 2 major defferences between 9.1 and 9.2: > - new ver. of MB (7) > - UART is using PLB instead of OPB > so, maybe PLB is not properly implemented. Finaly I have found what is wrong. In BSB "Configure IO interfaces" menu, there are two RS232 interfaces: DTE and DCE. In EDK 9.1 first one one the list is DCE but in 9.2 the first is DTE. Every time I was creating project I used the first RS232 interface on the list. I connected my board with PC through the DCE port, so that's why everything was fine on 9.1 and wrong on 9.2. Peter.Article: 128484
On Sun, 27 Jan 2008 01:15:36 +0000 (UTC), in sci.electronics.basics, Wim Lewis <wiml@hhhh.org> bloviated: >In article <a4e1p393u0n0dnui6bn4s52pmpa73lkqfm@4ax.com>, >Pillock <a@b.c> wrote: >>On Thu, 17 Jan 2008 21:14:46 -0500, in sci.electronics.basics, krw >><krw@att.bizzzzz> gurgled: >>>CMOS doesn't like X-Rays much. There is a failure mechanism that >>>tends to harden CMOS SRAM bits in one direction. I'm not sure how >>>bad it gets though. >> >>THE HORRORS! >> >>Someone need to tell Agilent & Teradyne ASAP. Millions of boards a >>year are run through their x-ray fault detection systems. >>Digital boards quite often with memory. > >There's a heck of a big difference between running a board through >an xray machine a few times, and having that board run for a long >time being exposed to xrays of uncertain energy while it's operating. And just what are those parameters? What level is safe? What level is damaging? Length of time with respect to *energy* level? Frequency domain? Studies to support that data? Don't leave everyone hanging:Article: 128485
>>There's a heck of a big difference between running a board through >>an xray machine a few times, and having that board run for a long >>time being exposed to xrays of uncertain energy while it's operating. > >And just what are those parameters? What level is safe? What level is >damaging? Length of time with respect to *energy* level? Frequency >domain? Studies to support that data? > >Don't leave everyone hanging: It's OK to leave me hanging. Like most people, I don't care much about the effects of X-rays. My equipment isn't subjected to any significant intensity, because it's not X-rayed while in use, nor is it likely to go into space. If you're so interested, why not research it yourself?Article: 128486
On Mon, 28 Jan 2008 14:58:32 +0000, in sci.electronics.basics, MikeShepherd564@btinternet.com bloviated: >>>There's a heck of a big difference between running a board through >>>an xray machine a few times, and having that board run for a long >>>time being exposed to xrays of uncertain energy while it's operating. >> >>And just what are those parameters? What level is safe? What level is >>damaging? Length of time with respect to *energy* level? Frequency >>domain? Studies to support that data? >> >>Don't leave everyone hanging: > >It's OK to leave me hanging. Like most people, I don't care much >about the effects of X-rays. My equipment isn't subjected to any >significant intensity, because it's not X-rayed while in use, nor is >it likely to go into space. > >If you're so interested, why not research it yourself? Ah, so you didn't quite catch the quite obvious drift of the questions. Here is a little research for you, look up the term FUD. Follow that with "saccharine in rodents".Article: 128487
On Jan 17, 3:00=A0am, Jon Beniston <j...@beniston.com> wrote: > On 17 Jan, 08:03, recoder <kurtulmeh...@gmail.com> wrote: > > > Dear All, > > =A0As an assignment I have to design a CCD Sensor based FPGA digital > > Camera. However, the Camera will be exposed to XRAY (It will be placed > > behind an Imaging Intensifier). Does anybody know how XRAY affects the > > electronic circuits (The CCD Sensor and the FPGA ). What type of noise > > should I expect and what should I do to prevent it. > > =A0Thanks in advance > > Can bits be flipped? > > Do you need a RadHard FPGA? > > Cheers, > Jon To all it matters to what level of radiation from your source gets to your CCD camera. As a X Product Manager for a X-ray imaging company if we placed the CCD camera behind a intensifier tube -- lots of material between it and the camera a few lens -- we had little problem with noise from the x-ray beam we we producing. We could still detect some x-rays at this point but they were real weak. Now when we put the CCD (Sony) B/W camera in the direct beam path we had issues of noise in the CCD detector. We landed up placing the camera off axis. When we went to a special CCD camera behind a screen and a little glass it was not a bad but could still be seen and needed averaging to get rid of the problems we could see. Hope this helps-- Place the camera off axis if at all possible remember a lot of thing are transperant to x- ray but will reflect light. Regards CliffArticle: 128488
On 2008-01-28, Antti <Antti.Lukats@googlemail.com> wrote: > > http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdf ...you got FIRED for missing 3 days of work due to a mixup in vacation scheduling? Wow. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 128489
> > http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdf > > eh, I wanted todo this, so now already instantly feeling better! > and I do have a smile :) on my face right now. Hi Antti, :) from me. Is it Actel FPGA on the last page? Regards, -- M.Veselic Sigma Lab.Article: 128490
Hi - Power supply bypassing being a hot topic in these parts, some folks may be interested in the following. According to the IEEE Santa Clara Valley IEEE EMC web site, Steve Weir of Terraspeed Consulting will be giving a presentation titled, "Using a Spatial View to Understand and Solve Common Power Bypass Problems" at the next chapter meeting, on Tuesday, February 12th at 6:30 PM. Meetings are held at the Applied Materials Bowers Cafeteria, 3090 Bowers Ave., Santa Clara, CA. You can find out more here: http://www.scvemc.org/ Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 128491
comp.arch.fpga wrote: > Hi, > > am a little confused as far as the capabilities of the DSP48 go. > I would like to implement a 18x35 MACC in (hopefully) only two DSP48. > The 18 bit coefficient is a 0.18 fixed point number. I.e. what I > really want > to implement is > ((A18 x B36)>>17)+C48 > > Apparently I overlooked that the DSP48 slice only allows for common C > inputs > which means that I can not split C appropriatly accross the two > adders. > > What am I missing? Do I really need to implement the adder in LUTs? > > Kolja Sulimma Kolja, You can easily make an 18x85 multiplier with two DSP48s (see fig 1-20 of http://www.xilinx.com/bvdocs/userguides/ug073.pdf) but to do an accumulation you will have to add a third DSP48, using it only as an accumulator. (I wouldn't do this in fabric. See fig. 5-2 of the same doc to see the concept used in a semiparallel FIR.) You could do it in two DSP48s if you can spare a cycle, for example, when it's time to clear the accumulator. This is done by doing separate multiply-accumulates on the MSB and LSB DSP48s, and then at the end of the accumulation period, on the spare cycle, summing the two together by changing the opcode mux. -KevinArticle: 128492
Tim (one of many) wrote: > Jonathan Bromley wrote: >> On Fri, 25 Jan 2008 09:12:45 -0800 (PST), Gabor <gabor@alacron.com> >> wrote: >> >>> When is 36 pins not 36 pins ? >> >> When it's a typo for 40, I think. C'mon, give the >> guy a break - we all make tripyng mshtks. > > I was sent this (no references for the alleged Cantab research): > > Olny srmat poelpe can raed this. I cdnuolt blveiee that I cluod aulaclty > uesdnatnrd what I was rdanieg. The phaonmneal pweor of the hmuan mnid, > aoccdrnig to a rscheearch at Cmabrigde Uinervtisy, it deosn't mttaer in > what oredr the ltteers in a word are, the olny iprmoatnt tihng is that > the first and last ltteer be in the rghit pclae. The rset can be a taotl > mses and you can still raed it wouthit a porbelm. Tihs is bcuseae the > huamn mnid deos not raed ervey lteter by istlef, but the word as a > wlohe. Amzanig huh?! Yaeh and I awlyas tghuhot slpeling was ipmorantt! That is pretty amazing. I've seen the same exercise done in German, with much less success, because many of the words are large concatenated compound nouns. When the brain comes across such a large word, such as Ernaehrungswissenschaftlerin (an actual word I encountered in an article today) it's much more difficult to process than were it broken down into the hyphenated noun Ernaehrungs-Wissenschaftlerin. I think it's similar to the concept that the brain can instantly process the number of dots in an image if the number of dots is up to eight or so, but for larger amounts one has to actually count them out. -KevinArticle: 128493
jack.harvard@googlemail.com wrote: > Hi, > > I tried to boot Linux on my FPGA-prototyped SoC system. The Linux > image is running from SDRAM which is controlled by a Dynamic Memory > Controller, but the Linux boot always stop at somewhere around(not at > the same point each time): > Mount-cache hash table entries: 512 > <6>CPU: Testing write buffer coherency: ok > > I thought this could possibly point to some obscure timing issues of > the memory controller, as 1) Modelsim simulation didn't point to any > memory controller issues 2) the memory controller is on a different > board from the actual SDRAM 3) tools like Synplify and ISE are not > reliable from my limited experience 4) latches might also cause > problems. > > I'm asking for thoughts about what can go wrong when prototyping a > memory controller into an FPGA. Please kindly offer your insights with > memory controllers especially if you had similar problems before. > > Thanks a lot, The things that can go wrong are legion. The #1 problem you can have is that read data arrives at the FPGA input pins at an unknown time and on an unknown clock edge and possibly near a clock edge and your controller needs to be able to accurately deskew all the datalines. You say that the Modelsim simulation works, but do you have the exact PCB trace delays and IOB delays programmed into the simulation? Likely not. And worst-case delays won't help you any, because the worst-case delay might actually work well whereas the *actual* delay (which, in the case of IOBs is probably much better than worst-case) might not. Having the FPGA and SDRAM on different boards (?) also sounds like a problem. Most controllers are only going to operate over a narrow range of trace delays. -KevinArticle: 128494
Hi,
talkb wrote:
> "John McCaskill" <jhmccaskill@gmail.com> wrote in message
> news:aa864ccf-655f-445e-9a68-a25979acbdc2@v67g2000hse.googlegroups.com...
> > You can use Smartmodels with ModelSim PE, you just need to get a
> > license for it. Look in the license file on the computer that you used
> > to see if it had a license. I use ModelSim PE with extra license for
> > Smartmodels, mixed language support, and code coverage. Even with
> > getting the extra licenses PE was much cheaper than SE. Most of the
> > difference is because of using a dongle instead of a floating license.
> > SE comes standard with a floating license.
>
> Modelsim/SE is a (ASIC) "sign-off grade" simulator -- it's more expensive
> for that reason alone, though cheaper than its competition (Synopsys VCS,
> Cadence Incisive.)
>
> Once upon a time, Cadence made a desktop simulator product called
> "Verilog Desktop" -- it was priced to compete with Modelsim/PE, Aldec, etc.
> But I'd guess Cadence didn't get any traction in the FPGA and desktop
> simulation market, so they stopped after version 5.1 or so.
>
> > EDK supports ModelSim, and Cadence, but not Aldec.
>
> I did notice Xilinx's Library Compilation Wizard only gives two choices:
> Modelsim or NC-Sim. But Aldec's support page has downloadable (precompiled)
> libraries for both ISE 9.2.04i and EDK 9.2i.02. I'm hoping this means
> Active-HDL is usable for EDK-simulation, even if Xilinx doesn't officially
> sanction it.
>
Xilinx works with VCS-MX also and probably all decent simulatorns on all
platforms, we use it on AMDs running Solaris 10 where Xilinx is not
supported, see below for supported simulators on Sparc Solaris 10!
edaadm@brera $ compxlib -help sim
Release 9.2.04i - COMPXLIB J.40
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
-s <simulator> : Specify the name of the simulator for which the libraries
are to be compiled. The valid simulator names are :-
mti_se mti_pe vcs_mx vcs_mxi ncsim
Also compiling is trivial in Verilog(just compile it), and in VHDL
Xilinx has supplied a file named vhdl_analyze_order in the
$XILINX/vhdl/src/XilinxCoreLib directory.
/michael
Article: 128495
Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote:
> I think it's similar
> to the concept that the brain can instantly process the number of dots
> in an image if the number of dots is up to eight or so, but for larger
> amounts one has to actually count them out.
See:
http://www.musanim.com/miller1956/
"The Magical Number Seven, Plus or Minus Two: Some Limits on
Our Capacity for Processing Information"
by George A. Miller
The Psychological Review, 1956, vol. 63, pp. 81-97
G.
Article: 128496Pillock wrote: > On Mon, 28 Jan 2008 14:58:32 +0000, in sci.electronics.basics, > MikeShepherd564@btinternet.com bloviated: > > >>>>There's a heck of a big difference between running a board through >>>>an xray machine a few times, and having that board run for a long >>>>time being exposed to xrays of uncertain energy while it's operating. >>> >>>And just what are those parameters? What level is safe? What level is >>>damaging? Length of time with respect to *energy* level? Frequency >>>domain? Studies to support that data? >>> >>>Don't leave everyone hanging: >> >>It's OK to leave me hanging. Like most people, I don't care much >>about the effects of X-rays. My equipment isn't subjected to any >>significant intensity, because it's not X-rayed while in use, nor is >>it likely to go into space. >> >>If you're so interested, why not research it yourself? > > > Ah, so you didn't quite catch the quite obvious drift of the > questions. > > Here is a little research for you, look up the term FUD. > > Follow that with "saccharine in rodents". better yet, look up "fundamentals of nuclear hardening of electronic equipment", L. W. Ricketts, Krieger pub. Cheers TerryArticle: 128497
On Jan 28, 5:52 pm, Michael Laajanen <michael_laaja...@yahoo.com> wrote: > Hi, > > > > talkb wrote: > > "John McCaskill" <jhmccask...@gmail.com> wrote in message > >news:aa864ccf-655f-445e-9a68-a25979acbdc2@v67g2000hse.googlegroups.com... > > > You can use Smartmodels with ModelSim PE, you just need to get a > > > license for it. Look in the license file on the computer that you used > > > to see if it had a license. I use ModelSim PE with extra license for > > > Smartmodels, mixed language support, and code coverage. Even with > > > getting the extra licenses PE was much cheaper than SE. Most of the > > > difference is because of using a dongle instead of a floating license. > > > SE comes standard with a floating license. > > > Modelsim/SE is a (ASIC) "sign-off grade" simulator -- it's more expensive > > for that reason alone, though cheaper than its competition (Synopsys VCS, > > Cadence Incisive.) > > > Once upon a time, Cadence made a desktop simulator product called > > "Verilog Desktop" -- it was priced to compete with Modelsim/PE, Aldec, etc. > > But I'd guess Cadence didn't get any traction in the FPGA and desktop > > simulation market, so they stopped after version 5.1 or so. > > > > EDK supports ModelSim, and Cadence, but not Aldec. > > > I did notice Xilinx's Library Compilation Wizard only gives two choices: > > Modelsim or NC-Sim. But Aldec's support page has downloadable (precompiled) > > libraries for both ISE 9.2.04i and EDK 9.2i.02. I'm hoping this means > > Active-HDL is usable for EDK-simulation, even if Xilinx doesn't officially > > sanction it. > > Xilinx works with VCS-MX also and probably all decent simulatorns on all > platforms, we use it on AMDs running Solaris 10 where Xilinx is not > supported, see below for supported simulators on Sparc Solaris 10! > > edaadm@brera $ compxlib -help sim > Release 9.2.04i - COMPXLIB J.40 > Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. > > -s <simulator> : Specify the name of the simulator for which the libraries > are to be compiled. The valid simulator names are :- > > mti_se mti_pe vcs_mx vcs_mxi ncsim > > Also compiling is trivial in Verilog(just compile it), and in VHDL > Xilinx has supplied a file named vhdl_analyze_order in the > $XILINX/vhdl/src/XilinxCoreLib directory. > > /michael The OP asked what EDK supports, compxlib is part of ISE, not EDK. I am currently using EDK/ISE 8.1 8.2 and 9.1, and I see that ISE does support vcs, but EDK does not. I also use ModelSim but not Cadence. When I say that EDK supports ModelSim and Cadence, I mean two things. 1. For those simulators the SimGen tool will generate setup scripts for you from your EDK project that let you launch the simulator, compile the project, setup the display windows, and run the simulation. I think that this is a very nice feature, but if you prefer another simulator, you can of course do this yourself. 2. Xilinx presumably does quality assurance testing against the simulators that they say are supported, and will provide help if you have problems. To me this is the critical point. At least for ModelSim, Xilinx is very specific about which versions they support. In the case of EDK 8.2, they specify one specific release of ModelSim as the only supported version. We have tried running with other versions with mixed results. When we used the supported version, our test benches passed and matched what we saw in hardware. When we used other versions, some times we got the same results, some times we did not. If your setup is working for you, I don't blame you for not wanting to change it. But there is a difference between it works, and it is supported. Regards, John McCaskill www.FasterTechnology.comArticle: 128498
"John McCaskill" <jhmccaskill@gmail.com> wrote in message news:aa864ccf-655f-445e-9a68-a25979acbdc2@v67g2000hse.googlegroups.com... > You can use Smartmodels with ModelSim PE, you just need to get a > license for it. Look in the license file on the computer that you used > to see if it had a license. I use ModelSim PE with extra license for > Smartmodels, mixed language support, and code coverage. Even with > getting the extra licenses PE was much cheaper than SE. Most of the > difference is because of using a dongle instead of a floating license. > SE comes standard with a floating license. Ok, I double-checked our license-server's license.dat file. The commented section indicated our company is licensed for "Modelsim-PE Plus" As far as I can tell, the actual license-increments are just 2 items: 1) msimpevlog (Verilog) 2) msimpe (VHDL) Nothing else 'special' in the license-file. Perhaps Modelsim allows a Verilog+VHDL combo license to subsitute for a Smartmodel license?Article: 128499
here is my codes. I want to verify the result and display at the end,
however I got like "cdcd", what's wrong? thanks
/*
* "Hello World" example.
*
* This example prints 'Hello from Nios II' to the STDOUT stream. It
runs on
* the Nios II 'standard', 'full_featured', 'fast', and 'low_cost'
example
* designs. It runs with or without the MicroC/OS-II RTOS and requires
a STDOUT
* device in your system's hardware.
* The memory footprint of this hosted application is ~69 kbytes by
default
* using the standard reference design.
*
* For a reduced footprint version of this template, and an
explanation of how
* to reduce the memory footprint for a given application, see the
* "small_hello_world" template.
*
*/
#include <stdio.h>
#include <stdlib.h>
#include <sys/alt_dma.h>
#include "system.h"
static volatile int rx_done = 0;
/*
* Callback function that obtains notification that the data has
* been received.
*/
static void done (void* handle, void* data)
{
rx_done++;
}
int main(int argc, char* argv[], char* envp[])
{
int rc;
static char buff[256]="abcdefghijklmn\0";
alt_dma_txchan txchan;
alt_dma_rxchan rxchan;
void* tx_data = (void*) buff; /* pointer to data to
send */
void* rx_buffer = (void*) 0x01000000; /* on_chip_memory addr*/
/* Create the transmit channel */
if ((txchan = alt_dma_txchan_open("/dev/dma_0")) == NULL)
{
printf ("Failed to open transmit channel\n");
exit (1);
}
/* Create the receive channel */
if ((rxchan = alt_dma_rxchan_open("/dev/dma_0")) == NULL)
{
printf ("Failed to open receive channel\n");
exit (1);
}
/* Post the transmit request */
if ((rc = alt_dma_txchan_send (txchan,tx_data,128,NULL,NULL)) < 0)
{
printf ("Failed to post transmit request, reason = %i\n", rc);
exit (1);
}
/* Post the receive request */
if ((rc = alt_dma_rxchan_prepare (rxchan,rx_buffer,128,done,NULL)) <
0)
{
printf ("Failed to post read request, reason = %i\n", rc);
exit (1);
}
/* wait for transfer to complete */
while (!rx_done);
printf ("Transfer successful!\n");
printf ("%s",(ONCHIP_MEMORY_0_BASE));
return 0;
}
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