Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Dear All, I need to do the following: 1. Capturing 10 bit monochrome video 2. Recursive Filtering 3. Display the output to a LCD 4. Optionally sending the output to Ethernet Can you refer development boards and IP's/ VHDL sources to fulfill all the tasks, Thanks in AdvanceArticle: 127426
"Sebastien Bourdeauducq" <sebastien.bourdeauducq@gmail.com> wrote in message news:5aa51783-e381-4bbb-ac35-885af810f308@f53g2000hsg.googlegroups.com... > Hi, > > Has anyone used the ddr_sdr core (http://www.opencores.org/ > projects.cgi/web/ddr_sdr/overview) on real hardware ? > > This core only uses the DQS lines for writing to the memory, and sets > them as outputs. Therefore, during reads, both the FPGA and the DDRAM > chip will drive them at the same time. Won't it be a problem ? Maybe > not, thanks to the series termination resistors...but can anyone > confirm ? Try looking to see how the output is set to a high impedance state during those read cycles. KJArticle: 127427
Sebastien Bourdeauducq wrote: > This core only uses the DQS lines for writing to the memory, and sets > them as outputs. Therefore, during reads, both the FPGA and the DDRAM > chip will drive them at the same time. Won't it be a problem ? Yes, that would be a problem. The FPGA shouldn't drive the DQS lines when the DRAM is driving them.Article: 127428
Hi it seems that Xilinx has promised to publisch (finally!) the programming APIs for cable IV and platform USB cable. this is not official but the universal scan last version includes notes that they add support for Cable IV and platform USB in JANUARY 2008; after Xilinx publishes the docs. so it can be derived that Xilinx has made promises to publish the APIs in 2007 hm, maybe they already online at xilinx.com ? any more info anyone? Antti LukatsArticle: 127429
FAQ page page for our Darnaw1 now in place with some of the common questions answered. It's here http://www.enterpoint.co.uk/moelbryn/darnaw1_faq.html. As a reminder the Enterpoint Team are now on holiday until early January and sales and support emails will resultantly have a slower response time than normal. There will be some coverage during this period so do ask if you need answers but do expect the slower response than normal. Our offical first shipping day of 2008 will be the 7th January. Meanwhile I wish everyone a Merry Christmas and a Happy New Year. John Adair Enterpoint.Article: 127430
Sebastien Bourdeauducq <sebastien.bourdeauducq@gmail.com> wrote: >Hi, > >Has anyone used the ddr_sdr core (http://www.opencores.org/ >projects.cgi/web/ddr_sdr/overview) on real hardware ? > >This core only uses the DQS lines for writing to the memory, and sets >them as outputs. Therefore, during reads, both the FPGA and the DDRAM >chip will drive them at the same time. Won't it be a problem ? Maybe >not, thanks to the series termination resistors...but can anyone >confirm ? I can't imagine there is such an error in the design especially since its a crippled version of a commercial product (if memory serves me well). How are you sure the DQS lines are set as outputs the whole time? -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127431
Well, I thought that "out" signals in VHDL could not be set to high- impedance state, only "inout" signals could ; and that contention might not be a big problem with SSTL signaling, but I was wrong. After reading your replies I looked more closely at the code, and it sets the DQS outputs to 'Z' when reading. I did not think that could be possible. Thanks, SebastienArticle: 127432
Dear Sir, My full project title is to create a dot product of 'n' numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze. I want a VHDL code for scalar dot product of n inputs. It should be added as custom IP (Intellectual Property) in to the hardware peripheral and interfaced with MicroBlaze. The target board is Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen in the website given below. http://wiki.ittc.ku.edu/ittc/Eecs388 I have to use MicroBlaze (Softcore) to pass the dot products values to the custom IP (Hardcore). No calculation should be done on the MicroBlaze (softcore). The calculation should be done on the custom IP (hard core). Following are the Phases involved. Phase1: Creation of VHDL code for N input dot product Phase2: Addition of custom IP (VHDL code of scalar dot product) and interface it with using MicroBlaze Phase3: Download into FPGA and result of the dot product is seen in the hyper terminal because the FPGA Board is interfaced with Computer via RS232 Serial Cable. The above Project is to be worked with Xilinx EDK 9.1i for implementation in FPGA and Xilinx ISE 9.1i for simulating the custom IP generated. Kindly let me know whether you can provide On-Line Support and provide solution for the above Project. Regards S. ArunkumarArticle: 127433
HenktenBakker wrote: > I'd also be interested in a WORKING example of the DDR SDRAM on this > board. > I asked this quastion already and had been pointed to examples allrady > too - but no success so far. I guess you did not have any success at all. I bought a board from Digi-Key and started development for an audio project. When I messured my SDRAM clock, I saw that someone already soldered on that board. Looks like someone tried to get it to work and gave up and returned the board. That I finally got. The high level on my clock line is only 2V unloaded. My almost 150MHz clock has a DC level of only 0.8V instead of the required 1.25V. This propably will not trigger the SDRAM at all. The levels on the address lines look ok on the first view. I will do some more investigations. It looks like two 100Ohm pullups will give correct clock levels. What happened? Did they forget a VCCIO pin or does the chip have a flaw? I have a rev. D board with a -6T SDRAM chip on it.Article: 127434
BALAS009 wrote: > Dear Sir, > > My full project title is to create a dot product of 'n' > numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze. > > I want a VHDL code for scalar dot product of n inputs. It should be > added as custom IP (Intellectual Property) in to the hardware > peripheral and interfaced with MicroBlaze. The target board is > Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen > in the website given below. > > http://wiki.ittc.ku.edu/ittc/Eecs388 > > I have to use MicroBlaze (Softcore) to pass the dot products values to > the custom IP (Hardcore). > > No calculation should be done on the MicroBlaze (softcore). The > calculation should be done on the custom IP (hard core). > > Following are the Phases involved. > > Phase1: Creation of VHDL code for N input dot product > > Phase2: Addition of custom IP (VHDL code of scalar dot product) and > interface it with using MicroBlaze > > Phase3: Download into FPGA and result of the dot product is seen in > the hyper terminal because the FPGA Board is interfaced with Computer > via RS232 Serial Cable. > > The above Project is to be worked with > > Xilinx EDK 9.1i for implementation in FPGA and Xilinx ISE 9.1i for > simulating the custom IP generated. > > Kindly let me know whether you can provide On-Line Support and provide > solution for the above Project. > > Regards > > S. Arunkumar This appears to be the absolutely most blatant "Do my work for me!" demand I've seen so far. You want a SOLUTION?! I won't repeat the phrase going through my head right now. You might garner some support if you give some indication that you're doing your own work. We - as a profession - do NOT need new engineers graduating with this kind of attitude toward assignments. Withdraw now and go into business school; those are the kinds of people that get others to do their work for them. If you want assistance, please use the university resources and leave us otherwise generous professionals alone. Merry Christmas.Article: 127435
My car needs an oil change. And all the windows in my house need a thorough wash. When can you come by and do that ? For free, of course... Peter Alfke On Dec 24, 6:24=A0am, BALAS009 <BALAS...@gmail.com> wrote: > Dear Sir, > > My full project title is to create a dot product of 'n' > numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze. > > I want a VHDL code for scalar dot product of n inputs. It should be > added as custom IP (Intellectual Property) in to the hardware > peripheral and interfaced with MicroBlaze. The target board is > Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen > in the website given below. > > http://wiki.ittc.ku.edu/ittc/Eecs388 > > I have to use MicroBlaze (Softcore) to pass the dot products values to > the custom IP (Hardcore). > > No calculation should be done on the MicroBlaze (softcore). The > calculation should be done on the custom IP (hard core). > > Following are the Phases involved. > > Phase1: Creation of VHDL code for N input dot product > > Phase2: Addition of custom IP (VHDL code of scalar dot product) and > interface it with using MicroBlaze > > Phase3: Download into FPGA and result of the dot product is seen in > the hyper terminal because the FPGA Board is interfaced with Computer > via RS232 Serial Cable. > > The above Project is to be worked with > > Xilinx EDK 9.1i for implementation in FPGA and Xilinx ISE 9.1i for > simulating the custom IP generated. > > Kindly let me know whether you can provide On-Line Support and provide > solution for the above Project. > > Regards > > S. ArunkumarArticle: 127436
I have a 32-bit (x86) Centos 5.1 installation with Xilinx Webpack 9.2i.04 and EDK 9.2. I first started with Xilinx AR #22648. (i.e., I downloaded install_drivers.tar.gz) I hadn't payed much attention during Centos's installation-screen, so onw I found out I was missing a bunch of development libraries, tools (gcc), etc. After a few hours of waiting for yum to install the necessary dev-environment tools, I got as far as install_drivers telling me it couldn't find various files. A few of these were obvious to fix -- Centos 5.1 sets up the dir-tree with only partially correct version-identifiers, and these broke the script's assumptions. After several hours of frustration, I gave up with getting the Platform USB driver to run under Centos 5.1. Thankfully, a few google-searches turned up a lifesaving workaround (for me, anyway) : http://www.rmdir.de/~michael/xilinx/ At first it didn't work. Centos puts 'fxload' in /usr/sbin, though this could have been due to my other counterproductive attempts to compile windrvr6. After I created a symlink in /sbin/fxload -> /usr/sbin/fxload, unplugged and replugged the FPGA-board, iMPACT worked! It could see the board, and download bitstreams to the Spartan-3E. Sorry for the lack of details in this post -- as you can tell, I'm kind of a novice linux/unix person. (I've used it for years, but only as a 'dumb-user' and not an administrator.) I'm kind of intimidated with the difficulty in bringing up a simple linux FPGA-dev environment. I should have listened to all the advice and stuck with a Linux 2.4 kernel (Centos 3)!Article: 127437
John_H <newsgroup@johnhandwork.com> wrote: >BALAS009 wrote: >> Dear Sir, >> >> My full project title is to create a dot product of 'n' >> numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze. >> >> I want a VHDL code for scalar dot product of n inputs. It should be >> added as custom IP (Intellectual Property) in to the hardware >> peripheral and interfaced with MicroBlaze. The target board is >> Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen >> in the website given below. >> >> http://wiki.ittc.ku.edu/ittc/Eecs388 >> >> The above Project is to be worked with >> >> Xilinx EDK 9.1i for implementation in FPGA and Xilinx ISE 9.1i for >> simulating the custom IP generated. >> >> Kindly let me know whether you can provide On-Line Support and provide >> solution for the above Project. >> >> Regards >> >> S. Arunkumar > >This appears to be the absolutely most blatant "Do my work for me!" >demand I've seen so far. You want a SOLUTION?! I won't repeat the >phrase going through my head right now. Hint, some people pay to get their homework done. Works great since they are likely to become a regular customer... -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127438
GREETINGS AND FELICITATIONS, MR G'MAIL - I AM PROUD TO PRESENT MYSELF TO YOU AS NABALU "SKIPPY" UMBEKE, MINISTER OF DESIGN FOR THE EXALTED FEDERAL REPUBLIC OF NIGERIA IN ABUJA. IT IS FOR ME TO OFFER YOU A FINDING ARISING FROM UNUSUAL CIRCUMSTANCES. AN ENGINEER WORKING FOR OUR MINISTRY RECENTLY DECEASED HIMSELF, LEAVING IN HIS WAKE AN FPGA DESIGN FOR WHAT WE CALL IT SCALAR DOT PRODUCT. IN HAPPY HAPPENSTANCE, WE ALSO HAVE NOT PAID FOR THIS DESIGN APPURTENANCE, LEAVING OUR OFFICES WITH A DUE PAYMENT OF $24,500,000 (TWENTY FOUR POINT FIVE MILLION DOLLARS). MR. G'MAIL, WOULD YOU BE WILLING TO DO US CONSIDERABLE SERVICE AND TAKE DESIGN AND EXCESS DOLLARS OFF OUR TABLE? WE CAN EASY TRANSFER BOTH TO YOU WITH IMMEDIACY IF YOU WOULD ONLY GIVE TO US YOUR BANK ACCOUNT NUMBERS, SOCIAL SECURITY NUMBER, AND ANY OTHER SUCH PRIVATE INFORMATIONS THAT YOU WOULD BE RELUCTANT TO EMIT TO ANYONE OTHER THAN A MINISTER OF DESIGN IN A FARAWAY LAND. AS SOON AS I USURP THIS INFORMATION FROM YOU, I WILL HASTILY TRANSFER TO YOU THE MONIES AND THE DESIGN BOTH. AS A SIGN OF OUR FAITH AND GOODWILL IN THIS BURGEONING BUSINESS RELATIONSHIP, WE WILL SEND TO YOU ALSO A DESIGN FOR A MOST EXCELLENT TRAFFIC LIGHT CONTROLLER. YOURS IN THE EPITOME OF HUMBLE SINCERITY, NABULU UMBEKE MINISTER OF DESIGNArticle: 127439
>This appears to be the absolutely most blatant "Do my work for me!" >demand I've seen so far. You want a SOLUTION?! I won't repeat the >phrase going through my head right now. I understood him to be asking for a commercial tender.Article: 127440
In article <odqdnUQPmoYvlO3anZ2dnUVZ_t2inZ2d@comcast.com>, John_H <newsgroup@johnhandwork.com> wrote: >BALAS009 wrote: >> Dear Sir, >> >> My full project title is to create a dot product of 'n' >> numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze. >> >> I want a VHDL code for scalar dot product of n inputs. It should be >> added as custom IP (Intellectual Property) in to the hardware >> peripheral and interfaced with MicroBlaze. The target board is >> Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen >> in the website given below. >> >> http://wiki.ittc.ku.edu/ittc/Eecs388 >> > >This appears to be the absolutely most blatant "Do my work for me!" >demand I've seen so far. You want a SOLUTION?! I won't repeat the >phrase going through my head right now. > >You might garner some support if you give some indication that you're >doing your own work. We - as a profession - do NOT need new engineers >graduating with this kind of attitude toward assignments. > >Withdraw now and go into business school; those are the kinds of people >that get others to do their work for them. > >If you want assistance, please use the university resources and leave us >otherwise generous professionals alone. > >Merry Christmas. I thought the the link was intersting. As a graduate student in ECE, I've taken every course my school offers related to configurable logic and haven't had anything this interesting offered. Not one class has included taking a design to hardware, I've had to do that on my own. The designs required for the classes have also been very small, bordering on trivial in the most challenging cases. Oh, well, that's a cool thing about FPGAs - it's pretty easy to do it on your own. It's just that I could justify more time on it if I were getting credit... Good job, University of Kansas! Rick rickc (a) rdrop comArticle: 127441
Bob Perlman wrote: > GREETINGS AND FELICITATIONS, MR G'MAIL - > > I AM PROUD TO PRESENT MYSELF TO YOU AS NABALU "SKIPPY" UMBEKE, > MINISTER OF DESIGN FOR THE EXALTED FEDERAL REPUBLIC OF NIGERIA IN > ABUJA. IT IS FOR ME TO OFFER YOU A FINDING ARISING FROM UNUSUAL > CIRCUMSTANCES. AN ENGINEER WORKING FOR OUR MINISTRY RECENTLY DECEASED > HIMSELF, LEAVING IN HIS WAKE AN FPGA DESIGN FOR WHAT WE CALL IT SCALAR > DOT PRODUCT. IN HAPPY HAPPENSTANCE, WE ALSO HAVE NOT PAID FOR THIS > DESIGN APPURTENANCE, LEAVING OUR OFFICES WITH A DUE PAYMENT OF > $24,500,000 (TWENTY FOUR POINT FIVE MILLION DOLLARS). > > MR. G'MAIL, WOULD YOU BE WILLING TO DO US CONSIDERABLE SERVICE AND > TAKE DESIGN AND EXCESS DOLLARS OFF OUR TABLE? WE CAN EASY TRANSFER > BOTH TO YOU WITH IMMEDIACY IF YOU WOULD ONLY GIVE TO US YOUR BANK > ACCOUNT NUMBERS, SOCIAL SECURITY NUMBER, AND ANY OTHER SUCH PRIVATE > INFORMATIONS THAT YOU WOULD BE RELUCTANT TO EMIT TO ANYONE OTHER THAN > A MINISTER OF DESIGN IN A FARAWAY LAND. AS SOON AS I USURP THIS > INFORMATION FROM YOU, I WILL HASTILY TRANSFER TO YOU THE MONIES AND > THE DESIGN BOTH. AS A SIGN OF OUR FAITH AND GOODWILL IN THIS > BURGEONING BUSINESS RELATIONSHIP, WE WILL SEND TO YOU ALSO A DESIGN > FOR A MOST EXCELLENT TRAFFIC LIGHT CONTROLLER. > > YOURS IN THE EPITOME OF HUMBLE SINCERITY, > NABULU UMBEKE > MINISTER OF DESIGN Mr. Umbeke, I'm sure the original poster thanks you for your kind offer of assistance. As it happens, I also have come into possession of much knowledge through my years of experience. Perhaps it would be possible for us to coagulate our knowledge to help this poor unfortunate student. I would be glad, nay enthralled, to share my portion of a useful design for a mere 30% of the total moneys involved. Yours, to the attainment of higher knowledge, RB P.S. Great post, Bob. Sorry I can't do it justice.Article: 127442
BALAS009 wrote: > Dear Sir, > > My full project title is to create a dot product of 'n' > numbers(a0*b0+a1*b1+....+aN*bN) using MicroBlaze. > > I want a VHDL code for scalar dot product of n inputs. It should be > added as custom IP (Intellectual Property) in to the hardware > peripheral and interfaced with MicroBlaze. The target board is > Vertex2Pro (maximum clock frequency 100 MHZ) and the same can be seen > in the website given below. > > http://wiki.ittc.ku.edu/ittc/Eecs388 > > I have to use MicroBlaze (Softcore) to pass the dot products values to > the custom IP (Hardcore). > > No calculation should be done on the MicroBlaze (softcore). The > calculation should be done on the custom IP (hard core). > > Following are the Phases involved. > > Phase1: Creation of VHDL code for N input dot product > > Phase2: Addition of custom IP (VHDL code of scalar dot product) and > interface it with using MicroBlaze > > Phase3: Download into FPGA and result of the dot product is seen in > the hyper terminal because the FPGA Board is interfaced with Computer > via RS232 Serial Cable. > > The above Project is to be worked with > > Xilinx EDK 9.1i for implementation in FPGA and Xilinx ISE 9.1i for > simulating the custom IP generated. > > Kindly let me know whether you can provide On-Line Support and provide > solution for the above Project. > > Regards > > S. Arunkumar I'm sure Dr. Andrews would love to hear about this. RBArticle: 127443
> Regards > S. Arunkumar Should you wish to get a complete, working design, please answer privately so I can give you my Paypal ID. Anyway, here is how I would do it. I will provide two solutions. Solution #1 : "the works". Your teacher will bow before your m4d skillZ. "dot product" core is an OPB master. Microblaze writes into "dot product" core's registers, information about where to grab the data in memory (vector 1 address, vector 2 address, vector length). "dot product" core acts as an OPB DMA master and burst-reads vector data, computes dot product, and wakes Microblaze up with an interrupt when it's done. Microblaze will then read result in "dot product" core's register. For added points, add provision for partitioned convolution. Solution #2 : damn, get this over with. Vector data is stored in opb_bram memory. Memory is dual port, so one port is connected to OPB via standard Xilinx opb_bram core. Standard Xilinx central_dma core is used to copy vector data from SDRAM into the dedicated BRAM. Microblaze writes into "dot product" core's registers, information about where to grab the data in BRAM (vector 1 address, vector 2 address, vector length). "dot product" core hits BRAM and reads vector data, computes dot product, and wakes Microblaze up with an interrupt when it's done. Microblaze will then read result in "dot product" core's register.Article: 127444
Hi, I have a custom made FPGA board with Spartan xc3s1000 -4 fg456 on it. There is this strange behaviour of different bitstreams that made me to turn on the verify option while configuring the FPGA. It was quite disappointing that the verification for different bitstreams fail. The FPGA does get programmed successfully but does not pass the verification phase. I have started suspecting the FPGA part on my board. There are some ISE projects whose generated bitstreams work fine on the board but if I add some functionality in these projects, the FPGA stops responding or start misbehaving. Is there anyway I can verify the complete FPGA for its LUTs, static ram cells etc which hold the configuration bits? In case if some LUTs or ram cells are faulty, is there any way I can know the locations of these faulty cells so that I can try mapping my design on the working area? Regards SMFArticle: 127445
Hi all, Does anybody knows where are the web page of "TechXclusives" subject. It seems they've disappeared from Xilinx website. Thanks.Article: 127446
On Dec 24, 2:14 am, recoder <kurtulmeh...@gmail.com> wrote: > Dear All, > I need to do the following: > 1. Capturing 10 bit monochrome video > 2. Recursive Filtering > 3. Display the output to a LCD > 4. Optionally sending the output to Ethernet > > Can you refer development boards and IP's/ VHDL sources to fulfill all > the tasks, > Thanks in Advance Hi, I already recommended this board to some one on this group and I think that the board meets your requirement. It is RTG-005 from Hunt Engineering. Detailed manual is available from their website; and luckily the source code (which they offer in accompanying CD) is in VHDL. Try their Demo in which monochrome video from camera link is grabbed, various image processing filters being managed in FPGA are available in user control (in a gui) and results are displayed on computer screen via usb interface from the board. Hope this helps. /MhArticle: 127447
hi... Im a novice in vhdl based design of fpgas'... I want to know 1. what is the use of core generators? 2. What are xilix primitives and cores? 3. what is the adv of using core generators over std. vhdl files?Article: 127448
<krc.1987@gmail.com> wrote in message news:70108b27-26ca-4463-8e67-fa375cf1e7e9@i12g2000prf.googlegroups.com... > > hi... > > Im a novice in vhdl based design of fpgas'... > > I want to know > > 1. what is the use of core generators? To assist the designer who doesn't have the time/resources/experience/etc. to develop a core on their own. An example might be a DDR memory controller (there are many others). > 2. What are xilix primitives and cores? Things like #1 that only work with Xilinx devices. All of the suppliers have their own stuff that is functionally identical (or nearly so) and yet tied to their devices. > 3. what is the adv of using core generators over std. vhdl files? For the designer, one advantage is that they can possibly get a design completed sooner than if they had to start from nothing. For the supplier, one advantage is that they've locked in a customer to their devices. There are other advantages and disadvantages that others will likely chime in with. As a general guide, skill in hooking up cores is less valuable on the resume than being able to produce cores and hook them up. KJArticle: 127449
The big advantage of using the core generator is to get a logic function that is difficult to infer in a language like VHDL or difficult to attain the required performance. The last statement is very general and refers to someone of average knowledge using VHDL versus Core Generator. There are companies and people who specialise in targetted VHDL, like ourselves, where with some expert knowledge can "guide" the synthesis tool into a preferred result by the style of writting. Usually this targetted VHDL is also used with place and route constraints to achieve well above average results and can do better than the core generator tool in many cases. So short statement is to use core generatot tools to achieve a result quickly for a given FPGA vendor and device family but do be aware that you may need to have a different implementation for a different device family or FPGA vendor. John Adair Enterpoint Ltd. Home of Craignell. The obsolete component solutiion. On 26 Dec, 14:36, "KJ" <kkjenni...@sbcglobal.net> wrote: > <krc.1...@gmail.com> wrote in message > > news:70108b27-26ca-4463-8e67-fa375cf1e7e9@i12g2000prf.googlegroups.com... > > > hi... > > > Im a novice in vhdl based design of fpgas'... > > > I want to know > > > 1. what is the use of core generators? > > To assist the designer who doesn't have the time/resources/experience/etc.= > to develop a core on their own. =A0An example might be a DDR memory contro= ller > (there are many others). > > > 2. What are xilix primitives and cores? > > Things like #1 that only work with Xilinx devices. =A0All of the suppliers= > have their own stuff that is functionally identical (or nearly so) and yet= > tied to their devices. > > > 3. what is the adv of using core generators over std. vhdl files? > > For the designer, one advantage is that they can possibly get a design > completed sooner than if they had to start from nothing. > > For the supplier, one advantage is that they've locked in a customer to > their devices. > > There are other advantages and disadvantages that others will likely chime= > in with. =A0As a general guide, skill in hooking up cores is less valuable= on > the resume than being able to produce cores and hook them up. > > KJ
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z