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Messages from 128300

Article: 128300
Subject: Re: How FPGA downconvert Giga SPS ADC data?
From: chen_yuru888@126.com
Date: Sun, 20 Jan 2008 13:53:26 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 20, 4:27=A0pm, austin <aus...@xilinx.com> wrote:
> Wide parallel data paths,
>
> For example, suppose the conversion is one 12 bit sample every 1 ns:
> BUT the converter transfers 60 bits, every 5ns (one 60 bit word every 5
> ns, or a 200 MHz 60 bit wide data path.
>
> Or, alternatively, the LVDS inputs are clocked on the rising, and
> falling edge of a 500 MHz clock, capturing 12 bits every 1 ns.
>
> Then, inside the FPGA, the path is widened to 60 bits, and processing is
> done of 5 samples, at one time, every 5 ns.
>
> So, no magic: =A0just acknowledge that the sample rate does not need to be=

> equal to the system clock.
>
> Austin
Thank you very much. Yes. The wide bandwidth data coming into FPGA is
the important first step. How about the downconversion? I feel the
downconversion DDC part is still very difficult. I suppose that it
should be here. For a wide band multichannel signal, how to demodulate
them after IF or RF sampling?

Article: 128301
Subject: Re: Sparkfun Spartean3e Board
From: Ben Jackson <ben@ben.com>
Date: Sun, 20 Jan 2008 16:27:26 -0600
Links: << >>  << T >>  << A >>
On 2008-01-20, Bob Smith <usenet@linuxtoys.org> wrote:
>
> I can program the FPGA using JTAG but can not figure out how to get
> ISE to program the SPI flash.

The Xilinx config parts have JTAG, so I don't think I've ever tried
to use Impact directly.

There is a sample picoblaze system that programs SPI flash devices,
though.

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

Article: 128302
Subject: Re: How FPGA downconvert Giga SPS ADC data?
From: austin <austin@xilinx.com>
Date: Sun, 20 Jan 2008 15:51:29 -0800
Links: << >>  << T >>  << A >>
Once sampled, it is "just data":  and as such, there are algorithms that 
do what you want.

I suggest you start by researching "sampled data systems" and read an 
introduction to digital signal processing.

You are asking very basic questions:  you may be a genius is some field, 
but you are a beginner in DSP, so you need to start at the beginning.

Austin

Article: 128303
Subject: Re: How FPGA downconvert Giga SPS ADC data?
From: fl <rxjwg98@gmail.com>
Date: Sun, 20 Jan 2008 16:04:21 -0800 (PST)
Links: << >>  << T >>  << A >>
On 20 jan, 18:51, austin <aus...@xilinx.com> wrote:
> Once sampled, it is "just data": =A0and as such, there are algorithms that=

> do what you want.
>
> I suggest you start by researching "sampled data systems" and read an
> introduction to digital signal processing.
>
> You are asking very basic questions: =A0you may be a genius is some field,=

> but you are a beginner in DSP, so you need to start at the beginning.
>
> Austin

Thank you very much. I am not genius at either side. I read and know a
little about CORDIC in DDC at normal frequency (up to 100MHz in FPGA I
think). I have the impression CORIDIC is relatively slow, because of
iteration operation. In the mix of DDC, what maximum frequency can
CORDIC achieve? I want to know the feasibility. Sure, I am reading a
lot of DSP now. I am interested at : are there some difference in the
architecture for high speed ADC data above GSPS? Thanks again.

Article: 128304
Subject: Re: Debbuging a RISC processor on an FPGA
From: Eric Smith <eric@brouhaha.com>
Date: Sun, 20 Jan 2008 18:08:44 -0800
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> There is nothing magic about Chipscope.  It's a wrapper around a dual
> port RAM.

"There is no extra magic inside the FPGA, just the usual magic."
          -- Göran Bilski

Article: 128305
Subject: Re: How FPGA downconvert Giga SPS ADC data?
From: John_H <newsgroup@johnhandwork.com>
Date: Sun, 20 Jan 2008 21:41:01 -0800
Links: << >>  << T >>  << A >>
fl wrote:
> On 20 jan, 18:51, austin <aus...@xilinx.com> wrote:
>> Once sampled, it is "just data":  and as such, there are algorithms that
>> do what you want.
>>
>> I suggest you start by researching "sampled data systems" and read an
>> introduction to digital signal processing.
>>
>> You are asking very basic questions:  you may be a genius is some field,
>> but you are a beginner in DSP, so you need to start at the beginning.
>>
>> Austin
> 
> Thank you very much. I am not genius at either side. I read and know a
> little about CORDIC in DDC at normal frequency (up to 100MHz in FPGA I
> think). I have the impression CORIDIC is relatively slow, because of
> iteration operation. In the mix of DDC, what maximum frequency can
> CORDIC achieve? I want to know the feasibility. Sure, I am reading a
> lot of DSP now. I am interested at : are there some difference in the
> architecture for high speed ADC data above GSPS? Thanks again.

Iteration is only needed when extracting phase information from an input 
pair.  Digital Down Conversion just modulates the ADC outputs by a fixed 
frequency.  Modulating the inputs by a fixed phase for a single timestep 
is fully pipelined without iteration.

The modulation is typically followed by halfband filter and Cascade 
Integrate Comb (CIC) stages.  The halfband filters for the highest 
frequency doesn't have to be a lot of taps - it's a very small FIR filter.

Fun stuff.  Enjoy your reading!  And visit andraka.com for some 
interesting information.

- John_H

Article: 128306
Subject: Re: Fuzzy Fixed Point Calculating
From: gvark <tsepkovsky@yandex.ru>
Date: Mon, 21 Jan 2008 03:32:43 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 18, 8:54=A0pm, austin <aus...@xilinx.com> wrote:
> http://www.google.com/search?as_q=3Dfuzzy+system+Sugeno&hl=3Den&suggon=3D0=
&...
>
> OK, 1,290 hits. =A0Still a lot of reading.
>
> Austin

Anyone can use google, but if you tryed ITS to read you can convinced
that the question is not be clear. and i search for more fundamental,
detail description...


but thank you just the same

Article: 128307
Subject: Re: Fuzzy Fixed Point Calculating
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Mon, 21 Jan 2008 11:42:28 +0000 (UTC)
Links: << >>  << T >>  << A >>
gvark <tsepkovsky@yandex.ru> wrote:
> On Jan 18, 8:54†pm, austin <aus...@xilinx.com> wrote:
> > http://www.google.com/search?as_q=fuzzy+system+Sugeno&hl=en&suggon=0&...
> >
> > OK, 1,290 hits. †Still a lot of reading.
> >
> > Austin

> Anyone can use google, but if you tryed ITS to read you can convinced
> that the question is not be clear. and i search for more fundamental,
> detail description...

People normally don't like to do others homework. If you ask a question, you
must get other people interested in your question. Some things to consider:
- tell what you have already done
- tell where your specific questions are
- tell, why you work on the problem
- read your posting before sending you typos
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 128308
Subject: Re: Fuzzy Fixed Point Calculating
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 21 Jan 2008 14:49:24 -0000
Links: << >>  << T >>  << A >>
Dear Gvark,
Perhaps this could help you?

http://fuzzy.cs.uni-magdeburg.de/nefprox/

Cheers, Syms. 



Article: 128309
Subject: Re: VHDL Micron memorymodel.
From: ghelbig@lycos.com
Date: Mon, 21 Jan 2008 09:19:58 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 19, 6:05 pm, Bucephalus <davidsullivan1...@gmail.com> wrote:
> I have the Spartan 3e starter kit.
> it has this model RAM on it (MT46V32M16). I have generated the memory
> controller for it, but I would like to play with it on ModelSim first
> to help me understand DDR SDRAM operation. I am reading the spec
> sheet, but I would like to see it work in ModelSim also.
>
> I looked on the Micron site and they said that they don't do VHDL
> memory models any more.
> Has anyone got any clues as to where I could find a memory model for
> the DDR SDRAM that is on the Sparten 3e kit?
>
> David

Modelsim is a mixed language simulator, and you don't really need to
understand the insides of the model to simulate your controller.

Just instantiate the Verilog models in your test bench.  FWIW, the
Micron models are good enough that 99.99% of the errors you will find
are in your controller.  (BTDT :)

G.



Article: 128310
Subject: bi-phase decoding
From: George <romans5_8@earthlink.net>
Date: Mon, 21 Jan 2008 13:16:02 -0500
Links: << >>  << T >>  << A >>
Can anyone point me to some VHDL code for decoding bi-phase mark and 
space formats.

Thanks in advance...

Article: 128311
Subject: Re: VHDL Micron memorymodel.
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Mon, 21 Jan 2008 23:18:21 +0000
Links: << >>  << T >>  << A >>
On Mon, 21 Jan 2008 09:19:58 -0800 (PST), ghelbig@lycos.com wrote:

>On Jan 19, 6:05 pm, Bucephalus <davidsullivan1...@gmail.com> wrote:
>> I have the Spartan 3e starter kit.
>> it has this model RAM on it (MT46V32M16). I have generated the memory
>> controller for it, but I would like to play with it on ModelSim first
>> to help me understand DDR SDRAM operation. I am reading the spec
>> sheet, but I would like to see it work in ModelSim also.
>>
>> I looked on the Micron site and they said that they don't do VHDL
>> memory models any more.
>> Has anyone got any clues as to where I could find a memory model for
>> the DDR SDRAM that is on the Sparten 3e kit?
>>
>> David
>
>Modelsim is a mixed language simulator, and you don't really need to
>understand the insides of the model to simulate your controller.
>
>Just instantiate the Verilog models in your test bench.  FWIW, the
>Micron models are good enough that 99.99% of the errors you will find
>are in your controller.  (BTDT :)

I tried that, a couple of years ago; instead of working, Modelsim told me it
wanted an expensive upgrade to the license.

So I went with the Hynix models, which aren't as nice (being precompiled, no
source to inspect) but worked just fine.

If there aren't any DDR3 models in VHDL that's going to become a problem though.

- Brian

Article: 128312
Subject: Re: effect of xray on fpga electronic circuits
From: tlbs101 <tlbs101@excite.com>
Date: Mon, 21 Jan 2008 16:12:46 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 17, 1:03=A0am, recoder <kurtulmeh...@gmail.com> wrote:
> Dear All,
> =A0As an assignment I have to design a CCD Sensor based FPGA digital
> Camera. However, the Camera will be exposed to XRAY (It will be placed
> behind an Imaging Intensifier). Does anybody know how XRAY affects the
> electronic circuits (The CCD Sensor and the FPGA ). What type of noise
> should I expect and what should I do to prevent it.
> =A0Thanks in advance

Hi,

There are rad-hard CCDs available.  There are also rad-hard FPGA's
available.  Actel uses anti-fuse technology, which is inherently rad-
hard.  We (fellow engineers and I at my aerospace company) use Actel
and Quicklogic FPGAs for space-based applications.

Tom P.
=2E

Article: 128313
Subject: Re: Source of accurate frequency
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Tue, 22 Jan 2008 02:51:58 -0600
Links: << >>  << T >>  << A >>
>We generate 2 output channels (since it is almost for free) and have a
>dual-16 character (really: 128 x 64 pixel) display. We will use a
>312.5 MHz xtal oscillator that promises single-digit ppm accuracy.

Do you have a URL for that part?

>For the first dozen prototypes I will ignore the accuracy question,
>since the average user seems to be content with 20 ppm. But we do not
>want to remain "average"...

>We will provide for a calibration input, and also for the non-volatile
>storage of calibration factors (We already store hundreds of
>frequencies for recall, again because it is almost for free).

Typical lab sources of 10 MHz are sine waves at roughly 0.5 V RMS
or 3V P-P.  I'd probably include some sort of signal conditioning
on any input path.  My straw man is a 50 ohm terminator, an AC coupling
cap, and a couple of resistors (10K?) to bias the input gate.  I'd
probably add clamping diodes and a single-gate buffer just because
I'm feeling paranoid today.  If you add jumpers to bypass the coupling
cap and disconnect the terminator then you can use the terminator
(with no cap) to keep the input away from the switching point when
there is no signal connected.  (I trying to avoid stray oscillators.)

Of course, as long as you have one input, you might as well add a few
more so you can use it to measure frequency of several things at the
same time.  Even if it can't go as fast as you can generate it would
still be a neat toy.

And you might as well add a few extra/spare outputs.

GPS gizmos often need 5V at (say) 100 mA.  And they have RS-232
signals to configure them and get periodic (1 sec) status info.

I was going to suggest a couple of RS-232 connectors, but then I
had the obvious idea...

How about filling all the unused outside area on the board with the
holes for the Digilent 6 pin connectors?  You don't have to install
the connectors, but they will be there when somebody needs them.



Here is another crazy idea that's probably already on your list...

Tradditional PWM outputs are on for N out of M cycles.  You
can dither between N and N+1 for more accurate output at the cost
of low frequecy noise.  You can often do better by distributing the output
"bits" over the whole M cycles rather than bunching them up at one
end.

Why not use the high speed serial outputs to make the dithered
format at a much higher speed?  The jitter will be at a higher
frequency and hence easier to filter out.

It's probably just a couple of lines of code in a few places.





-- 
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 128314
Subject: FPGA decoupling calculation
From: kislo <kislo02@student.sdu.dk>
Date: Tue, 22 Jan 2008 01:00:49 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi, i am currently trying to figure out the number and values of a
decoupling network for a spartan3e 500k (powered by the triple power
supply from texas instruments TPS75003) .. i dont have the luxury of a
software tool to help me simulate and analyse, but i just want a good
estimate which can be supported by theoretic statements. I have read
xapp623 (Power Distribution System (PDS) Design), and calculated the
number and values of capacitors using the method in the application
node. This is the results:
Vccint - 1.2V 8 supply pins
  1 - 4,7uF
  2 - 0.47uF
  5 - 0.047uF

Vccaux - 2.5V 8 supply pins
  1 - 4,7uF
  2 - 0.47uF
  5 - 0.047uF

Vcco - 3.3V 14 supply pins
 1 - 10uF
 2 - 4.7uF
 4 - 0.47uF
 8 - 0.047uF

So here i start wondering ... the application node method is to have
one capacitor per vcc/gnd pin ... according to my knowledge (probably
bad), the decoupling capacitors should be determined from the
(frequency dependent)dynamic current requirement of the fpga. Since im
designing the decoupling network for a unknown fpga utialization i am
only interrested in the worst case scenario. If we take Vccint for
example:

1.2V 5% tolerance - 2A max - 0.5ns risetimes

Inorder for the voltage ripple to be under 5% for the bandwidth of
0.35/0.5ns = 700Mhz, the impedance of the PDS must be below :
(1.2V*0.05)/2A = 0.03R
Inorder for this to be realised i need INSANLY many decoupling
capacitors. By placing 14 0.0047uF, 10 0.047uF, 2 0.47uF I can stay
below 0.03R for a 80Mhz bandwith .... that means i still need to cover
up to 700Mhz :/ .. but this result is far from what result i got from
the xilinx application note ..

I know that the previous calculations assumed that the current demand
for the harmonics were 2A for the entire bandwidth, but how does the
current relate to the harmonics of a signal transitions? if i got
50Mhz swiching frequency will the current drop with 20db/decade, just
as the amplitude of the harmonics?

regards kim










Article: 128315
Subject: Re: Fuzzy Fixed Point Calculating
From: gvark <tsepkovsky@yandex.ru>
Date: Tue, 22 Jan 2008 01:15:05 -0800 (PST)
Links: << >>  << T >>  << A >>
On 21 Jan., 15:49, "Symon" <symon_bre...@hotmail.com> wrote:
> Dear Gvark,
> Perhaps this could help you?
>
> http://fuzzy.cs.uni-magdeburg.de/nefprox/
>
> Cheers, Syms.

I saw it :) thank you!

perhaps can anyone help me in more thin question...

I will be writing in Data Type int in C notation.
 (int32  in Matlab notation)
also i have all value scaled about  coeff K=1000, and become
mambership function in diapason [0 ..K].
I'm not sure, that i have it rigth maked.
 For defuzzification in Anfis i must use
 Out= max (Rules*Outcoeff)
than norm defuzzyfication
Out= sum(Rules*Outcoeff)/sum(Rules),
 in my simulation work bad (in online training application).

Redgars.


Article: 128316
Subject: Re: Source of accurate frequency
From: -jg <Jim.Granville@gmail.com>
Date: Tue, 22 Jan 2008 01:43:30 -0800 (PST)
Links: << >>  << T >>  << A >>
Hal Murray wrote:
# Of course, as long as you have one input, you might as well add a
few
# more so you can use it to measure frequency of several things at the
# same time.  Even if it can't go as fast as you can generate it would
# still be a neat toy.

I've already suggested dual reciprocal Frequency counters [to keep
Peter busy :) ]
and a very good front end, for this is the AnalogDevices  PLL
Synthesizers/VCOs
family. (ADF40xx ADF41xx) - small and low cost.

 These have a MuxOut mode, that the designer must have thought about
more generic/interesting uses than synthesisers, as they can be used
as front
ends for continuous reciprocal counters (no gates, so no precision
corners)
- with these, if you want to average over longer, or very long times,
you can
do that with running numbers in the background.

-jg

Article: 128317
Subject: Re: FPGA decoupling calculation
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 22 Jan 2008 10:21:46 -0000
Links: << >>  << T >>  << A >>
Hi Kim,
I've not got much time so here's a few pointers:-

IMO, Xilinx publish excessive requirements which covers their arse if 
anything should go wrong. Fair enough. However, you should know that it's 
fairly difficult to get this wrong, indeed, some folks (not me!) on this 
newsgroup apparently use very few bypass caps.

Free capacitor parameter stuff.:-
http://www.murata.com/designlib/mcsil/index.html

Above a few 10's of MHz, all same sized caps have the same impedance. (See 
murata thing above) Just use 0402 1uF for everything. One per pin is more 
than enough. Make sure your board has a ground plane, try to use two vias 
for each cap terminal.

Here's some stuff on where to place your caps.

http://www.sigcon.com/pubsIndex.htm#bypass%20capacitors

Or, ignore that stuff, sooo 20th C. Better bypass here:-
http://www.x2y.com/

Finally, there are caps hidden in the FPGAs themselves. Go to your 
university's chemistry dept. and ask for some HF to find them!

Also, STFW ! ;-)

HTH, Syms. 



Article: 128318
Subject: Re: FPGA decoupling calculation
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Tue, 22 Jan 2008 11:06:37 +0000 (UTC)
Links: << >>  << T >>  << A >>
Symon <symon_brewer@hotmail.com> wrote:
> Hi Kim,
> I've not got much time so here's a few pointers:-

> IMO, Xilinx publish excessive requirements which covers their arse if 
> anything should go wrong. Fair enough. However, you should know that it's 
> fairly difficult to get this wrong, indeed, some folks (not me!) on this 
> newsgroup apparently use very few bypass caps.

If you route the Xilinx recommended number of CAPs, you either have no room
for signal breakout or the bypass caps end up far away from the FPGA. The
calculation also seems to forget about the interinsic C and L of the supply
layers.

My rule is: - try to implement a good ground plain, no swiss cheese
            - try to place one 0603/0402 cap in X5/7R near each supply pin
              with the traces to the FPGA as short as possible

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 128319
Subject: Re: effect of xray on fpga electronic circuits
From: Thiemo Nordenholz <list+jvrjb701jlw6bwj0@thiemo.net>
Date: 22 Jan 2008 11:19:41 GMT
Links: << >>  << T >>  << A >>
> Dear All,
>  As an assignment I have to design a CCD Sensor based FPGA digital
> Camera. However, the Camera will be exposed to XRAY (It will be placed
> behind an Imaging Intensifier). Does anybody know how XRAY affects the
> electronic circuits (The CCD Sensor and the FPGA ). What type of noise
> should I expect and what should I do to prevent it.

As you did not mention it, perhaps it is yet unknown: The 'NASA office of
Logic Design' did quite some studies about the influence of differend kinds
of radiation on both off-the-shelf and 'rad hard' types of electronics. Did
not see anything on CCDs, but FPGAs seem to be definitely in scope there.

There's loads of information about their results and learned lessons on
http://klabs.org/ , which is their web site.

Hope this helps,
  Thiemo

-- 
Query a PGP key server (e.g. http://www.pgp.net/) for my public key 41068629.
Strange sender address? Please see http://www.thiemo.net/misc/list-mail.shtml

Article: 128320
Subject: Re: FPGA decoupling calculation
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 22 Jan 2008 11:20:50 -0000
Links: << >>  << T >>  << A >>
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message 
news:fn4int$d1c$1@lnx107.hrz.tu-darmstadt.de...
> Symon <symon_brewer@hotmail.com> wrote:
>> Hi Kim,
>> I've not got much time so here's a few pointers:-
>
>> IMO, Xilinx publish excessive requirements which covers their arse if
>> anything should go wrong. Fair enough. However, you should know that it's
>> fairly difficult to get this wrong, indeed, some folks (not me!) on this
>> newsgroup apparently use very few bypass caps.
>
> If you route the Xilinx recommended number of CAPs, you either have no 
> room
> for signal breakout or the bypass caps end up far away from the FPGA. The
> calculation also seems to forget about the interinsic C and L of the 
> supply
> layers.
>
Hi Uwe,
Indeed. I notice their own dev. boards don't follow the XAPP recomendation.
Hmmm.
Cheers, Syms. 



Article: 128321
Subject: Re: Source of accurate frequency
From: Allan Herriman <allanherriman@hotmail.com>
Date: Tue, 22 Jan 2008 23:07:29 +1100
Links: << >>  << T >>  << A >>
On Tue, 22 Jan 2008 02:51:58 -0600,
hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote:

>>We generate 2 output channels (since it is almost for free) and have a
>>dual-16 character (really: 128 x 64 pixel) display. We will use a
>>312.5 MHz xtal oscillator that promises single-digit ppm accuracy.
>
>Do you have a URL for that part?
>
>>For the first dozen prototypes I will ignore the accuracy question,
>>since the average user seems to be content with 20 ppm. But we do not
>>want to remain "average"...
>
>>We will provide for a calibration input, and also for the non-volatile
>>storage of calibration factors (We already store hundreds of
>>frequencies for recall, again because it is almost for free).
>
>Typical lab sources of 10 MHz are sine waves at roughly 0.5 V RMS
>or 3V P-P.  I'd probably include some sort of signal conditioning
>on any input path.  My straw man is a 50 ohm terminator, an AC coupling
>cap, and a couple of resistors (10K?) to bias the input gate.  I'd
>probably add clamping diodes and a single-gate buffer just because
>I'm feeling paranoid today.  If you add jumpers to bypass the coupling
>cap and disconnect the terminator then you can use the terminator
>(with no cap) to keep the input away from the switching point when
>there is no signal connected.  (I trying to avoid stray oscillators.)

I recommend using a differential input buffer instead of a CMOS/TTL
type for better sensitivity and lower jitter with sinewave inputs.

These are also available in single-gate packages,e.g. 	
FIN1101
"3.5 ps max random jitter and 135 ps max deterministic jitter"
http://www.fairchildsemi.com/pf/FI/FIN1101.html
http://search.digikey.com/scripts/DkSearch/dksus.dll?keywords=FIN1101+

NB4N527S
"2 ps Maximum RMS Jitter"
http://www.onsemi.com/PowerSolutions/product.do?id=NB4N527S


Back in the day, I used to make low phase noise reference clock
buffers out of ECL-like logic made from discrete BJTs.  I wouldn't do
that now though.

Regards,
Allan

Article: 128322
Subject: Re: FPGA decoupling calculation
From: Allan Herriman <allanherriman@hotmail.com>
Date: Tue, 22 Jan 2008 23:15:28 +1100
Links: << >>  << T >>  << A >>
On Tue, 22 Jan 2008 01:00:49 -0800 (PST), kislo
<kislo02@student.sdu.dk> wrote:

>... decoupling network ...
> .. i dont have the luxury of a software tool to help me simulate and analyse

The headers in your post suggest you are using Windows.  That's good,
because you can download LTSpice and use that.

http://www.linear.com/designtools/software/switchercad.jsp

Like all simulations, the results are only as good as your models.  In
particular, you'll end up with lumped approximations which may result
in resonances that don't appear on the real board.
(The real board will have distributed capacitance, and also dielectric
loss (which gets rid of a lot of the impedance peaks).)

Regards,
Allan

Article: 128323
Subject: Re: FPGA decoupling calculation
From: kislo <kislo02@student.sdu.dk>
Date: Tue, 22 Jan 2008 04:32:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On 22 Jan., 12:20, "Symon" <symon_bre...@hotmail.com> wrote:
> "Uwe Bonnes" <b...@hertz.ikp.physik.tu-darmstadt.de> wrote in message
>
> news:fn4int$d1c$1@lnx107.hrz.tu-darmstadt.de...
>
>
>
> > Symon <symon_bre...@hotmail.com> wrote:
> >> Hi Kim,
> >> I've not got much time so here's a few pointers:-
>
> >> IMO, Xilinx publish excessive requirements which covers their arse if
> >> anything should go wrong. Fair enough. However, you should know that it=
's
> >> fairly difficult to get this wrong, indeed, some folks (not me!) on thi=
s
> >> newsgroup apparently use very few bypass caps.
>
> > If you route the Xilinx recommended number of CAPs, you either have no
> > room
> > for signal breakout or the bypass caps end up far away from the FPGA. Th=
e
> > calculation also seems to forget about the interinsic C and L of the
> > supply
> > layers.
>
> Hi Uwe,
> Indeed. I notice their own dev. boards don't follow the XAPP recomendation=
.
> Hmmm.
> Cheers, Syms.- Skjul tekst i anf=F8rselstegn -
>
> - Vis tekst i anf=F8rselstegn -

yea i noticed that too, the Spartan3E starter board dosent follow the
XAPP recommendation

Article: 128324
Subject: Re: FPGA decoupling calculation
From: KJ <kkjennings@sbcglobal.net>
Date: Tue, 22 Jan 2008 05:02:42 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 22, 4:00=A0am, kislo <kisl...@student.sdu.dk> wrote:
>i dont have the luxury of a
> software tool to help me simulate and analyse, but i just want a good
> estimate which can be supported by theoretic statements.

A spreadsheet can give a rough estimate as well...more later

>I have read
> xapp623 (Power Distribution System (PDS) Design), and calculated the
> number and values of capacitors using the method in the application
> node. This is the results:
> Vccint - 1.2V 8 supply pins
> =A0 1 - 4,7uF
> =A0 2 - 0.47uF
> =A0 5 - 0.047uF
>
> Vccaux - 2.5V 8 supply pins
> =A0 1 - 4,7uF
> =A0 2 - 0.47uF
> =A0 5 - 0.047uF
>
> Vcco - 3.3V 14 supply pins
> =A01 - 10uF
> =A02 - 4.7uF
> =A04 - 0.47uF
> =A08 - 0.047uF
>
> So here i start wondering ... the application node method is to have
> one capacitor per vcc/gnd pin ... according to my knowledge (probably
> bad), the decoupling capacitors should be determined from the
> (frequency dependent)dynamic current requirement of the fpga. Since im
> designing the decoupling network for a unknown fpga utialization i am
> only interrested in the worst case scenario. If we take Vccint for
> example:
>
> 1.2V 5% tolerance - 2A max - 0.5ns risetimes
>
> Inorder for the voltage ripple to be under 5% for the bandwidth of
> 0.35/0.5ns =3D 700Mhz, the impedance of the PDS must be below :
> (1.2V*0.05)/2A =3D 0.03R

Look up the specs on the caps for the parasitic L and R.  Now you can
build a spreadsheet that calculates the complex impedance Z as a
function of frequency of each cap type (i.e. 10uF, 4.7uF, etc.).
Knowing that, you can now compute the impedance of your PDS as a
function of frequency as well.  Then graph it and you'll see your
expected impedance profile.  You'll also want to factor in your PCB
impedance as well, but start with the caps.

>
> I know that the previous calculations assumed that the current demand
> for the harmonics were 2A for the entire bandwidth, but how does the
> current relate to the harmonics of a signal transitions? if i got
> 50Mhz swiching frequency will the current drop with 20db/decade, just
> as the amplitude of the harmonics?

I'm not sure where you're getting the 20dB/decade assumption since the
drop would depend entirely on the characteristics of the functions
being generated.  If you could build a really good pseudo random
generator set of outputs from the FPGA, then one would expect a
roughly flat frequency response across the entire frequency band.
Most real designs though are not terribly random and would have some
rolloff but trying to take advantage of that in designing the power
delivery for an unknown FPGA design might not be the best approach.

By the way, going about figuring out the number and values of caps to
use based on current demand and voltage ripple over a frequency range
as you're doing is exactly the right approach.  Don't forget about the
PCB stackup though, closely spaced power/ground plane pairs supply the
low impedance path that you'll need to connect up the caps (which are
the source of charge for the load) with the load itself.  This PCB
impedance can be factored into that same spreadsheet model.

Kevin Jennings



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