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Peter Alfke wrote: > We will use a > 312.5 MHz xtal oscillator that promises single-digit ppm accuracy. > For the first dozen prototypes I will ignore the accuracy question, > since the average user seems to be content with 20 ppm. But we do not > want to remain "average"... You could maybe allow for something simple like maxim's DS32KHz which comes straight out of the box at 2ppm over 0-40'C, or the DS3231 which has more trim options, but may over-complicate the details. Maxim also have a DS76KHz, but that's not so widely stocked. -jgArticle: 128276
>Maxim also have a DS76KHz, but that's not so widely stocked. What's interesting about 76.8 KHz? Who uses that, or some (sub)multiple of it? -- These are my opinions, not necessarily my employer's. I hate spam.Article: 128277
>Yes, grey hair, but (still) lots of it ! >Today is my 20th anniversary at Xilinx. >It has been a very good experience, in every respect... >Peter It's been very good for us too. Many thanks. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 128278
>So I was thinking of having the program counter as my trigger, so when >the end is reached then I wanna somehow read out the values of the >register with Chipscope. Or each time the program counter changes I read >out the values of the Registers to see if the results are as expected >and could so also immediately identify the instructions that have caused >problems. SO far i have just debugged a simple counter with the >chipscope so I hope the approach with the RISC also works as I have just >described. There is nothing magic about Chipscope. It's a wrapper around a dual port RAM. You probably don't want it to grab all Registers when X happens. It's hard to do that on a single clock cycle. What would you want in a RAM if you knew there was a problem? It might make sense to grab the register (address and value) whenever X happens, maybe when X is write to a register. It might make sense to grab the PC whenever a branch happens. As a hack, you can ignore Chipscope and figure out how to wiggle a few external wires and then sprinkle debugging crap into your code. If the wires are connected to LEDs, you can use them for low level debugging just by looking at them. You can also connect a scope or logic analyzer. This assumes the CPU (hardware and software) is mostly working. I'd use one signal for a trigger and others for X happened. With modern digital scopes, you can see the pattern of X leading up to the error that triggers the scope. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 128279
Peter Alfke wrote: > I have no intentions of burdening the box with a >>$10 precision > oscillator, I rather provide a separate calibration capability, for > manufacturing and for ultra-demanding users, where a few hundred > dollars do not matter. Maybe you can use a big enough case for your clock generator and then mount it as an optional module inside. Looks like this is nice frequency standard: http://www.kernco.com/index.php?page=commercial Frequency stability is 5*10^-11. Another feature is "low cost". I've sent them an eMail what this means in USD :-) -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 128280
Hal Murray wrote: > If you have a stable local clock, you can calibrate it > over the net. Use NTP - Network Time Protocol. I don't think this will be very accurate. The wikipedia article says, that it provides accuracies of 200 microseconds: http://en.wikipedia.org/wiki/Network_Time_Protocol Maybe you can get higher accuracy by sending millions of requests over a long time and averaging, but if thousands of customers are sending millions of requests, this will be better than any denial-of-service attack and the NTP provider has to shutdown the service. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 128281
On Sat, 19 Jan 2008 23:46:13 -0600, hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > > >>Maxim also have a DS76KHz, but that's not so widely stocked. > >What's interesting about 76.8 KHz? Who uses that, or some >(sub)multiple of it? Pagers, hence the availability of low power, low cost, small sized devices. Regards, AllanArticle: 128282
>> If you have a stable local clock, you can calibrate it >> over the net. Use NTP - Network Time Protocol. > >I don't think this will be very accurate. The wikipedia article says, that >it provides accuracies of 200 microseconds: A typical low cost crystal is much more stable than it is accurate. The main source of instability is temperature. It will vary by roughly 1 ppm per C. It's likely to be off by 10 or 100 ppm from the number printed on the package. If you know how far off it is, you can sometimes correct in software. If I can measure time to within 1 second, then I have to wait 1 million seconds to calibrate a crystal to within 1 ppm. That's 12 days. (That's probably ignoring a factor of two or such.) PCs keep much better time after you make that sort of correction. If you run ntpd, you can look at the "drift" file to see how far off your crystal is. (That error may include software errors.) Several handy machines say: 49.665, 117.415, 101.876, -10.274, 130.319, and 128.166 So if we assume the temperature is stable and that I can calibrate a crystal to within 1 ppm, then I can reduce the error by a factor of 10 or 100, depending on how far off the crystal was. > Maybe you can get higher accuracy by sending millions of requests over a > long time and averaging, but if thousands of customers are sending millions > of requests, this will be better than any denial-of-service attack and the > NTP provider has to shutdown the service. Sending lots of packets is not likely to help. You probably want to send a handful (say 10) 1 minute apart and discard any with a long round trip time. Then wait a long time, then send another batch of 10. That's assuming the network topology doesn't change while you are waiting, or if it does, that the to/from times are ballanced on both measurements so you can correct by half the round trip time to get the real time. Filtering out network quirks gets "interesting" in the Chinese sense. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 128283
Hal Murray wrote: > >Maxim also have a DS76KHz, but that's not so widely stocked. > > What's interesting about 76.8 KHz? Who uses that, or some > (sub)multiple of it? I think infra-red remote controls use 38.4KHz, but I'm not sure why they'd need a TCXO for that - so there must be another application :) 76.8 IS also a Standard Baud-multiple, so perhaps there is a Baud-based reason ? (tho that also does not need tcxo...) Just figured it out: 76.8 allows one hundredths of a second precision for stop-watch type application ie /768 to 10ms. - doing that from a 32.768 needs divide by 327.68 -jgArticle: 128284
On Jan 17, 2:52 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > On 16 Jan., 05:23, Dick <leeyei...@gmail.com> wrote: > > > Hi all, > > > I'm a new guy in fpga. I need to implement a GMSK in altera fpga. I > > plan to design a gaussian filter but I don't know how to do it. > > The nice property of the gauss function is, that if you fold more or > less any function with itself multiple times the result converges to a > gauss function. Therefore you can build a gauss filter by cascading > multiple simple filters. For exampel four consecutive boxcar filters > provide a good aproximation to a gauss filter. > > If you use a CIC-implementation of the boxcar you end up with an > extremely efficient implementation. (No multipliers, four adders) > > Kolja Sulimma Thank you. I used CIC implemetation of the boxcar (cascaded 3 and 5), really an extremely efficient imlementationt.Article: 128285
On Sat, 19 Jan 2008 18:05:55 -0800 (PST), Bucephalus
<davidsullivan1974@gmail.com> wrote:
>
>I have the Spartan 3e starter kit.
>it has this model RAM on it (MT46V32M16). I have generated the memory
>controller for it, but I would like to play with it on ModelSim first
>to help me understand DDR SDRAM operation. I am reading the spec
>sheet, but I would like to see it work in ModelSim also.
>
>I looked on the Micron site and they said that they don't do VHDL
>memory models any more.
>Has anyone got any clues as to where I could find a memory model for
>the DDR SDRAM that is on the Sparten 3e kit?
Hynix still have VHDL models for DDR and DDR2 memories that
match this Micron device. Since the DDR(2) behaviour is
JEDEC-standardised, the difference in manufacturer should
not matter unless you use some obscure feature that's supported
by Micron but not by Hynix (I'm not aware of any such; you would
need to read the data sheet carefully).
I think the MT46V32M16 is 32M x 4 banks x 16 bits, DDR (not DDR2).
If I'm right, then you need this file (sorry about the 3-line link):
http://www.hynix.com/inc/pdfDownload.jsp
?path=/datasheet/simo/new/
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1).zip
but you can find the whole set at
http://www.hynix.com/products/support/simulationmodel.jsp?menuNo=1&m=8&s=3
Everyone else (Micron, Qimonda) seems to have stopped supporting
VHDL models. Hynix don't have VHDL for their newest parts (DDR3).
Since the models are quite big and complex, you may find that
the free Modelsim Xilinx edition will slow down to a crawl
if you try to simulate them. It's worth a try, though.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 128286Hello John, Does Enterpoint have something like this: http://wacco.mveas.com/ ? THX, B.Article: 128287
On Jan 20, 4:19 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sat, 19 Jan 2008 18:05:55 -0800 (PST), Bucephalus > > <davidsullivan1...@gmail.com> wrote: > > >I have the Spartan 3e starter kit. > >it has this model RAM on it (MT46V32M16). I have generated the memory > >controller for it, but I would like to play with it on ModelSim first > >to help me understand DDR SDRAM operation. I am reading the spec > >sheet, but I would like to see it work in ModelSim also. > > >I looked on the Micron site and they said that they don't do VHDL > >memory models any more. > >Has anyone got any clues as to where I could find a memory model for > >the DDR SDRAM that is on the Sparten 3e kit? > > Hynix still have VHDL models for DDR and DDR2 memories that > match this Micron device. Since the DDR(2) behaviour is > JEDEC-standardised, the difference in manufacturer should > not matter unless you use some obscure feature that's supported > by Micron but not by Hynix (I'm not aware of any such; you would > need to read the data sheet carefully). > > I think the MT46V32M16 is 32M x 4 banks x 16 bits, DDR (not DDR2). > If I'm right, then you need this file (sorry about the 3-line link): > http://www.hynix.com/inc/pdfDownload.jsp > ?path=/datasheet/simo/new/ > DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1).zip > but you can find the whole set at > > http://www.hynix.com/products/support/simulationmodel.jsp?menuNo=1&m=... > > Everyone else (Micron, Qimonda) seems to have stopped supporting > VHDL models. Hynix don't have VHDL for their newest parts (DDR3). > > Since the models are quite big and complex, you may find that > the free Modelsim Xilinx edition will slow down to a crawl > if you try to simulate them. It's worth a try, though. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Thanks for the help guys. I will look at these models tomorrow. Maybe if verilog is more popular and there is more support for it, I think I will start learning it. cheers DavidArticle: 128288
On Jan 20, 7:57 am, Bucephalus <davidsullivan1...@gmail.com> wrote: > On Jan 20, 4:19 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: > > > > > On Sat, 19 Jan 2008 18:05:55 -0800 (PST), Bucephalus > > > <davidsullivan1...@gmail.com> wrote: > > > >I have the Spartan 3e starter kit. > > >it has this model RAM on it (MT46V32M16). I have generated the memory > > >controller for it, but I would like to play with it on ModelSim first > > >to help me understand DDR SDRAM operation. I am reading the spec > > >sheet, but I would like to see it work in ModelSim also. > > > >I looked on the Micron site and they said that they don't do VHDL > > >memory models any more. > > >Has anyone got any clues as to where I could find a memory model for > > >the DDR SDRAM that is on the Sparten 3e kit? > > > Hynix still have VHDL models for DDR and DDR2 memories that > > match this Micron device. Since the DDR(2) behaviour is > > JEDEC-standardised, the difference in manufacturer should > > not matter unless you use some obscure feature that's supported > > by Micron but not by Hynix (I'm not aware of any such; you would > > need to read the data sheet carefully). > > > I think the MT46V32M16 is 32M x 4 banks x 16 bits, DDR (not DDR2). > > If I'm right, then you need this file (sorry about the 3-line link): > > http://www.hynix.com/inc/pdfDownload.jsp > > ?path=/datasheet/simo/new/ > > DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1).zip > > but you can find the whole set at > > >http://www.hynix.com/products/support/simulationmodel.jsp?menuNo=1&m=... > > > Everyone else (Micron, Qimonda) seems to have stopped supporting > > VHDL models. Hynix don't have VHDL for their newest parts (DDR3). > > > Since the models are quite big and complex, you may find that > > the free Modelsim Xilinx edition will slow down to a crawl > > if you try to simulate them. It's worth a try, though. > > -- > > Jonathan Bromley, Consultant > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > Thanks for the help guys. > I will look at these models tomorrow. Maybe if verilog is more popular > and there is more support for it, I think I will start learning it. > cheers > David Am I missing something? I can't seem to find any vhdl in that link you sent me. The hynix ram. This is the second time I have tried that ram actually because I went to hynix yesterday and I sourced that file. I couldn't find any VHDL in there, just like now when I downloaded the link. Am I supposed to run one of those other files to generate it? DavidArticle: 128289
On Sun, 20 Jan 2008 08:06:51 -0800 (PST), Bucephalus <davidsullivan1974@gmail.com> wrote: >Am I missing something? I can't seem to find any vhdl in that No, you're not; I was missing something - the fact that Hynix don't publish the source code, but only the models compiled for a specific version of a simulator. The compiled library units for ModelSim are clearly there, but since their creation date is 2003 it seems likely that it won't work with the version of ModelSim you're using now. Similarly, the compiler output for VCS is there (the .o files). Apologies for the red herring. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 128290
Hal Murray wrote: <snip> > A typical low cost crystal is much more stable than it is accurate. > > The main source of instability is temperature. It will vary by roughly > 1 ppm per C. It's likely to be off by 10 or 100 ppm from the number > printed on the package. <snip> Beware. Cheap crystals can be far from stable. I've watched inexpensive 100 ppm frequency sources "tick" and "pop" their frequencies around, apparently borrowing some piezoelectric effect from the crystal. It may be that the device is warming up when I see these small but abrupt changes in frequency. As long as the designer is aware of whether their oscillator exhibits discrete or continuous changes in frequency, special applications can be kept clean. As far as stability, close-in phase noise could be a measure of stability. Cheap oscillators tend to have quite a bit of low frequency noise; they're much better at keeping the clock periods within many 10s of picoseconds of average than they are at being "stable" depending on what your needs are. Different people have different definitions of stability. Me - I'd hate to see a frequency meter or frequency source suddenly change the last 3 digits of a 9-digit counter from one apparently "stable" value to a different set of "consistent" digits. - John_HArticle: 128291
Hi I have a SparkFun Spartan3e development board which uses an ATMEL AT45DB161D serial SPI flash for configuration. Here is a photo: http://www.sparkfun.com/commerce/images/Spartan3EEvalBoard-01-L.jpg I can program the FPGA using JTAG but can not figure out how to get ISE to program the SPI flash. All my attempts end with "Program Failed" messages. SparkFun has a utility to do this but they did not include direction on how to install and use the utility. Also this _should_ work from ISE, right? Is anyone using this board? Any pointers on generating a .mcs file? Any pointers on how to program the SPI flash? The Verilog project is just the four bit counter in the Xilinx tutorial. thanks in advance Bob SmithArticle: 128292
On Jan 20, 11:53 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sun, 20 Jan 2008 08:06:51 -0800 (PST), > > Bucephalus <davidsullivan1...@gmail.com> wrote: > >Am I missing something? I can't seem to find any vhdl in that > > No, you're not; I was missing something - the fact that Hynix > don't publish the source code, but only the models compiled for > a specific version of a simulator. > > The compiled library units for ModelSim are clearly there, > but since their creation date is 2003 it seems likely that > it won't work with the version of ModelSim you're using now. > > Similarly, the compiler output for VCS is there (the .o files). > > Apologies for the red herring. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. I was asking Mentor Graphics support some questions about ModelSim compiled models recently, and I was told that latter versions of ModelSim can use compiled models created by an earlier version by using the refresh command. I was also told that SE can use models compiled by PE. I did not ask if there was a limit to how big of a difference there could be between the versions, but you might try getting the compiled models and refreshing them with your copy of ModelSim and see if they will work. I also did not ask if the Xilinx specific version of ModelSim could use models compiled by PE or SE because we already need a mixed language version with the Swift Model support. Regards, John McCaskill www.FasterTechnology.comArticle: 128293
Bob Smith wrote: > Hi > > I have a SparkFun Spartan3e development board which uses an ATMEL > AT45DB161D serial SPI flash for configuration. Here is a photo: > http://www.sparkfun.com/commerce/images/Spartan3EEvalBoard-01-L.jpg > > I can program the FPGA using JTAG but can not figure out how to get > ISE to program the SPI flash. All my attempts end with "Program > Failed" messages. SparkFun has a utility to do this but they did > not include direction on how to install and use the utility. Also > this _should_ work from ISE, right? > > > Is anyone using this board? > Any pointers on generating a .mcs file? > Any pointers on how to program the SPI flash? > > The Verilog project is just the four bit counter in the Xilinx > tutorial. > > thanks in advance > Bob Smith I didn't think the SPI had a native link from the Xilinx tools. See (for example) the SPI programming designs for the Xilinx Spartan3E starter kit. Look for "SPI" on the page: http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm - John_HArticle: 128294
On Fri, 18 Jan 2008 14:49:46 -0800 (PST), Peter Alfke <peter@xilinx.com> wrote: >This is slightly off-topic: >I have mentioned before that I am in the process of designing (and >manufacturing in limited volume) a clock-generator box (1 Hz to 1.5 >GHz in 1 Hz increments). We debated some jitter issues... >It's tough to get a very accurate reference xtal (2 ppm should be >possible, 20 ppm is easy) >I might include a simple calibration mechanism (any reasonable amount >of logic is free in the Virtex-5 FPGA), but from where do I get a very >accurate reference frequency input of any value ? > >Decades ago, the major TV stations kept the color subcarrier very >accurate (much better than 0.01 ppm), but that service has ben >abandoned. WWV needs a short-wave receiver, or at least a good >selective amplifier. >I am asking this smart group for some creative ideas. GPS ? >I indicate the frequency on a 9-digit display, so it would be >desirable to be able to guarantee better than 1 ppm (after calibration >for at least a few days. Temperature drift is not a big issue in a lab >instrument...) >Peter Alfke We've been buying some 40 MHz 7mm surface-mount VCXOs that have pretty good phase noise behavior and tc well below 0.1 ppm/k... I have some test notes here somewhere. In time domain, their jitter is a few ps RMS out to a corner around 1 millisecond, where jitter starts to increase linearly with period, to around 4 ns per second. We factory-trim the boxes that use this, using a delta-sigma dac (RC lowpassed straight off a Spartan3 pin!) to trim the vcxo dead on. I'll look up the mfr/pn Monday if you're interested. I think we get them from Digikey. One trick is to keep them thermally isolated to keep millikelvin temperature wafts from making low-frequency phase noise. A really good SC-cut OCXO can have jitter of a few ps per second. Big bucks. We have an ebay rubidium standard for checking our counters. We send the counters out to a cal lab regularly, the rubidium occasionally, and everything always agrees to 25 ppb or so. We'll get a GPS source one of these days, and I guess we could save some cal lab costs. JohnArticle: 128295
"Frank Buss" <fb@frank-buss.de> wrote in message news:1ljnuafwmnylp.3pyu5unornyl.dlg@40tude.net... > Peter Alfke wrote: > > Maybe you can use a big enough case for your clock generator and then > mount > it as an optional module inside. Looks like this is nice frequency > standard: > > http://www.kernco.com/index.php?page=commercial > > Frequency stability is 5*10^-11. Another feature is "low cost". I've sent > them an eMail what this means in USD :-) > Here's a rubidium reference for a reasonable price (for the job it does!): http://www.thinksrs.com/downloads/PDFs/Catalog/PRS10c.pdfArticle: 128296
Hi, I have a question about ADC input to FPGA. Although I read some past thread on ADC connection with ADC. I still don't understand how to downconvert Giga Hz adc in FPGA. The new ADC, for example ADC08D1500, can support 1.5GSPS or even more. Its manufacture gives the demo prototype which has Xilinx FPGA. To downconverter the ADC data, I think the FPGA digital filter must be upto 1.5GSPS. Then, low throught data can be obtained by decimation. The fastest multiplier in FPGA is DSP48(?). It can be as fast as GSPS now? Could you tell me what's the technique to downconvert GSPS data in FPGA? Thanks in advance.Article: 128297
On 20 jan, 15:15, fl <rxjw...@gmail.com> wrote: > Hi, > I have a question about ADC input to FPGA. Although I read some past > thread on ADC connection with ADC. I still don't understand how to > downconvert Giga Hz adc in FPGA. The new ADC, for example =A0ADC08D1500, > can support 1.5GSPS or even more. Its manufacture gives the demo > prototype which has Xilinx FPGA. To downconverter the ADC data, I > think the FPGA digital filter must be upto 1.5GSPS. Then, low throught > data can be obtained by decimation. The fastest multiplier in FPGA is > DSP48(?). It can be as fast as GSPS now? Could you tell me what's the > technique to downconvert GSPS data in FPGA? Thanks in advance. There should be several polyphase filters to do the filtering at the maximum FPGA speed, then decimation? It is still a little believable to me because I suspect the multiple polyphase filters need a lot of DSP48 to give an decent filter performance. What's your idea? Thanks.Article: 128298
Usually there are either 2 seperate headers for JTAG and SPI programming or 1 header with a signal switch. Looking at the photo on your link there appear to be 2 headers with JTAG signals but with different pin layouts so these may be the 2 headers. Look up Xilinx XAPP455 for more information on the wiring aspect of using JTAG headers for SPI programming. There is SPI programming support, in the Impact part of ISE, in the last few versions of ISE. It is a seperate menu option from the boundary scan option. Once you find the option ensure the prom selection matches exactly your SPI device otherwise you will get errors. Your may also need to hold Prog_B low whilst programming the SPI to avoid drive conflicts. If you have a Parallel Cable III look-alike be careful of using extension cables. Often these cause issues. John Adair Enterpoint Ltd. - Home of Drigmorn1. The Low Cost FPGA Development Board. On 20 Jan, 18:41, Bob Smith <use...@linuxtoys.org> wrote: > Hi > > I have a SparkFun Spartan3e development board which uses an ATMEL > AT45DB161D serial SPI flash for configuration. =A0Here is a photo:http://w= ww.sparkfun.com/commerce/images/Spartan3EEvalBoard-01-L.jpg > > I can program the FPGA using JTAG but can not figure out how to get > ISE to program the SPI flash. =A0All my attempts end with "Program > Failed" messages. =A0SparkFun has a utility to do this but they did > not include direction on how to install and use the utility. =A0Also > this _should_ work from ISE, right? > > Is anyone using this board? > Any pointers on generating a .mcs file? > Any pointers on how to program the SPI flash? > > The Verilog =A0project is just the four bit counter in the Xilinx > tutorial. > > thanks in advance > Bob SmithArticle: 128299
Wide parallel data paths, For example, suppose the conversion is one 12 bit sample every 1 ns: BUT the converter transfers 60 bits, every 5ns (one 60 bit word every 5 ns, or a 200 MHz 60 bit wide data path. Or, alternatively, the LVDS inputs are clocked on the rising, and falling edge of a 500 MHz clock, capturing 12 bits every 1 ns. Then, inside the FPGA, the path is widened to 60 bits, and processing is done of 5 samples, at one time, every 5 ns. So, no magic: just acknowledge that the sample rate does not need to be equal to the system clock. Austin
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