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On 29 Jan., 08:54, "Maki" <veselic...@eunet.yu> wrote: > >> >http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdf > > >> > eh, I wanted todo this, so now already instantly feeling better! > >> > and I do have a smile :) on my face right now. > > >> Hi Antti, > >> :) from me. > >> Is it Actel FPGA on the last page? > > >> Regards, > >> -- > >> M.Veselic > >> Sigma Lab. > > > YES > > It must be Fusion. I've never seen pricing for this family. The board is > very cheap... > > Regards, > -- > M.Veselic > Sigma Lab no, fusion is more expensive. the cheapest Actel is A3P060 (A3P030 think is still not in full production available) 060 is very small, so in order to achive the full functions needed some functions are moved from FPGA to small flash MCU, that gives best price for the functionality. when trying to implement SLOW functions that are easy for sub 1 USD MCU in the FPGA the FPGA add-on price (device upgrade penalty) is more than 1 USD sub 6 USD FPGA designs are pretty much possible with FPGA's from all vendors it just depend on quantity. MAX2-570 cost 3.50, well it's not called FPGA by altera, but I would say its small flash FPGA. From lattice I dont have pricing that would allow sub 6 USD designs, for Xilinx it sure would be possible, but maybe in really huge volumes only. in small-mid range volumes cheapest xilinx FPGA based design would have BOM cost >= 8 USD AnttiArticle: 128676
Xesium wrote: > Hi everybody, > It's been a while I'm struggling with ML310 board to have my design > loaded from compact flash to the Virtex II-pro FPGA on the board. I'm > generating system.ace file using iMPACT and program the compact flash > using a card reader. In my design I have a Microblaze with an OPB > timer, OPB SysAce controller and OPB uart-lite, I have some more > controllers connected to OPB which I think should not matter in the > flow of my design. In my software application I set the timer, write > something to the STD-OUT which is RS232 and after executing some code > I read the value of the timer again to know how many cycles it took > for that piece of code. Anyway my problem is when I load the design to > the compact flash, when I power on the device (or when I reset > system_ace) sysAce Status LED on the board blinks several times and > then all the LEDs including SysAce Status LED go green which to me > means that it loaded the design to the FPGA. However the problem is > the system seemingly goes to freeze mode. It doesn't write anything to > hyperterminal so that I could know if it is working or not. As well no > matter how much I keep SysAce button pressed it doesn't reset the > sysace any more. As well I can't get connected to the board for debug > using XMD through Parallel IV cable. So in fact I can't do anything > except to shut down the board. I have no clue what the problem can be. > I also tried using the bitstream already on the Xilinx ML310 Compact > Flash card. I put my design in to folder cf7 but the same things > happen when I want to load that design. > > Do you have any clue what the problem can be? I'd appreciate it if you > could point me to the solution or can introduce a tutorial or article > which in fact shows how exactly configuring through flash can be done. > I already went through several articles but still haven't been able to > get it work. > > I'd appreciate your comments and help beforehand, > > Amir Hi Amir, I have never had much luck generating ace files with impact, especially if you want to load program data for a microblaze or some such. The most reliable way I have found is to run the genace.tcl script from within an XPS/EDK shell. The syntax goes something like this: xmd -tcl genace.tcl -jprog -hw <name of bit file.bit> -board ml310 - ace <name of ace file.ace> There are other options to load program or data sections into external ram if needs be. You can find more info in the Emebedded System Tools Reference Manual www.xilinx.com/ise/embedded/est_rm.pdf If you just put the ace file it generates on a CF card by itself, the systemAce should load it no problems Good luck, DaveArticle: 128677
Hello, I want to set up design environment for my new Spartan-3E FPGA starter kit. I have downloaded ISE WebPack 9.2 and the service pack 9.2i SP4. To my dismay, when I want to point to my target device at the start or later(Set Properties for project), the Family drop-down, doesnot show of all the things, Spartan-3E. These options are available: Some Coolrunners, some CPLD's, Spartan 3A DSP and Spartan 3A and 3AN. I tried with Spartan-3A DSP and FPGA, but after bitstream generation, when I want to flash the design, there is some error, which is obviously because of wrong target device. Did I do something wrong. Can anyone, please lead me to a good 'how to' about this problem and also to start and set up my environment. Where can I get it to point it to synthesise for Spartan-3E? Do I have to use a previous version like 8.2 from the DVD, that came with the kit? It took a whole night to install Webpack 9.2 from internet. And I suppose ISE 9.2 supports 3E, atleast it mentions that it supports, but where? Please enlighten me. Thanks. PallaviArticle: 128678
pallavi wrote: > Hello, > I want to set up design environment for my new Spartan-3E FPGA starter > kit. > I have downloaded ISE WebPack 9.2 and the service pack 9.2i SP4. > To my dismay, when I want to point to my target device at the start or > later(Set Properties for project), the Family drop-down, doesnot show > of all the things, Spartan-3E. > I don't know what's wrong with your setup, but I'm using ISE WebPack 9.2.04i, and it shows the Spartan-3E devices.Article: 128679
Hello All, I am using the UNIFORM procedure in VHDL to generate random numbers. UNIFORM generates random numbers in the range 0.1 to 0.99999. I wish to generate random signed and unsigned numbers of variable widths(integer range). I would like to get some ideas on how I should scale this data? Right now, when i convert the real output from real to integer to signed, it just gives me an output of wither 0 or 1 . Your comments would be appreciated Thank youArticle: 128680
On Feb 3, 8:43 am, FPGA <FPGA.unkn...@gmail.com> wrote: > Hello All, > > I am using the UNIFORM procedure in VHDL to generate random numbers. > UNIFORM generates random numbers in the range 0.1 to 0.99999. I wish > to generate random signed and unsigned numbers of variable > widths(integer range). I would like to get some ideas on how I should > scale this data? Right now, when i convert the real output from real > to integer to signed, it just gives me an output of wither 0 or 1 . > Your comments would be appreciated > > Thank you Try multiplying it by a scaling factor before you convert it to integer.Article: 128681
On Feb 3, 8:11=A0am, Chris Maryan <kmar...@gmail.com> wrote: > On Feb 3, 8:43 am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > Hello All, > > > I am using the UNIFORM procedure in VHDL to generate random numbers. > > UNIFORM generates random numbers in the range 0.1 to 0.99999. I wish > > to generate random signed and unsigned numbers of variable > > widths(integer range). I would like to get some ideas on how I should > > scale this data? Right now, when i convert the real output from real > > to integer to signed, it just gives me an output of wither 0 or 1 . > > Your comments would be appreciated > > > Thank you > > Try multiplying it by a scaling factor before you convert it to > integer. Let the real random number you generated be "my_random_number". Let the random integer (my_random_integer) you want to generate be in the range "my_range_low" to "my_range_high". Then after using UNIFORM on "my_random_number", you would do my_random_integer <=3D my_range_low + my_random_number*(my_range_high - my_range_low) - Sudheendra KadriArticle: 128682
Antti wrote: > no, fusion is more expensive. > the cheapest Actel is A3P060 (A3P030 think is still not in full > production available) > 060 is very small, so in order to achive the full functions needed > some functions > are moved from FPGA to small flash MCU, that gives best price for the > functionality. > when trying to implement SLOW functions that are easy for sub 1 USD > MCU in the > FPGA the FPGA add-on price (device upgrade penalty) is more than 1 USD Yes, and what you can get in the low-end uC is advancing all the time. Fast SPI is common, so you can get a reasonable bandwidth into the FPGA and if you do not need Xtal precision, many uC now have CAL osc inbuilt -jgArticle: 128683
Hi, i need to know is it possible to readback and verify the loaded configuration in the FPGA after the GSR is deasserted and the FPGA is up and running with the loaded configuration? I am suspecting that due to power requirement of my application, the FPGA loses its configuration when the current demand increases ( HDD is connected to the FPGA board, when the FPGA talks to the HDD through SATA controller, the current goes up from .8 Amp to 1.7 Amps)and the FPGA stops working in the expected manner. Any ideas......... FarhanArticle: 128684
Farhan, First question: whose FPGA? Not every manufacturer supports readback. Xilinx FPGAs may be verified while operating, easiest being through the JTAG cable. If any of the power supplies droop sufficiently to trigger the power on reset, then the device will clean out (erase its configuration memory, and re-load itself). Such a case it pretty easy to see, by watching the power supply voltages with an oscilloscope, and also looking at the configuration interface Done, CCLK, etc.). AustinArticle: 128685
maverick wrote: > Hi, > i need to know is it possible to readback and verify the loaded > configuration in the FPGA after the GSR is deasserted and the FPGA is > up and running with the loaded configuration? I am suspecting that due > to power requirement of my application, the FPGA loses its > configuration when the current demand increases ( HDD is connected to > the FPGA board, when the FPGA talks to the HDD through SATA > controller, the current goes up from .8 Amp to 1.7 Amps)and the FPGA > stops working in the expected manner. > > Any ideas......... What do the supply voltage do? Does they remain in spec at all times? Is there any noise on them? What about the voltages on the IO pins, do they look correct? If you really think the fpga is getting corrupted or reset somehow, maybe you could use one pin to blink an LED or something and see if it ever acts strange. -JeffArticle: 128686
You mention that there is a problem when the current demand increases. Could it be that you don't have enough bulk capacitance to supply the instaneous current demand, thus your supplies dip. "maverick" <sheikh.m.farhan@gmail.com> wrote in message news:663f35a7-16a9-44ff-82b8-7adc8a6027f0@q21g2000hsa.googlegroups.com... > Hi, > i need to know is it possible to readback and verify the loaded > configuration in the FPGA after the GSR is deasserted and the FPGA is > up and running with the loaded configuration? I am suspecting that due > to power requirement of my application, the FPGA loses its > configuration when the current demand increases ( HDD is connected to > the FPGA board, when the FPGA talks to the HDD through SATA > controller, the current goes up from .8 Amp to 1.7 Amps)and the FPGA > stops working in the expected manner. > > Any ideas......... > > Farhan > >Article: 128687
On Feb 1, 11:12 pm, mk <kal*@dspia.*comdelete> wrote: > On Fri, 1 Feb 2008 09:13:38 -0800 (PST), emeb <ebromba...@gmail.com> > wrote: > > > > >On Feb 1, 3:13 am, mh <moazzamhuss...@gmail.com> wrote: > > >> Eric, > >> Have you seen Gnat tool ? > >> It is a powerful tool for communicating with FPGA through JTAG, > >> consisting of a VHDL core and TCL scripts to establish the > >> communication. > > >> Hope this helps, > >> /MH > > >Gnat looks like a very useful suite of tools. Unfortunately, the > >article (http://www.xilinx.com/publications/xcellonline/xcell_53/ > >xc_jtag53.htm) was written in 2005, and the URLs to the actual > >applications & libraries are all dead (the company that was hosting > >them has deleted them - searching the website turns up nothing). > > >Nice idea though. Anyone know if the project has been moved somewhere > >else? > > >EB > > There seems to be a copy here:http://www.xess.com/appnotes/gnat_xsa_3s1000.html All, I myself was confronted with such a situation and I asked this question on this forum, and was contacted by S3 group who later sent me the tool. I used it and found it an excellent tool. HTH /MHArticle: 128688
Hi, Our company is looking to buy some Linux servers for design implementations of Virtex5. So I was wondering if there is any optimum configuration that I can use to decrease my run time of the designs. -- GoliArticle: 128689
Hello, I have a question about the OFFSET In constraint. To my mind, OFFSET In is the same thing that the set-up time. But what about the hold time ? If I want to have a bigger hold time, I need to decrease my OFFSET In constraint ?? Or the only thing I can do is playing with the clock skew or data path delay ? Tk.Article: 128690
On Feb 4, 4:50 am, LilacSkin <lpaul...@iseb.fr> wrote: > Hello, > > I have a question about the OFFSET In constraint. > > To my mind, OFFSET In is the same thing that the set-up time. > But what about the hold time ? > > If I want to have a bigger hold time, I need to decrease my OFFSET In > constraint ?? > > Or the only thing I can do is playing with the clock skew or data path > delay ? > > Tk. For full details about the OFFSET constraint, read the constraint guide. It is in your ISE directory: $Xilinx\doc\usenglish\books\docs \cgd. If you want to specify hold time, you will use: OFFSET = IN <setup time> VALID <data valid window> BEFORE <clock>; where the hold time is the data valid window - the setup time. For example: TIMEGRP TNM_CTRL_INPUTS OFFSET = IN 3ns VALID 3ns BEFORE fpga_0_CLK; Specifies 3ns setup and 0 hold. TIMEGRP TNM_CTRL_INPUTS OFFSET = IN 3ns VALID 4ns BEFORE fpga_0_CLK; Specifies 3ns setup and 1ns hold. Regards, John McCaskill www.FasterTechnology.comArticle: 128691
Andreas Ehliar wrote: > On 2008-01-26, mmihai <iiahim@yahoo.com> wrote: >> On Jan 25, 12:24 am, taco <trala...@joepie.nl> wrote: >> >>> Right now I'm running an opencore 8051 which works fine and can be >>> programmed in C, but for the project I'm doing it could be that this >>> runs too slow and cannot handle to dataflow entering a FIFO. microblaze >>> would certainly solve it unless I have to add hardware. >> >> What is the complexity of your code? >> >> If you want to minimize the code to fit inside block RAMs the 8051 >> might not be your best choice. >> You can find some comparison data on my proc4 web page: >> http://www.delajii.net/proc4 > > I took a quick look at your webpage [1] and have a few questions: > > Do you have a C-compiler for your processor? (You only say that it is > programmable in a high-level language on your webpage.) Yeah, same question. I think this is not the case and if it's not a standard high level language, moving to a different processor is not very easy. > > Do you know if commercial compilers for Z80 and 8051 will produce better > results than sdcc? The answer is yes. The Keil compiler produces better optimized code for 8051. > > I also note that the 8051 results were done with 6 clocks per machine > cycle. AFAIK there are much faster 8051 cores available. Mmm. to get the graphs in some better direction? TacoArticle: 128692
> I myself was confronted with such a situation and I asked this > question on this forum, and was contacted by S3 group who later sent > me the tool. I used it and found it an excellent tool. > HTH Seems the unmodified tool is still missing on the S3 site: http://www.s3group.com/system_ic/gnat/download_gnat/ Could you upload it somewhere?Article: 128693
Hi all,
Are there any way to force some generate programming file from .ucf ?
1.
Generate Programming File
-> General Options
-> Create Binary Configuration File -> checked
2.
Generate Programming File
-> Configuration Options
-> Unused IOB Pins -> Float
OK we can do this in the ISE project manager but it is possible to do
the same from .ucf ?
Regards,
Larry
http://www.amontec.com
USB Chameleon key on 01-MARCH-2008, for a new reconfigurable logic
story.
Article: 128694>Hello All, > >I am using the UNIFORM procedure in VHDL to generate random numbers. >UNIFORM generates random numbers in the range 0.1 to 0.99999. I wish >to generate random signed and unsigned numbers of variable >widths(integer range). I would like to get some ideas on how I should >scale this data? Right now, when i convert the real output from real >to integer to signed, it just gives me an output of wither 0 or 1 . >Your comments would be appreciated > >Thank you > Actually it returns reals in the range 0.0 to 1.0 (exclusive), that is it can return 0.0, but not 1.0. As a previous reply states, you need to multiply the returned value by a (real type) scaling factor before conversion to unsigned, and remember to offset if converting to signed.Article: 128695
On Feb 2, 5:23=A0pm, mk <kal*@dspia.*comdelete> wrote: > On Sat, 2 Feb 2008 21:19:28 +0100, "Xin Xiao" <x...@x.com> wrote: > > >I have synthesized and implemented my design, and I was going to simulate= > >post-route using ModelSim. The problem is that all internal signals have > >been renamed, and I can't match each signal with the signal name from my > >vhdl code. How can I show the "behavioral" signal names during post-route= > >simulation? Or where is the correspondence between vhdl signal names and > >post-route signal names? > > >Thanks! > > In general there is none but there are some cases which might be > helpful. Usually module ports are preserved so you can put the names > you're interested as module outputs and still have them available. > They don't even have to be at the top level (usually). The other case > is registers are usually quite predictively changed ie a register > foo[7:0] almost always gets named foo_reg_7, foo_reg_6 etc. You can > use this to access your signals. > One question is that why you need to see your internal signals in gate > level. Even if you feel the need to do gate-level back-annotated sims, > surely you don't need to debug them there unless of course you're > trying to catch an apparent incorrectly generated hardware problem but > that's very rare and the problem is almost always somewhere else. > Debug your circuits in RTL fully and make sure you meet timing in P&R > then you don't have to debug gate-level. Depending on your synthesis tool and place and route tool, there are attributes available such as 'preserve_signal' and 'preserve_driver' that can be used on those special signals you would like to keep. That is, it prevents them from being renamed or optimized out. If there are only a few important signals you need to keep, then this is a good alternative.Article: 128696
Hello all, For all those who know that the Xilinx FPGA Editor exists, and maybe that it's good for something, but are reluctant to try it out (for obvious reasons): I've made a short video guide, which takes the viewer around, and also demonstrates some very useful things you can do with it. Overall, it's some 20 minutes of video (in three parts). Link: http://billauer.co.il/xilinx-fpga-editor-video-tutorial-guide.html It's maybe not easy to follow at first glance, but since all operations are shown explicitly on screen capture, using the "pause" button, and trying it out yourself, should be pretty straightforward. The tutorial goes through everything from opening an NCD file for editing, viewing the design down to its small details, making some changes, and finally saving the altered design for creation of a bitfile. It also shows how to create probes (or: how to touch any signal within your FPGA design with your oscilloscope probe in a minute). Hope it turns out useful out there. EliArticle: 128697
Hi I have a simple question, whats the best way of designing a lookup table which is 16 bit wide in VHDL and for sythesis. It receives 4 input bits and depending of the values 1 bit will be selected for the output. As I have a 32 bit architecture, this kind of lookup table should have 32 instances in parallel. So I wonder what is the best option to implement this? I also need to configure these lookup tables before using them. Is the following approach feasable? I have one register that is 16 bits wide and which holds the value of my lookup table. Now I use 32 Muxes and each receives the 16 bits that are stored in the lookup register. Each mux has its own 4-input selection signal, which consists of the corresponing bits of the registers, and outputs the the corresponding bit. So I would need quite a lot of muxes, it is maybe better to have 32 16-bit lookup tables in parallel and read there directly the value out? Thanks for helpful tips!Article: 128698
Xesium wrote: > Hi everybody, > I have written a very simple code for microblaze on Virtex II-Pro > (XC2VP30 on ML310 board) which basically writes something to STD-OUT > (through uart). When I load the design to the FPGA through parallel > cable IV everything works perfectly which gives me the idea that > basically there is nothing wrong with the design in general and the > code. I've been trying to load the design through compact flash for a > few weeks now but I haven't still been able. I'm using EDK 8.2.02 and > ISE 8.2.03. If I generate the .ace file using EDK when I switch on the > board the sysAce Error red LED is turned on meaning that the design is > not loaded appropriately. However when I generate .ace file using > iMPACT from ISE then it sounds like the design is loaded because the > green SysAce Status LED is turned on but it writes nothing to the > hyperterminal through which I'm getting connected to UART on the > board. > > Do you have any clue what the problem is? > > I appreciate any help beforehand, It sounds like you have a working design since you can download through the PC4 cable and have it run. I am not an EDK expert, but here are my thoughts. The SystemACE error LED is likely being lit as you have not changed your JTAG chain description to remove the System ACE from the chain. You need System ACE in the chain description when downloading from a cable, but when the System ACE is the master and programming the devices it isn't part of the chain description since it is the master. In the case of iMPACT generating a valid ACE file but not a working design, this is probably due to the software not being initialized in the BlockRAMs. You should have an ELF file that was generated for your program that was marked to be the one that is initialized to the BlockRAMs and a BMM file that defines the memory map to internal/external RAMs. When you do an "Update Bitstream" these should be combined with the placed/routed BIT file to create a download.bit file. This is the one that you should be using with iMPACT to generate the ACE file. I hope that this helps. BTW, 8.2i is fairly old you might also want to consider moving to 9.2i Ed McGettigan -- Xilinx Inc.Article: 128699
Thanks so much Dave. I actually tried this command: $ xmd -tcl genace.tcl -jprog -hw implementation/download.bit -board ml310 -target mdm -elf timer_test/executable.elf -ace system.ace My software code is supposed to write something to hyperterminal through RS232 port and I have in fact populated the local BRAMs with the data and instructions of my software code and download.bit should contain that information (I tried commands with and without -elf timer_test/executable.elf). When I download the bitstream through my computer everything looks OK and my code writes whatever it is supposed to write to hyperterminal. The structure that I have on my CF card is as follows: The CF for ML310 comes already loaded with some programs, when I turn on the device the ML310 demo on the CF is loaded and writes something on hyperterminal and gives me some options. There is one folder in the path: <CF-Drive>/xilinx/cf7 where I can copy my ace file to. If I want to execute and load my design when Xilinx demo is loaded I have to press 7 so that it loads my design (which is inside folder cf7). So whenever I hit 7 it says that it is loading new config 7, the sysAce Status on the board blinks twice (or three times) and then all the LEDs go green giving me the idea that now it's working. However if my code is actually loaded then it should write something to the hyperterminal but that doesn't happen! Firstly I don't know why it is so, secondly I know no more convenient way to make sure that my design is actually loaded and working (the only way I found convenient is to write something to the output)! So I really appreciate any help or comment in this regards, Amir PS. By the way all the problems that I had like the system being frozen is solved now. I actually went back and designed everything from scratch and now that part is solved. I also made sure that ISE and EDK that I'm using (8.2) is updated with the latest service packs. On Feb 3, 1:48 am, David <simianfe...@gmail.com> wrote: > Xesium wrote: > > Hi everybody, > > It's been a while I'm struggling with ML310 board to have my design > > loaded from compact flash to the Virtex II-pro FPGA on the board. I'm > > generating system.ace file using iMPACT and program the compact flash > > using a card reader. In my design I have a Microblaze with an OPB > > timer, OPB SysAce controller and OPB uart-lite, I have some more > > controllers connected to OPB which I think should not matter in the > > flow of my design. In my software application I set the timer, write > > something to the STD-OUT which is RS232 and after executing some code > > I read the value of the timer again to know how many cycles it took > > for that piece of code. Anyway my problem is when I load the design to > > the compact flash, when I power on the device (or when I reset > > system_ace) sysAce Status LED on the board blinks several times and > > then all the LEDs including SysAce Status LED go green which to me > > means that it loaded the design to the FPGA. However the problem is > > the system seemingly goes to freeze mode. It doesn't write anything to > > hyperterminal so that I could know if it is working or not. As well no > > matter how much I keep SysAce button pressed it doesn't reset the > > sysace any more. As well I can't get connected to the board for debug > > using XMD through Parallel IV cable. So in fact I can't do anything > > except to shut down the board. I have no clue what the problem can be. > > I also tried using the bitstream already on the Xilinx ML310 Compact > > Flash card. I put my design in to folder cf7 but the same things > > happen when I want to load that design. > > > Do you have any clue what the problem can be? I'd appreciate it if you > > could point me to the solution or can introduce a tutorial or article > > which in fact shows how exactly configuring through flash can be done. > > I already went through several articles but still haven't been able to > > get it work. > > > I'd appreciate your comments and help beforehand, > > > Amir > > Hi Amir, > > I have never had much luck generating ace files with impact, > especially if you want to load program data for a microblaze or some > such. The most reliable way I have found is to run the genace.tcl > script from within an XPS/EDK shell. The syntax goes something like > this: > > xmd -tcl genace.tcl -jprog -hw <name of bit file.bit> -board ml310 - > ace <name of ace file.ace> > > There are other options to load program or data sections into external > ram if needs be. You can find more info in the Emebedded System Tools > Reference Manual > > www.xilinx.com/ise/embedded/est_rm.pdf > > If you just put the ace file it generates on a CF card by itself, the > systemAce should load it no problems > > Good luck, > > Dave
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