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Hello, I'm using the High-Performance DDR2 Controller in my design to interface with two Micron MT47H64M16 - 8 Meg x 16 x 8 banks. These DDR2 devices have the control lines connected together so I can control both devices for 32-data. I'm reading over the DDR and DDR2 SDRAM High Performance Controller User Guide page 3-18 and my question is about the input "local_address". In my design the bit width for local_address is 27-bits. Can someone tell me how the mem_row_address, mem_col_address, and mem_bank_address are broken down from the 27 bits? Thanks, joeArticle: 136301
On Nov 10, 8:00=A0am, "jjlind...@hotmail.com" <jjlind...@hotmail.com> wrote: > Hello, I'm using the High-Performance DDR2 Controller in my design to > interface with two Micron MT47H64M16 - 8 Meg x 16 x 8 banks. These > DDR2 devices have the control lines connected together so I can > control both devices for 32-data. I'm reading over the DDR and DDR2 > SDRAM High Performance Controller User Guide page 3-18 and my question > is about the input "local_address". In my design the bit width for > local_address is 27-bits. Can =A0someone tell me how the > mem_row_address, mem_col_address, and mem_bank_address are broken down > from the 27 bits? > > Thanks, > joe I should add that I'm trying to follow the example on page 3-17 when writing to the memory. So the local size input is set to "2" and local_be set to "3". joeArticle: 136302
On Nov 10, 12:55 am, "H. Peter Anvin" <h...@zytor.com> wrote: > It would still be nice to have more chips with combination > microcontroller and small FPGA at the low end, as that is often a useful > mix as opposed to having to have a much bigger FPGA. Aiming this at the > high-end CPLD markets (with features such as onboard flash, 5V > tolerance, etc.) would be especially nice. My feeling is that when talking about low cost FPGA's, it's not the logic fabric required to implement a decent microcontroller-class soft core that's the problem, it's the ram to store the program that is mostly missing and thus pushes you either into a larger FPGA than logic demands require, or into using an external memory. And flash cells would be nice too, but if doing that might as well include storage for the FPGA bit file too. Otherwise you can just append the program code in a serial config flash and load that into ram to execute from. Or you could if the ram problem were solved...Article: 136303
Jonathan Bromley wrote: > I'm just coming to the end of a session working > alongside a very, very smart young designer whose > only noticeable fault is the total lack of useful > commentary in his code. Initially I thought that > was just bull-headed idiocy on his part, but now > I recognise that his thoughts are probably a lot > less fleeting than mine... so he doesn't (yet) > need comments for himself; I'll check back in 6 months to see how this design rule is working out for him ;) -- Mike TreselerArticle: 136304
Max wrote: > Hi there, > > I have a very stupid question. I was wondering how much silicon the > actual FPGA logic (that is the slices and the BRAM ressources) are > occuping on the physical chip. So can I expect that the whole physical > chip is dedicated to these ressources or are there other components on > the chip that take some space like flash memory for instance, or some > other (external control) logic? > Historically, the bulk of the chip was the interconnects & their configurable switch arrays. I'm not sure if this is still true of the latest designs, but I expect so.Article: 136305
On Nov 10, 8:02=A0am, "jjlind...@hotmail.com" <jjlind...@hotmail.com> wrote: > On Nov 10, 8:00=A0am, "jjlind...@hotmail.com" <jjlind...@hotmail.com> > wrote: > > > Hello, I'm using the High-Performance DDR2 Controller in my design to > > interface with two Micron MT47H64M16 - 8 Meg x 16 x 8 banks. These > > DDR2 devices have the control lines connected together so I can > > control both devices for 32-data. I'm reading over the DDR and DDR2 > > SDRAM High Performance Controller User Guide page 3-18 and my question > > is about the input "local_address". In my design the bit width for > > local_address is 27-bits. Can =A0someone tell me how the > > mem_row_address, mem_col_address, and mem_bank_address are broken down > > from the 27 bits? > > > Thanks, > > joe > > I should add that I'm trying to follow the example on page 3-17 when > writing to the memory. So the local size input is set to "2" and > local_be set to "3". > > joe Hello again, I've been reading over the data sheet for the DDR2 memory and I made a mistake, the bit width for the local_address input on the DDR2 Megacore Controller should be 25-bits, not 27 bits. The DDR2 has 13 bits on the row, 3 bits on the bank, and 10 bits on the columns. Sorry about that error. Hopefully someone can help be point out where the row, column, and bank is located in those 25 bits of the local_address. Thanks, joeArticle: 136306
On Nov 10, 10:30=A0am, "jjlind...@hotmail.com" <jjlind...@hotmail.com> wrote: > On Nov 10, 8:02=A0am, "jjlind...@hotmail.com" <jjlind...@hotmail.com> > wrote: > > > > > On Nov 10, 8:00=A0am, "jjlind...@hotmail.com" <jjlind...@hotmail.com> > > wrote: > > > > Hello, I'm using the High-Performance DDR2 Controller in my design to > > > interface with two Micron MT47H64M16 - 8 Meg x 16 x 8 banks. These > > > DDR2 devices have the control lines connected together so I can > > > control both devices for 32-data. I'm reading over the DDR and DDR2 > > > SDRAM High Performance Controller User Guide page 3-18 and my questio= n > > > is about the input "local_address". In my design the bit width for > > > local_address is 27-bits. Can =A0someone tell me how the > > > mem_row_address, mem_col_address, and mem_bank_address are broken dow= n > > > from the 27 bits? > > > > Thanks, > > > joe > > > I should add that I'm trying to follow the example on page 3-17 when > > writing to the memory. So the local size input is set to "2" and > > local_be set to "3". > > > joe > > Hello again, I've been reading over the data sheet for the DDR2 memory > and I made a mistake, the bit width for the local_address input on the > DDR2 Megacore Controller should be 25-bits, not 27 bits. The DDR2 has > 13 bits on the row, 3 bits on the bank, and 10 bits on the columns. > Sorry about that error. Hopefully someone can help be point out where > the row, column, and bank is located in those 25 bits of the > local_address. > > Thanks, > joe Ah, must be Monday, I'm making too may errors :) I should have said 26 bits, get my numbers straight, sorry for the confusion. joeArticle: 136307
ikki wrote:
> I would like to ask you about the coding for it. I do understand the
> concept of it. But, how do I shift it right so that every clock cycle the
> LSB will be transferred out ?
Use a <= assignment from the reg bit to the out port.
> here are my codes ,. .. do you see any errrors about this ? ...how can i
> edit from here...
Reread this thread.
Several solutions to your problem are described.
If you want to debug your own code,
get a simulator and do it yourself.
-- Mike Treseler
Article: 136308<jjlindula@hotmail.com> wrote in message news:8a9329ee-81bc-462e-9ace- > Hello again, I've been reading over the data sheet for the DDR2 memory > and I made a mistake, the bit width for the local_address input on the > DDR2 Megacore Controller should be 25-bits, not 27 bits. The DDR2 has > 13 bits on the row, 3 bits on the bank, and 10 bits on the columns. > Sorry about that error. Hopefully someone can help be point out where > the row, column, and bank is located in those 25 bits of the > local_address. One easy way to figure this out on your own is to start up a simulation and simply walk a 1 across the local address side doing either a read or write operation and then seeing which address bits get twiddled by the controller while it performs that operation. Another method would involve inspecting the controller's source code but that code is rather opaque and once you convince yourself you know what's going on, you still probably won't be confident enough without first verifying it in simulation anyway as I just mentioned. Kevin JenningsArticle: 136309
>>explore wrote: >>> Thanks for your response. Unfortunately the board was not designed >>> by us. This is an AVNET PCIe board that we happened to purchase a >>> while ago. We hadn't put in the XAUI core until recently. Now we are >>> forced to use the same GTP locations specified in the AVNET user >>> guide. We were suggested by Xilinx support that we can use the >>> flexibility of channel bonding available with rocketio's to try and >>> make timing and this is the reason we are still hopeful of finding a >>> solution to it. They also told us that some people were successful in >>> making changes to the channel bonding in AURORA cores and the design >>> to meet timing when they had a similar problem. As I mentioned >>> earlier, the design meets timing when the tiles have channel bonding >>> levels of 5,4,1,0 with 2 pipeline stages for rxchanbond signals, but I >>> do not get to see it work in simulation. Would like your suggestion/ >>> inputs on this. >>> >>> Thanks for your time once again. >>> >>> --Chethan >>> >>> >>> On Jun 16, 7:31 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: >>>> explore wrote: >>>>> I am using a XAUI core in my design for a PCIe board with a Xilinx >>>>> Virtex - 5 LX110t FPGA. The board specifications require the GTP >dual >>>>> tiles of XAUI to be constrained to locations X0Y0 and X0Y7 which are >>>>> far from each other on the FPGA. Due to this, the design does not >meet >>>>> timing. The user-guide for the rocketio transceivers suggests >>>>> modification of channel bonding attributes of the GTP Dual tiles to >>>>> meet timing. To try this out, the default channel bonding level for >>>>> the 4 GTP tiles (2 GTP duals) was changed to 3,2,1,0 with 3 as the >>>>> master tile. This design works fine in simulation, but does not meet >>>>> timing. The timing error as seen on timing analyzer was due to the >>>>> rxchanbondo signal. >>>>> The channel bond level was further changed to 5,4,1,0 with 5 as the >>>>> master. Two pipeline stages were added for the rxchanbondo signal >>>>> (between the tiles 4 and 1). This design meets timing, but does not >>>>> work in simulation. All these changes were made to the >>>>> rocketio_wrapper.v file in the XAUI core generated using coregen. >>>>> I feel that the wiring between the tiles in the rocketio_wrapper.v >>>>> file needs to be modified to hook-up all the signals that may have >>>>> been disturbed due to the addition of the two pipeline stages. >>>>> Unfortunately I do not have a lot of experience working with >rocketio >>>>> transceivers and their channel bonding attributes which puts me in a >>>>> state of bother while analyzing what signals need to be modified/ >>>>> reassigned/patched between the gtp tiles. >>>>> I would appreciate any suggestions from anybody who has had >experience >>>>> working with XAUI, rocketio's and their channel bonding attributes. >>>>> Thanks for your help in advance >>>> Why are the GTP_DUAL sites constrained to X0Y0 and X0Y7, these are >the >>>> worst possible locations to choose from. If the board hasn't gone >>>> through layout yet, can you change these to be adjacent locations? >>>> >>>> Ed McGettigan >>>> -- >>>> Xilinx Inc. >>> >> >>Ok, I understand now. I hope that when you take the design forward to >>your own platform that you clean this up and don't follow this design. >> >>I was not familiar with this particular board, but I was able to >>determine that you are using the Avnet AES-XLX-V5LXT-PCIE110-G board and > >>after getting the schematics it does show that the XAUI/CX4 interface >>that you are trying to use is split across the device using X0Y0 and >X0Y7. >> >>There are a couple of issues with this board design, but I will address >>your channel bond timing issue first. >> >>You can make this timing work, but you have to insert additional >>registers in the RXCHBONDO[2:0] to RXCHBONDI[2:0] path. These ports use > >>the faster 10-bit RXUSRCLK clock that will be running at at 312.5MHz in >>your application. My guess is that you will need at least 2 register >>stages to get across the device at this frequency and you made need >>three as the clock-to-out on RXCHBONDO and the setup into RXCHBONDI are >>long with respect to a 312.5 MHz clock. >> >>You should place absolute placement LOC attributes on these registers to > >>ensure that MAP doesn't pack the stages into the same slice and you get >>the spread that you need. After you have the timing working you will >>then need to set the correct CHAN_BOND_LEVEL value for each lane based >>on the number of stages that you used. This is describe in the GTP User > >>Guide (UG196) Configurable Channel Bonding section. >> >>In addition to channel bonding issue you also have two other issues with > >>this board that impact your XAUI design. >> >>1) You need to use two REFCLK sources, one for each GTP_DUAL. The board > >>supports it, but you will likely need to update the XAUI source to add >>the second set of inputs to one of the GTP_DUALs. >> >>2) The P/N nets are swapped for some of the pairs. The schematic >>indicates that you need to set the TXPOLARITY0 and RXPOLARITY0 on X0Y7 >>and TXPOLARITY1 on X0Y0 to 1 (default is 0). >> >>Good luck. >> >>Ed McGettigan >>-- >>Xilinx Inc. >> > >Does this help resolve issues? Do you see any other issues with this >board? > > > > > Hello, I also have a problem with this evalboard and the XAUI core. I added three registers to the chanbond path and changed the chanbond levels as described. The RX align Flag is set, so this seems to work. My PC (Windows XP, Myricom 10 GbE NIC) tells me that the connection is established, but also that the connection speed is only 1,4 GHz. I generated the XAUI Core without MDIO interface, because of the size. The status vector output shows an RX Fault, TX seems to be ok. I can't find any description of what could be the reason for this fault. What can I do to debug the core? Thanks PhilipArticle: 136310
Does it support verilog1995 VCD? Or Extended VCD format? -- Amal On Nov 7, 10:50=A0am, timinganalyzer <timinganaly...@gmail.com> wrote: > Hi All, > > A newly added feature of the TimingAnalyzer is the ability to > read .vcd files. =A0These files can be generated by logic simulators or > tools like Xilinx chipscope, or test equipment like logic analyzers. > So, =A0you can easily make annotated timing diagrams from simulation or > test equipment outputs. > > Would it be possible to email any .vcd files samples that you might > have, =A0that are not proprietary, =A0so I can test this feature with .vc= d > files from as many sources as possible? > > tiiminganaly...@gmail.com > supp...@timing-diagrams.com > > Thank you in advance, > Dan > > www.timing-diagrams.comArticle: 136311
On Nov 10, 11:10=A0am, "KJ" <kkjenni...@sbcglobal.net> wrote: > <jjlind...@hotmail.com> wrote in message news:8a9329ee-81bc-462e-9ace- > > Hello again, I've been reading over the data sheet for the DDR2 memory > > and I made a mistake, the bit width for the local_address input on the > > DDR2 Megacore Controller should be 25-bits, not 27 bits. The DDR2 has > > 13 bits on the row, 3 bits on the bank, and 10 bits on the columns. > > Sorry about that error. Hopefully someone can help be point out where > > the row, column, and bank is located in those 25 bits of the > > local_address. > > One easy way to figure this out on your own is to start up a simulation a= nd > simply walk a 1 across the local address side doing either a read or writ= e > operation and then seeing which address bits get twiddled by the controll= er > while it performs that operation. =A0Another method would involve inspect= ing > the controller's source code but that code is rather opaque and once you > convince yourself you know what's going on, you still probably won't be > confident enough without first verifying it in simulation anyway as I jus= t > mentioned. > > Kevin Jennings Hello, I found the answer at the end of the documentation, DDR and DDR2 SDRAM High Performance Controller User Guide page 3-40. Another question, when writing a block of data, do I fill up the rows first for each column or fill up each column of each row? What is the best addressing scheme? Thanks, joeArticle: 136312
On 11=D4=C210=C8=D5, =CF=C2=CE=E712=CA=B102=B7=D6, Andreas Ehliar <ehliar-n= os...@isy.liu.se> wrote: > On 2008-11-10, mynewlife...@yahoo.com.cn <mynewlife...@yahoo.com.cn> wrot= e: > > > In the report, route use 88.5% timing budget, how to make route use > > fewer timing budget. reset_n is an output of BUFG. > > If I have a synchronuos reset I usually solve this problem by adding a co= uple > of registers to the reset signal. This means that the reset signal will n= ot > have any immediate effect, but I don't really care if the chip will reset > itself in 3 nanoseconds or 15 nanoseconds. > > By the way, is your reset signal synchronuos with your clock signal or no= t? > If it isn't, you need to synchronize it with a couple of flip-flops regar= dless > of the above advice. > > /Andreas I am sure reset signal synchronuos with clock signal, and I also add a couple of registers.Article: 136313
On 11=D4=C210=C8=D5, =CF=C2=CE=E75=CA=B110=B7=D6, hal-use...@ip-64-139-1-69=
.sjc.megapath.net (Hal
Murray) wrote:
> Do you really have only one clock in your design?
>
> Do you understand metastability?
I know what is metastability, I have more than one clock in my design,
but the other clock is only for xilinx ip core like sgmii or xaui
core. The reset signal to reset ip core or logic is different.
>
> The usual approach is to treat an external reset as an asynchronous
> signal and synchronize it (pair of FFs) locally at each state machine.
Reset signal is an input of FPGA, I use a special module to treat this
external reset, reset_int had already synchronize with global clk,
then I use BUFG like this,
BUFG reset
( .I (reset_int),
.O(reset_n)
);
The reset_n is a very high fanout network. In other modules, reset_n
signal is used directly to reset logic, I think it is synchronous
design, reset_n is an output of BUFG, so I do not synchronize it
locally at each state machine. Dose it matter?
> It may take some extra logic if your design depends upon a chain
> of state machines coming out of reset together.
What does this mean?
Thank you for you replay.
Article: 136314On Nov 10, 5:24=A0pm, Amal <akhailt...@gmail.com> wrote: > Does it support verilog1995 VCD? =A0Or Extended VCD format? > > -- Amal > > On Nov 7, 10:50=A0am, timinganalyzer <timinganaly...@gmail.com> wrote: > > > Hi All, > > > A newly added feature of the TimingAnalyzer is the ability to > > read .vcd files. =A0These files can be generated by logic simulators or > > tools like Xilinx chipscope, or test equipment like logic analyzers. > > So, =A0you can easily make annotated timing diagrams from simulation or > > test equipment outputs. > > > Would it be possible to email any .vcd files samples that you might > > have, =A0that are not proprietary, =A0so I can test this feature with .= vcd > > files from as many sources as possible? > > > tiiminganaly...@gmail.com > > supp...@timing-diagrams.com > > > Thank you in advance, > > Dan > > >www.timing-diagrams.com Currently, just the vcd format, but I could add the extended vcd format if requested. Do you know what tools work with the extended format? I have also worked with a compressed file format which might of interest to some users working with large simulations. Thanks, DanArticle: 136315
On Nov 10, 6:08=A0pm, wallra <khamitkar.ravik...@gmail.com> wrote: > when i completed the edk base system builder wizard with EDK 8.2i > and connected spartan 3e starter kit and downloaded the bitstream with > Test_app_memory.c and .elf files > i didn't seen anything on my hyperterminal with all hardware kit and > wire attached > with baud rate of 9600 as standard one. > will any body suggest what would be the cause for this happen, > all suggestions arew valuable for me. no one can solve this simple problem of newbi like me who want to lean EDK and C programing of itsArticle: 136316
"Stonethrower" <digi_64-public[removethis]@yahoo.com> wrote in message news:gesvb8$67i$1@ss408.t-com.hr... >> but it costs 20 Dollars... So I am wondering if there are any other sites >> out there where I can learn this kind of stuff? > > Try this one on San Jose State University: > http://www.engr.sjsu.edu/crabill/ > ... > also try MIT's OpenCourseWare on FPGA: > http://ocw.mit.edu/ans7870/6/6.111/s04/NEWKIT/index.htm The main course page is http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-111Spring2004/CourseHome/index.htm. You'll find videos, PDFs, etc. Good luck.Article: 136317
>Reset signal is an input of FPGA, I use a special module to treat this >external reset, reset_int had already synchronize with global clk, >then I use BUFG like this, > BUFG reset > ( .I (reset_int), > .O(reset_n) > ); >The reset_n is a very high fanout network. In other modules, reset_n >signal is used directly to reset logic, I think it is synchronous >design, reset_n is an output of BUFG, so I do not synchronize it >locally at each state machine. Dose it matter? High fanout signals are "interesting". Routing takes a long time relative to how fast you can clock a well placed small design. It can easily take more than a clock period to get a signal across the chip. Check your documentation. My old copy of the library guide says BUFG is a global clock buffer. It won't help you to distribute anything but a clock. You may be able to make your design work by splitting your reset signal into several signals with different names, one for each region of the chip. You can add extra pipeline stages as necessary to meet timing. If you keep the number of pipeline stages in each branch the same, then all the local reset signals will get cleared at the same time. >> It may take some extra logic if your design depends upon a chain >> of state machines coming out of reset together. >What does this mean? >Thank you for you replay. If you don't keep the number of pipeline stages in each branch the same, then some sections (state machines) will come out of reset before others. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 136318
>I have a Xilinx ML555 and Linux as OS.
>The job assigned to me is linux programming for "Data transfer
>between CPU and FPGA over PCI bus".
>Someone already did the similar thing. Please help me.
>General flow is like this.
>(1) CPU sends data to FPGA
>(2) FPGA do computations
>(3) FPGA gives it back to CPU
How fast does that have to go? Are you going to crunch a lot of
data? Or crunch for a long time on a tiny bit of data?
Do you need a solid, high quality design, or just get
something to one once to finish your thesis?
There are 2 ways to get data to/from a PCI device.
You can load/store from an address that is setup to
point to the device. This is called PIO, Programmed I/O.
It's slow, but simple. This is find if you are doing something
like brute force searching DES - lots of computing, not much
I/O.
You can setup the device to read/write big chunks of data
to/from memory: DMA, Direct Memory Access. This is a lot
faster. You need this if you are doing video processing.
DMA is much more complicated, both for the driver and for
the FPGA.
If you are using DMA, the first thing you need to do is
allocate a big chunk of memory. You want contigious memory,
so you may have to allocate it early in the boot process
rather than waiting until you open the device and memory
has been fragmented.
DMA works in physical memory. User code works in virtual memory.
You need an ioctl to map the memory into user space and return
the virtual address and also the physical address so your
user program can setup the DMA control registers.
The general idea is something like:
open device, allocate memory, ...
Loop until done:
fill data into first half of memory block
setup DMA control registers and whatever
poke FPGA to start
wait until it finishes
grab data from second half of memory block
After you get that done, you can double buffer things.
For something like a network controller, the system
allocates a buffer when it needs it, copies the data
to/from the buffer and user space, and sets up
the DMA registers for you. That's another layer
of complication. You can debug the FPGA without it,
then make the driver do all the fancy stuff.
>What I want to ask is following.
>(1) This is the first time for Linux programming.
> Where can I get the sample codes or reference?
Sorry, I don't have any handy examples. Have you checked
the Xilinx web site?
>(2) I think that initially FPGA chip is not configured.
> So How to configure it? ( I mean that if I have a bitstream file
>for FPGA, How can I configure FPGA with it?)
You load it just like you load any other board. That's usually
with a gizmo that plugs into a USB port (or printer port) and the
other end plugs into JTAG or such on the board you want to program.
I haven't worked with that particular board. I assume it has a
flash chip, so you program the flash via JTAG, then power cycle
the machine. On power up, the FPGA will load itself from the flash.
After you get things debugged, you may be able to program the flash
from the FPGA.
>(3) If you have already done with similar job, plz give me an advice
>about how to proceed.
> I have to do it myself, so even a little advice is big help for
>me.
I would try hard to avoid doing the whole thing by myself.
It really helps to have somebody else to bounce ideas off.
The driver is only half the problem. You also need some code
in the FPGA. When debugging things, you have to figure out
if the problem is in your driver or in the FPGA code.
You need a copy of the PCI specs. A logic analyzer or scope
on the PCI bus may help a lot.
--
These are my opinions, not necessarily my employer's. I hate spam.
Article: 136319"timinganalyzer" <timinganalyzer@gmail.com> wrote in message news:bf961753-a564-4045-b12b-31d524986f31@a17g2000prm.googlegroups.com... On Nov 10, 5:24 pm, Amal <akhailt...@gmail.com> wrote: > Does it support verilog1995 VCD? Or Extended VCD format? > > -- Amal > > On Nov 7, 10:50 am, timinganalyzer <timinganaly...@gmail.com> wrote: > > > Hi All, > > > A newly added feature of the TimingAnalyzer is the ability to > > read .vcd files. These files can be generated by logic simulators or > > tools like Xilinx chipscope, or test equipment like logic analyzers. > > So, you can easily make annotated timing diagrams from simulation or > > test equipment outputs. > > > Would it be possible to email any .vcd files samples that you might > > have, that are not proprietary, so I can test this feature with .vcd > > files from as many sources as possible? > > > tiiminganaly...@gmail.com > > supp...@timing-diagrams.com > > > Thank you in advance, > > Dan > > >www.timing-diagrams.com > >Currently, just the vcd format, but I could add the extended vcd >format if requested. > >Do you know what tools work with the extended format? Modelsim is one of them. Hans www.ht-lab.com > I have also >worked with a compressed file format which might of interest to some >users working with large simulations. > >Thanks, DanArticle: 136320
On Nov 10, 8:28=A0pm, wallra <khamitkar.ravik...@gmail.com> wrote: > On Nov 10, 6:08=A0pm, wallra <khamitkar.ravik...@gmail.com> wrote: > > > when i completed the edk base system builder wizard with EDK 8.2i > > and connected spartan 3e starter kit and downloaded the bitstream with > > Test_app_memory.c and .elf files > > i didn't seen anything on my hyperterminal with all hardware kit and > > wire attached > > with baud rate of 9600 as standard one. > > will any body suggest what would be the cause for this happen, > > all suggestions arew valuable for me. > > no one can solve this simple problem of newbi like me who want to lean > EDK and C programing of its Are you sure that FPGA is configured? How about writing simple program with printf and debug it, if you enable it on your design.Article: 136321
On Nov 10, 3:45=A0pm, lomtiks...@gmail.com wrote: > Hi, > > I am facing an issue of accessing the registers of a peripheral > sitting on the DCR bus via PLBV46 to DCR Bridge and uBlaze. The uBlaze > is on the PLB bus. The bridge is a slave on PLB and a master on DCR. > Please see below for a snippet of the .mhs file. > > Since my peripheral has the C_DCR_BASEADDR =3D 0b0000000000, I assume it > is register 0 on the PLB2DCR bridge and I can simply access it by > looking at the base address of the PLB2DCR. For example, > write_adress (0x87000000, value1) > write_adress (0x87000004, value2) > Does it make sense? > > BEGIN plbv46_dcr_bridge > =A0PARAMETER INSTANCE =3D plbv46_dcr_bridge_0 > =A0PARAMETER HW_VER =3D 1.00.a > =A0PARAMETER C_BASEADDR =3D 0x87000000 > =A0PARAMETER C_HIGHADDR =3D 0x8700ffff > =A0BUS_INTERFACE SPLB =3D mb_plb > =A0BUS_INTERFACE MDCR =3D dcr_v29_0 > END > > BEGIN xps_tft > =A0PARAMETER INSTANCE =3D xps_tft_0 > =A0PARAMETER HW_VER =3D 1.00.a > =A0PARAMETER C_DCR_SPLB_SLAVE_IF =3D 0 > =A0PARAMETER C_TFT_INTERFACE =3D 0 > =A0PARAMETER C_DEFAULT_TFT_BASE_ADDR =3D 0x10800000 > =A0PARAMETER C_DCR_BASEADDR =3D 0b0000000000 > =A0PARAMETER C_DCR_HIGHADDR =3D 0b0000000011 > =A0BUS_INTERFACE MPLB =3D mb_plb > =A0BUS_INTERFACE SDCR =3D dcr_v29_0 > =A0PORT TFT_VSYNC =3D VGA_VSYNCH > =A0PORT TFT_HSYNC =3D VGA_HSYNCH > =A0PORT TFT_VGA_CLK =3D VGA_OUT_PIXEL_CLOCK > =A0PORT SYS_TFT_Clk =3D tft_clk > =A0PORT TFT_DE =3D VGA_OUT_BLANK_Z > =A0PORT DCR_Rst =3D sys_bus_reset > =A0PORT DCR_Clk =3D sys_clk_s > =A0PORT TFT_VGA_R =3D VGA_OUT_RED > =A0PORT TFT_VGA_G =3D VGA_OUT_GREEN > =A0PORT TFT_VGA_B =3D VGA_OUT_BLUE > END > > Thank you in advance Hi, I am not sure how your other EDK setup files looks like but still thot of sharing some info. Note: PLB can be configured as 32,63 or 128 dwidth and address access is by default 32. DCR address access is 10 width so please study address translation section of the Product spec. Now coming to direct query ....the bridge core has registers classified as slave access registers,interrupt registers. I think slave access register may not start from 0. In this case DCR is slave so make sure you are setting proper reg address space. Hope this helps. SundarArticle: 136322
Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote: > >Reset signal is an input of FPGA, I use a special module to treat this > >external reset, reset_int had already synchronize with global clk, > >then I use BUFG like this, > > BUFG reset > > ( .I (reset_int), > > .O(reset_n) > > ); > >The reset_n is a very high fanout network. In other modules, reset_n > >signal is used directly to reset logic, I think it is synchronous > >design, reset_n is an output of BUFG, so I do not synchronize it > >locally at each state machine. Dose it matter? > High fanout signals are "interesting". > Routing takes a long time relative to how fast you can clock a > well placed small design. It can easily take more than a clock period > to get a signal across the chip. > Check your documentation. My old copy of the library guide says > BUFG is a global clock buffer. It won't help you to distribute > anything but a clock. > You may be able to make your design work by splitting your reset signal > into several signals with different names, one for each region of > the chip. You can add extra pipeline stages as necessary to > meet timing. > If you keep the number of pipeline stages in each branch the > same, then all the local reset signals will get cleared at > the same time. > >> It may take some extra logic if your design depends upon a chain > >> of state machines coming out of reset together. > >What does this mean? > >Thank you for you replay. > If you don't keep the number of pipeline stages in each branch > the same, then some sections (state machines) will come out of > reset before others. Shouldn't make using GSR and the STARTUP primitive make life easier? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 136323
Hello, I am relatively inexperience and I'm looking for some advice on a system I am designing. The system accesses a memory location and uses information stored at that address to access the next memory element. this means that every clock cycle a new memory element is addressed and the information at that address has to be ready to be read at start of the next clock cycle. I currently have the system implemented on a virtex 2 pro board using the on chip block rams, but I now need to expand the design. 1. What sort of memory should I use (ddr, asyncronous...), and where can I find information about how to read and write to the Dimm slots (The xilinx site has information, but I was hoping for something a little more practical) 2. What is the best way of initializing this memory, considering the memory will probably be a couple of Megs in size. ThanksArticle: 136324
On 21 Okt., 15:33, Pratap <pratap.i...@gmail.com> wrote: > On Oct 20, 2:39 pm, Darol Klawetter <darol.klawet...@l-3com.com> > wrote: > > > > > On Oct 20, 9:12 am, "sebastian.schuep...@gmail.com" > > > <sebastian.schuep...@googlemail.com> wrote: > > > Hi, > > > > I would like to connect an external clk source (i.e. signal generator) > > > to my virtex 2 pro board (xupv2p) > > > The thing is that I didn't really unterstand the concept of > > > differential clocks. Can I just connect one clk source to one input or > > > do i have to have an input for both EXTERNAL_CLOCK_P and > > > EXTERNAL_CLOCK_N. Whats the difference between those. > > > > Thanks for your help. > > >Sebastian > > > The differential clock input circuitry of the FPGA measures the > > voltage difference between the two inputs, not their absolute voltage > > level with respect to a common reference (e.g. ground). The advantage > > of differential clocks is greater noise immunity. If the differential > > pair is routed correctly, then a noise source will couple into both > > inputs, affecting the common mode voltage but not the voltage > > difference. > > > Also, differential pairs cancel out self noise because each signal of > > the pair emits an EM field that is of opposite phase with respect to > > the other. There's plenty of info on the web if you want more detail. > > > Darol Klawetter > > I am regularly using the pin "EXTERNAL_CLOCK_P" for my purpose > and I am leaving the other node "EXTERNAL_CLOCK_N" unconnected.It > works.In this case in the ucf file you will have to use the standard > "LVCMOS25" or LVTTL instead of "LVDS". > > -Pratap Thanks for your help. This is exactly what I was looking for. I tried it and it works with LVTTL.
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