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On Jun 24, 5:19 am, muthu...@gmail.com wrote: > How do we decide which simulation should we go with for a project? > I understand in general VCS is cycle-based simulator and Modelsim is > Event-based simulator. > > But even in VCS when we compile VHDL design there is an option to > choose the simulation type "Cycle-based" or "Event-based". > > Best regards, > Muthu Depending on how you write your RTL code, an event based simulator can perform nearly as well as a cycle based one. Most good simulators already consolidate processes that share the same sensitivity list to reduce overhead. Clocked processes that share the same clock (and async reset, if applicable) get merged, but combinatorial processes, which almost never share entire sensitivity lists, don't. So if you RTL is almost exclusively clocked processes (with very few combinatorial ones), it is for all practical purposes, a cycle based simulation. Andy AndyArticle: 133326
On Jun 24, 3:19=A0am, grant0920 <grant0...@gmail.com> wrote: > Are there any > research groups who can apply such placement methods in a =93real=94 DPR > architecture? > Is there any architecture that can freely > be placed the partial bitstreams at run-time? Thanks very much! I suggest you read this paper from FPL 2007: http://www.ccm.ece.vt.edu/papers/athanas_2007_FPL07_wod.pdf The authors developed tools to dynamically relocate partial bitstreams in Xilinx devices, along with a channel router to wire them up again. This does enable the use of module placement algorithms in real-time and frees the design from fixed module size constraints. StephenArticle: 133327
Hi I was wondering if anyone can tell me if using edk, is it possible to create 2 separate peripherals with external ports that can communicate with each other? What i'm trying to design is a peripheral which acts as a pipeline stage which has some memory that is written via a microblaze. This memory is then used to store coefficients to be used during normal pipeline operation. Multiple pipeline stages should then be added and connected to each other using external ports (via the .mhs file ) and run independently of the microblaze. I have constructed these blocks and the memory portion is working however i cannot get the 2 peripherals to communicate with each other is there anything i'm overlooking? Has anyone done anything similar to this? ShaneArticle: 133328
Erik Anderson wrote:
> My question to the community is, does anyone
> have best practices techniques that address the multiple FPGA target
> problem?
The top synthesis entity would instance the rtl entities
and unbound netlist components.
The top simulation UUT would instance the same rtl entities
and sim models of the device netlists.
> Is there a good way to write your code to encourage multiple
> FPGA development?
Minimize or eliminate the use of device netlists.
If the netlists differ between brands,
one or the other will need wrapper logic
to make up the difference.
> Also, is there a good way to construct your
> directory structure within a code repository?
I don't think that matters much
as long as it is simple and doesn't change.
Synthesis is controlled by a file list anyway.
Simulation is controlled by a makefile or script.
The important thing is that everyone commits changes
and someone runs a daily sim and synth build
that starts from scratch.
-- Mike Treseler
Article: 133329Matthew Hicks wrote: > Try to make an architecturally independent wrapper that has internal > implementations for each target device. As far as directory structure, > I like the method commonly used for embedded OSes of making a clear > division between device independent and device dependent code. The rest > of the structure depends heavily on the complexity and structure of the > project but I tend to create a folder for each high-level function. I would have to agree completely with Matthew. I have a project which spans both Xilinx and Altera, and a number of different target platforms of each! I've had moderate success by doing exactly as Matthew descibes... The common code is situated in the main code trunk. I have device-dependent implementations in a per-device directory (and PLL/DCM is exactly one example of this), (eg. Cyclone II, Spartan III), but wrapped with a high-level device-independent wrapper. Similarly, I have a target platform independent "top level" design which is wrapped again by target-dependent code in per-target directories (eg. DE1, DE2, RC-10) to form the top level of each project build. FWIW I also have re-usable "modules" at a lower level to further complicate matters, but I won't confuse the issue here. It's taken a bit of time and a lot of maintenance to get to this point as the project has evolved, adding platforms and devices, but I think in your case there's less build options so it should pull together with minimal effort. I also wrote a Pearl script to elaborate and/or synthesise the entire code tree (using wildcards etc) so at any point I can quickly see what I may have "broken" with my last set of changes... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 133330
On Jun 24, 2:01=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > MikeWhy wrote: > > (snip on aliasing and imaging) > > >>http://www.nikonians.org/nikon/d200/nikon_d200_review_2.html#aa95cf09 > > Sure, I've clicked the shutter a few times. I was even around when Sigma= > > splatted in the market with the Foveon sensor. All the same, Bayer > > aliasing isn't related to Nyquist aliasing and sampling frequency. The > > OP needn't concern himself with Nyquist considerations. Yes? > > Bayer aliasing and sampling (spatial) frequency are exactly related > to Nyquist aliasing, however the OP was asking about the time domain > signal coming out of a CCD array. =A0That signal has already been > sampled and Nyquist should not be a consideration. =A0(Unless one is > sampling the CCD output at a lower frequency.) =A0The OP didn't explain > the optical system at all, so I can't say if that is a concern > or not. > > -- glen Thanks guys, all the suggestions and explanations have been very helpful! One more question regarding the FIFO inside the FPGA. I am planning to use two 12 bit ADC (4 diff inputs in total) sampling at 40 MHz. Now that means I will have 120 KBytes (960 Kbits) of data per frame to store before I transfer it over the bus at low rate. It seems like a FIFO is the best way to buffer this data and transfer it with a slower clock later or maybe even four different FIFO for each channel (240 Kbits each). Xilinx Spartan-3 XC3S4000 has a total of 1,728Kbits (enough for 960 Kbits per frame) of block RAM (4 RAM columns, 24 RAM blocks per column and 18,432 bits per block RAM) that I guess I can use for FIFOs ? I would like a FIFO of size (20K x 12 bits) =3D 240 Kbits. Can I just instantiate that using the CoreGeneator ? Not sure if I understand all this right ... the XC3S4000 is little bigger for what I need to do in terms of logic ... but then again it seems like the only one with enough block ram for the FIFOs unless I am misunderstanding something. Please advise ... Thanks !Article: 133331
On 24 Jun., 12:19, muthu...@gmail.com wrote: > How do we decide which simulation should we go with for a project? > I understand in general VCS is cycle-based simulator and Modelsim is > Event-based simulator. > > But even in VCS when we compile VHDL design there is an option to > choose the simulation type "Cycle-based" or "Event-based". Cyclebased is a reduction of resolution with gain of speed. You won't do a event based simulation of booting the OS on a microcontroller unless you have really too time in the design schedule :). But a cycle based simulation gives you no chance of simulating designs with multiple clock domains propperly (every asynchronous input is a new clock domain). And you won't learn anything when doing backannotated simulations cycle based. bye ThomasArticle: 133332
"ertw" <gill81@hotmail.com> wrote in message news:0a1b0830-7fc9-466c-8c22-8a5c9555c1b3@m3g2000hsc.googlegroups.com... One more question regarding the FIFO inside the FPGA. I am planning to use two 12 bit ADC (4 diff inputs in total) sampling at 40 MHz. Now that means I will have 120 KBytes (960 Kbits) of data per frame to store before I transfer it over the bus at low rate. It seems like a FIFO is the best way to buffer this data and transfer it with a slower clock later or maybe even four different FIFO for each channel (240 Kbits each). Xilinx Spartan-3 XC3S4000 has a total of 1,728Kbits (enough for 960 Kbits per frame) of block RAM (4 RAM columns, 24 RAM blocks per column and 18,432 bits per block RAM) that I guess I can use for FIFOs ? I would like a FIFO of size (20K x 12 bits) = 240 Kbits. Can I just instantiate that using the CoreGeneator ? Not sure if I understand all this right ... the XC3S4000 is little bigger for what I need to do in terms of logic ... but then again it seems like the only one with enough block ram for the FIFOs unless I am misunderstanding something. Please advise ... ========== Yikes. The 4000 is a bit big if that's all you're doing. I guess this is the fun part of the job, and I wouldn't dream of depriving you of it. :) The choices are to slow it down; store it off chip; or suck it up and get the big chip for its block ram. I like using an overly large chip least, but only you know the constraints of why so fast and what's possible. 3 ns DDR2 SDRAM is pretty cheap these days ($10 single quantity for 16Mx16 bit). So, I take it the device doesn't exist yet?Article: 133333
The thing is really odd. I wanted to figure out when the program jumps to the address 0x60. I used XMD, set a breakpoint to the interrupt and went through the whole interrupt stuff step by step (i.e. instruction by instruction). I could see, that the program is continued correctly after the interrupt (it sends data through UART). So everything worked as expected! However, when I then use "con" to continue the program (after the interrupt was successful and the normal program already continued), the program freezes again and the program counter is set to 0x60 (which seems to be a program exception or something like that). How can that be? Matthias > I have the following problem on a Virtex5 system: > I use an interrupt controller, that is connected to the PPC interrupt > port. The interrupt controller and the PPC interrupt handler are > initialized but working ONLY for the very first interrupt. After the > first interrupt occured the processor hangs at address 0x60, which is in > the interrupt vector table: > > 00000060 <IVOR6>: > 60: 7c 70 43 a6 mtsprg 0,r3 > 64: 38 60 00 06 li r3,6 > 68: 7c 60 43 a6 mtspr 256,r3 > 6c: 48 00 00 94 b 100 <non_critical_irq> > > Did I miss something about the initialization? I used the source code > provided with the examples of the xps_intc. > > MatthiasArticle: 133334
On 24 Jun., 09:19, grant0920 <grant0...@gmail.com> wrote: > Hi All: > > There are many papers about the 1D or 2D placement. However, > the papers are almost for the algorithm discussion. The current method > for dynamically partially reconfigurable architectures is EAPR flow, > but the DPR blocks need to be defined at design-time by using the ucf > file. All the area constraints are finally included in the static_full > and partial bitstreams. So, I am very confused how 1D and 2D placement > can be applied to a =93real=94 DPR system at run-time. Are there any > research groups who can apply such placement methods in a =93real=94 DPR > architecture? I know that some proposed methods, which contained a > specific filter to re-modify the location information in the > bitstream, can relocate a partial bitstream to a new location. > However, the area sizes of DPR blocks need to be the same. However, > for example, two DPR blocks are implemented at design-time. Is it > possible that the two DPR areas can be merged for placing a partial > bitstream that needs both the resources of two DPR blocks like real 1D > or 2D placement at run-time? Is there any architecture that can freely > be placed the partial bitstreams at run-time? Thanks very much! > > Best regards, > Huang Hi Huang, if you like, you can have a look at the following papers from FPL 2007 and ERSA 2007: "A Design Methodology for Communication Infrastructures on partially reconfigurable FPGAs", presented at FPL 2007, shows a design flow, which allows to place several hardware modules within a partial reconfiguration region. Thus, the resources can be used more efficient than compared to other approaches. "Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs", presented at ERSA 2007, can be seen as an addition to the FPL-Paper. An "embedded communication macro" is introduced which enables the communication between the modules. The methods can be used for 1D as well as 2D placement. Best Regrads, JensArticle: 133335
Just a small update again. I managed to get the design working a bit better... I modified my linker script, such that the .vectors section is now stored in the BRAM memory instead of the DDR2 memory. As a result the processor keeps working after an interrupt. So maybe the problem was some kind of timeout error because of the slow DDR-RAM? But I now have the problem that the processer seems to see interrupts all the time. Actually there are no interrupts from the interrupt controller. So the processor just stays in the interrupt routines for an external interrupt all the time and the normal program is never continued after there was one or more real interrupts. But it is now possible to have more than just a single interrupt. The odd thing again is that the processor goes to the normal program when I use step by step in XMD. Matthias Matthias Alles schrieb: > The thing is really odd. I wanted to figure out when the program jumps > to the address 0x60. I used XMD, set a breakpoint to the interrupt and > went through the whole interrupt stuff step by step (i.e. instruction by > instruction). I could see, that the program is continued correctly after > the interrupt (it sends data through UART). So everything worked as > expected! > However, when I then use "con" to continue the program (after the > interrupt was successful and the normal program already continued), the > program freezes again and the program counter is set to 0x60 (which > seems to be a program exception or something like that). > > How can that be? > > Matthias > > > >> I have the following problem on a Virtex5 system: >> I use an interrupt controller, that is connected to the PPC interrupt >> port. The interrupt controller and the PPC interrupt handler are >> initialized but working ONLY for the very first interrupt. After the >> first interrupt occured the processor hangs at address 0x60, which is in >> the interrupt vector table: >> >> 00000060 <IVOR6>: >> 60: 7c 70 43 a6 mtsprg 0,r3 >> 64: 38 60 00 06 li r3,6 >> 68: 7c 60 43 a6 mtspr 256,r3 >> 6c: 48 00 00 94 b 100 <non_critical_irq> >> >> Did I miss something about the initialization? I used the source code >> provided with the examples of the xps_intc. >> >> MatthiasArticle: 133336
Hi.
I'm trying to write a couple of values to a block of memory that is
read by the system generator during hw-co-sim.
I Use a Sysgen shared memory block in my design. I write to the shared
mem. using the following code.
uint32_t *test;
test = (uint32_t *)0x84018000; //Base address of shared mem.
test[0] = 1;
test[1] = 2;
test[2] = 3;
test[3] = 4;
For some reason, it is always only the first value i write that is
actually stored in the shared memory. The others are not. Does anyone
have any idea what is happening?
Article: 133337On 23 Jun., 15:00, "Norman Bollmann" <wirdnichtgele...@gmx.net> wrote: > Therefore external memory has to > be used, slowing down the throughput. Target is a database searching of > 262144 elements with 16 bit each in maximum 220 ms. What type of searches are you performing? What other operations are required? There are data structures that do an identity lookup in constant time and interval searches in logarithmic time. A CPU should do that in less than a microsecond. Kolja SulimmaArticle: 133338
Spartan 3E starter kit: I tried (like all beginners) to read rotary switch (knob) using FSM with 8 states, 4 for CW and 4 for CCW movements. I did not debounce phased switch inputs. It works fine. But I remember seeing much debate on this issue and claims of success with 4 FF's (plus debouncers). My design created 3 FFs and works fine without debouncers. What have I done wrong? Do "Spartan 3E starter kits" already have debouncers? Another question: When I include something like a<=a+1; and a<=a-1; it puts adders and stuff. Is it possible to force the use of async. up- down counters? ThanksArticle: 133339
We are students who are trying to interface JHD1629a LCD to spartan 3a dsp 1800 board. In the board the are two slots of EXP connectors. We are confused how to join connect LCD with EXP connector slots.Article: 133340
"RCIngham" <robert.ingham@gmail.com> wrote in message news:zq6dnfbRSeEDOsLV4p2dnAA@giganews.com... > Is the concept of "Content addressable memory" known to you? > > http://en.wikipedia.org/wiki/Content-addressable_memory > Hi Robert, Do you have any examples of any 'proper' CAM devices that I can research? I know that Altera's ESBs can be used as small CAMs, and that Xilinx have an app. note design that can do single cycle reads and multi-cycle writes using a BlockRAM. It would appear that Micron have dumped their 2Mb 'Harmony' device long ago. I found various dead links to products, but nothign active. Thanks, Syms.Article: 133341
Hello
Very easy question, but I just wanna make sure that I have done it the
correct way so that I dont have to look in this simple stuff for errors :)
Basically I have two FPGAs (Control & Target FPGAs) and I wanna foward
data between them for receiving and sending single bits. My VHDL code
for the Control FPGA looks as follows:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ForwardBits is
port(
a_control : in std_logic;
b_control : out std_logic;
a_target : out std_logic;
b_target : in std_logic
);
end ForwardBits;
architecture Behavior of ForwardBits is
begin
a_target <= a_control;
b_control<= b_target;
end architecture Behavior;
And the other thing I have to do is mapping the signals to PINs of the
Control FPGA which looks as follows:
NET "b_control" LOC = "M25";
NET "a_control" LOC = "M26";
NET "a_target" LOC = "U2";
NET "b_target" LOC = "V5";
Basically, the only erros could be done with the Pin mapping but that
should be fine.
Else if I should have missed something I would be thankful for letting
me know
Cheers
Article: 133342meralonurlu@gmail.com wrote: > Spartan 3E starter kit: > I tried (like all beginners) to read rotary switch (knob) using FSM > with 8 states, 4 for CW and 4 for CCW movements. I did not debounce > phased switch inputs. It works fine. But I remember seeing much debate > on this issue and claims of success with 4 FF's (plus debouncers). My > design created 3 FFs and works fine without debouncers. What have I > done wrong? Do "Spartan 3E starter kits" already have debouncers? > Another question: When I include something like a<=a+1; and a<=a-1; it > puts adders and stuff. Is it possible to force the use of async. up- > down counters? > Thanks How do you suppose an async up/down counter would be implemented? Possibly with adders and stuff? A problem with async elements under mechanical control is that the switch-generated clock is never guaranteed to be free of runt pulses or pulses that violate the minimum clock period. In general, an asynchronous design is prone to many problems unless the single element is the only thing the designer is putting into the circuit (which is quite a waste of an FPGA!), Resynchronizing outside controls like the mechanical switch eliminates many of the problems associated with unpredictable clocks and allows a full system to be integrated without the complexities of combining asynchronous elements. - John_HArticle: 133343
Friends, I have been using the Xilinx tools ISE, EDK in Windows environment. But now planning to use Linux PC for running ISE and EDK. I am curious, which platform (Windows or Linux) is good for Xilinx tools? I am planning to use the ISE and EDK in GUI mode, not command line mode. Linux version would be Red hat Enterprise WS version 4.0 (64-bit). Thank you. Best regards, MuthuArticle: 133344
hi all; I am using HWICAP to configure certain LUTs , and as mentioned in the HWICAP data sheet that "when LUTs are configured in Shift Register Mode or as a RAM. If a LUT is modified or just read back in a column that also has a LUT RAM or LUT shift register, then the LUT or shift register will be interrupted and it will lose its state. To resolve the problem, the LUT shift registers and LUT RAMs should be placed in columns that are not read back or modified. " ,what i know form the beginning is the instance name of the LUTs , is it possible to add constrains to avoid placing these LUTs in columns that contain RAMs or Shift registers, or may be there is another solution. thanksArticle: 133345
fmostafa, Which family? In V5, we have an added bit in the bitstream which prevents LUTRAM and SRL16/32 from being readback. The function performed is called GLUTMASK (not that it matters what it is called). It was added just so you do not have to deal with "knowing" which LUT are not to be disturbed (by a readback/verify). AustinArticle: 133346
On Jun 25, 4:44 pm, austin <aus...@xilinx.com> wrote: > fmostafa, > > Which family? > > In V5, we have an added bit in the bitstream which prevents LUTRAM and > SRL16/32 from being readback. The function performed is called GLUTMASK > (not that it matters what it is called). It was added just so you do > not have to deal with "knowing" which LUT are not to be disturbed (by a > readback/verify). > > Austin hi, thanks for your fast replay, but my family is virtex 2 pro, is there a solution based on constrains.Article: 133347
On Jun 25, 4:44 pm, austin <aus...@xilinx.com> wrote: > fmostafa, > > Which family? > > In V5, we have an added bit in the bitstream which prevents LUTRAM and > SRL16/32 from being readback. The function performed is called GLUTMASK > (not that it matters what it is called). It was added just so you do > not have to deal with "knowing" which LUT are not to be disturbed (by a > readback/verify). > > Austin hi, thanks for your fast replay, but my family is virtex 2 pro is there a solutionArticle: 133348
fmostafa, In Virtex 2 Pro, you would need to apply placement constraints to place the LUTRAM/SRL16 all in the same column so you could avoid that column later in a readback. http://toolbox.xilinx.com/docsan/xilinx4/data/docs/cgd/types3.html Such constraints may make the design so it can not be routed. It is not a simple process, and one that would require a lot of manual floor planning, and trial and error. That is why we added the GLUTMASK feature. AustinArticle: 133349
Symon wrote:
> Do you have any examples of any 'proper' CAM devices that I can research? I
> know that Altera's ESBs can be used as small CAMs, and that Xilinx have an
> app. note design that can do single cycle reads and multi-cycle writes using
> a BlockRAM. It would appear that Micron have dumped their 2Mb 'Harmony'
> device long ago. I found various dead links to products, but nothign active.
Useful CAM structures don't fit well in FPGAs
and the vendors have quit trying.
Some sort of hash table may be a better fit.
http://en.wikipedia.org/wiki/Hash_table
-- Mike Treseler
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z