Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Jan 29, 11:46 am, jleslie48 <j...@jonathanleslie.com> wrote:
> On Jan 29, 12:35 am, rickman <gnu...@gmail.com> wrote:
>
> > I have to say that I find your learning process to be very
> > interesting. It has been so long for me that I have forgotten exactly
> > what it was that I had to learn or unlearn to switch from software to
> > HDL. I am getting a feel for that again.
>
> So glad your enjoying yourself :))))))
>
> Rata-fracken,summana,friken,thing-a-mabob....
Ok, boys, things are finishing up on a high note this week.
My partner in crime here in NJ got his UART working, and with it
albiet not pretty,
a working hello world program. Now the producers and consumers are a
bit raw,
but the throttle on the 16 byte "bucket brigade" fifo seems to be
working.
His messaging was pretty messy, but using some of the techniques
discussed here,
I'm starting to clean them up. here is a snippet of the cleaned up
code:
----------------------------
constant project_name_stg : string := "Testing 1, 2, 3! and
some more characters too!!!";
SIGNAL project_name_cnt : INTEGER RANGE
project_name_stg'range;
SIGNAL lprj_MESS_TRAN : STD_LOGIC := '0';
constant person_mess_stg : string := "Cindy Crawford's
measurments are: 34, 24, 34";
SIGNAL person_mess_cnt : INTEGER RANGE
person_mess_stg'range;
SIGNAL lprj_person_TRAN : STD_LOGIC := '0';
SIGNAL lprj_PERSON_TRAN_ENABLE :
STD_LOGIC := '0';
...
-------------------------------------------------------------------------------------------------
-- SENDING lprj PROJECT MESSAGE TO TRANSMIT UART ( TX_DATA_IN
[ 7-0 ] )
-------------------------------------------------------------------------------------------------
P16: PROCESS ( CLK_16_6MHZ, UART_RESET_BUFFER, TX_BUFFER_FULL,
TX_WRITE_BUFFER_STB,
lprj_MESS_TRAN, project_name_cnt,
lprj_PERSON_TRAN, person_mess_cnt,
lprj_RECEIVE_TRAN, RECEIVE_MAX, RECEIVE_MESS
( 0 TO lprj_RECEIVE_MAX ) )
BEGIN
IF ( CLK_16_6MHZ = '1' AND CLK_16_6MHZ'EVENT ) THEN
IF ( UART_RESET_BUFFER = '0' ) THEN
IF ( ( lprj_MESS_TRAN = '1' ) AND
( TX_BUFFER_FULL = '0' ) AND
( TX_WRITE_BUFFER_STB = '0' ) ) THEN
--TX_DATA_IN( 7 DOWNTO 0 ) <= PROJECT_NAME
( lprj_MESS_CNT );
TX_DATA_IN <= to_slv(project_name_stg
( project_name_cnt ));
ELSIF ( ( lprj_PERSON_TRAN = '1' ) AND
( TX_BUFFER_FULL = '0' ) AND
( TX_WRITE_BUFFER_STB = '0' ) ) THEN
TX_DATA_IN <= to_slv(person_mess_stg
( person_mess_cnt ));
ELSIF ( ( lprj_RECEIVE_TRAN = '1' ) AND
( TX_BUFFER_FULL = '0' ) AND
( TX_WRITE_BUFFER_STB = '0' ) ) THEN
TX_DATA_IN( 7 DOWNTO 0 ) <= RECEIVE_MESS( RECEIVE_MAX );
END IF;
END IF;
END IF;
END PROCESS P16;
-----------------------------
which while is a vast improvement over what code he gave me:
-------------------------
-- ASCII NUMBERS
-----------------------------------------------------------------------------
constant N0 : std_logic_vector( 7 DOWNTO 0 ) := x"30";
-- ASCII VALUE FOR UART
constant N1 : std_logic_vector( 7 DOWNTO 0 ) := x"31";
-- ASCII VALUE FOR UART
constant N2 : std_logic_vector( 7 DOWNTO 0 ) := x"32";
-- ASCII VALUE FOR UART
constant N3 : std_logic_vector( 7 DOWNTO 0 ) := x"33";
-- ASCII VALUE FOR UART
constant N4 : std_logic_vector( 7 DOWNTO 0 ) := x"34";
-- ASCII VALUE FOR UART
...<the whole alphabet>...
----------------------------------------------------------------------------------------------
-- LOKI PERSON MESSAGE ARRAY
- 44 CHARACTERS
----------------------------------------------------------------------------------------------
SUBTYPE REG_A IS STD_LOGIC_VECTOR( 7 DOWNTO 0 );
TYPE LOKI_PERSON IS ARRAY ( INTEGER RANGE <> ) OF REG_A;
SIGNAL LOKI_PERSON_TRAN :
STD_LOGIC := '0';
CONSTANT LOKI_PERSON_MAX :
INTEGER := 43;
SIGNAL LOKI_PERSON_CNT : INTEGER RANGE 0 TO
LOKI_PERSON_MAX;
SIGNAL LOKI_PERSON_TRAN_ENABLE :
STD_LOGIC := '0';
SIGNAL PERSON_MESS : LOKI_PERSON( 0 TO
LOKI_PERSON_MAX )
:= ( CR, AC, AI, AN, AD, AY, SP, AC, AR, AA, AW, AF, AO,
AR, AD, PO, AS, SP,
AM, AE, AA, AS, AU, AR, AE, AM, AE, AN, AT, AS, SP,
AA, AR, AE, SP,
N3, N4, SP, N2, N4, SP, N3, N4, CR );
...
------------------------
However, my version of the code skips the first letter of each of the
messages!
the problem I'm sure resides in this bit here:
mine:
-------------------------------------------------------------------------------------------------
-- INITIALIZING lprj PROJECT MESSAGE COUNT ( project_name_cnt )
-------------------------------------------------------------------------------------------------
P10: PROCESS ( CLK_16_6MHZ, UART_RESET_BUFFER, UART_RESET_NEXT,
lprj_MESS_TRAN, TX_WRITE_BUFFER_STB )
BEGIN
IF ( CLK_16_6MHZ = '1' AND CLK_16_6MHZ'EVENT ) THEN
IF ( ( UART_RESET_BUFFER = '0' ) AND
( UART_RESET_NEXT = '1' ) ) THEN
project_name_cnt <= project_name_stg'low;
ELSIF ( ( lprj_MESS_TRAN = '1' ) AND
( TX_WRITE_BUFFER_STB = '1' ) AND
( project_name_cnt /=
project_name_stg'high ) ) THEN
project_name_cnt <= ( project_name_cnt + 1 );
END IF;
END IF;
END PROCESS P10;
his:
-------------------------------------------------------------------------------------------------
-- INITIALIZING LOKI PROJECT MESSAGE COUNT ( LOKI_MESS_CNT )
-------------------------------------------------------------------------------------------------
P10: PROCESS ( CLK_16_6MHZ, UART_RESET_BUFFER, UART_RESET_NEXT,
LOKI_MESS_TRAN, TX_WRITE_BUFFER_STB )
BEGIN
IF ( CLK_16_6MHZ = '1' AND CLK_16_6MHZ'EVENT ) THEN
IF ( ( UART_RESET_BUFFER = '0' ) AND
( UART_RESET_NEXT = '1' ) ) THEN
LOKI_MESS_CNT <= 0;
ELSIF ( ( LOKI_MESS_TRAN = '1' ) AND
( TX_WRITE_BUFFER_STB = '1' ) AND
( LOKI_MESS_CNT /= LOKI_MESS_MAX ) ) THEN
LOKI_MESS_CNT <= ( LOKI_MESS_CNT + 1 );
END IF;
END IF;
END PROCESS P10;
--------------------------
I'm guessing that project_name_stg'low is coming in at a 1 instead of
0, and
the increment therefore goes to 2, and I start with the second
character.
Since I've also finally got the testbench going, I should be able to
see that
project_name_cnt increment to 2 before the first character hits the
the TXT_DATA_IN.
That's what I about to check out. its Testbench time!!!
To be continued....
Article: 137826
On Fri, 30 Jan 2009 13:39:41 -0800 (PST), jleslie48 wrote:
>Ok, boys, things are finishing up on a high note this week.
Good to hear.
A few suggestions for your consideration....
>P16: PROCESS ( CLK_16_6MHZ, UART_RESET_BUFFER, TX_BUFFER_FULL,
>TX_WRITE_BUFFER_STB,
> lprj_MESS_TRAN, project_name_cnt,
> lprj_PERSON_TRAN, person_mess_cnt,
> lprj_RECEIVE_TRAN, RECEIVE_MAX, RECEIVE_MESS
>( 0 TO lprj_RECEIVE_MAX ) )
AAAARGH. A clocked process should be sensitized ONLY
to its clock (and its asynchronous reset, if it has one).
It does nothing unless there's an active edge on the
clock, so there is no point in having the process wake
up because of changes on other signals; that's just a waste
of simulation effort and an unnecessary obfuscation.
>BEGIN
> IF ( CLK_16_6MHZ = '1' AND CLK_16_6MHZ'EVENT ) THEN
> IF ( UART_RESET_BUFFER = '0' ) THEN
> IF ( ( lprj_MESS_TRAN = '1' ) AND
> ( TX_BUFFER_FULL = '0' ) AND
> ( TX_WRITE_BUFFER_STB = '0' ) ) THEN
> --TX_DATA_IN( 7 DOWNTO 0 ) <= PROJECT_NAME
>( lprj_MESS_CNT );
> TX_DATA_IN <= to_slv(project_name_stg
>( project_name_cnt ));
>
> ELSIF ( ( lprj_PERSON_TRAN = '1' ) AND
> ( TX_BUFFER_FULL = '0' ) AND
> ( TX_WRITE_BUFFER_STB = '0' ) ) THEN
> TX_DATA_IN <= to_slv(person_mess_stg
>( person_mess_cnt ));
>
> ELSIF ( ( lprj_RECEIVE_TRAN = '1' ) AND
> ( TX_BUFFER_FULL = '0' ) AND
> ( TX_WRITE_BUFFER_STB = '0' ) ) THEN
> TX_DATA_IN( 7 DOWNTO 0 ) <= RECEIVE_MESS( RECEIVE_MAX );
> END IF;
> END IF;
> END IF;
>END PROCESS P16;
As a software guy you must surely see the value in factoring-out
the common conditional expression
TX_BUFFER_FULL='0' AND TX_WRITE_BUFFER_STB='0'
but that's the least of my worries. This code appears to be
some kind of data-stream generator that happens - just happens -
to be sending its data to a UART, rather than a memory or an
Ethernet interface or an LCD display or whatever. It seems
grotesque that its control flow is so intimately tangled with
the internal details of the UART; such an approach is stacking
up many, many problems for the future as your design grows.
Furthermore, it looks pretty strange to me that the code that
indexes/counts its way through the strings is so completely
disconnected from the code that picks up characters in
those strings; that's a good recipe for getting off-by-one
timing errors (as you've discovered). Think about those
old software mantras about "coherence and coupling":
coherent (i.e. closely related) activities should go
together in a common piece of code such as a process;
coupling of one piece of activity to another is bad
and should be avoided - keep your functional blocks
as decoupled as possible.
PLEASE give some consideration to establishing a clear,
simple, UNIFORM interface between your blocks.
As I've pointed out before, the easiest way to do that is
often (not always, but often) to have a ready/valid handshake.
The data consumer asserts "ready" on any clock cycle in
which it can have data written to it. The producer
asserts "valid" on any clock cycle where its data
output is useful. On clock cycles where "ready" and
"valid" are BOTH true, both parties agree that an item
of data is transferred. At this point:
1.the producer must EITHER
(a) update its output to be the next data item in
sequence, leaving "valid" true; OR
(b) drop its "valid" signal to false so that the
consumer does not try to take data on the next clock.
2.the consumer must EITHER
(a) drop its "ready" signal to false so that "valid" on
the next clock would not transfer any data, OR
(b) hold "ready" true, and be prepared to accept new
data on the next clock.
In this way you can almost completely decouple the
producer and consumer, with only the data and this simple
two-wire clocked handshake between them. Producers and
consumers can then be mixed-and-matched in a very simple way.
It should be pretty easy to re-jig your UART control signals
to conform to this arrangement. And it will be VERY easy
to rework your data producer to do likewise.
Enjoy your weekend :-)
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 137827On 2009-01-30, colin <colin_toogood@yahoo.com> wrote: > > Has anyone here successfully built a byteblaster clone. Yes. > connected up the JTAG pins as specified and Quartus accepts that a > byteblaster is fitted. That's based on a couple of the parallel port pins being shorted. Doesn't tell you much about the rest. > I can see activity on TCLK, TMS and TDI at the > FPGA and TDO is getting back to the parallel port but Quartus cannot > auto detect anything. You mean it CAN auto detect the cable but no devices? If you want to see the one I made, it's on the edge of this board: http://ad7gd.net/flex/ It's self-contained in the schematic, too. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 137828
rickman <gnuarm@gmail.com> wrote: (snip, I wrote) >> There are some people interested in porting old computer >> designs, such as the Apple II, to FPGA. In that case, it >> might make sense to include the original tristate lines. (snip) > This is a good example of what I was thinking of. If I were porting > such a design, although "port" is not really the correct term because > there is no existing HDL code, I would not describe tri-state buffers > in my code. Well, some people still use schematic capture for new designs. In this case, the old design is a schematic on paper. > I would describe a selection function which was a top > level OR with each of the "tri-state" buffers being replaced by an AND > gate. Say, for example, the Apple II with add-in cards. One could have the main board as a verilog module, and add-in cards (serial, disk, video) as separate modules that are included and then loaded into the synthesis tools. > If there were timing issues that required the bus to "remember" > the last driven state, I would add a latch with the enable driven by > an OR of all of the individual enables. I don't see how you could > expect a synthesis tool to do anything other than to replace the tri- > state drivers with the OR-AND multiplexer and I don't see any reason > to even try to duplicate a design at that level. There might have been discussion on the need to keep old data on the Apple II bus. Otherwise, one should be happy if the tools convert tristate to AND/OR logic. That would complicate the verilog code for a system bus, though. For anything within a module, I agree at least 99%. -- glenArticle: 137829
> What happened to 4 & 5? Looks like Xilinx marketing want to 'resync' as the Virtex 6 and Spartan 6 (and hey, it's a number higher than Altera so that's worth something in their world, right ;) Anyone seen package choices for Spartan 6 yet ? Are Xilinx going to push prices, or leave the sub $1 / Low power area to Actel ? -jgArticle: 137830
On Jan 30, 5:20=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Fri, 30 Jan 2009 13:39:41 -0800 (PST), jleslie48 wrote: > >Ok, boys, things are finishing up on a high note this week. > > Good to hear. > > A few suggestions for your consideration.... > > >P16: =A0PROCESS ( CLK_16_6MHZ, UART_RESET_BUFFER, TX_BUFFER_FULL, > >TX_WRITE_BUFFER_STB, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 lprj_MESS_TRAN, =A0 =A0project_name= _cnt, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 lprj_PERSON_TRAN, =A0person_mess_cn= t, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 lprj_RECEIVE_TRAN, RECEIVE_MAX, =A0= =A0 =A0RECEIVE_MESS > >( 0 TO lprj_RECEIVE_MAX ) =A0) > > AAAARGH. =A0A clocked process should be sensitized ONLY > to its clock (and its asynchronous reset, if it has one). > It does nothing unless there's an active edge on the > clock, so there is no point in having the process wake > up because of changes on other signals; that's just a waste > of simulation effort and an unnecessary obfuscation. > > > > >BEGIN > > =A0 =A0 IF ( CLK_16_6MHZ =3D '1' AND CLK_16_6MHZ'EVENT ) THEN > > =A0 =A0 =A0 =A0 =A0IF ( UART_RESET_BUFFER =A0 =3D '0' ) THEN > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 IF =A0 =A0( ( lprj_MESS_TRAN =A0 =A0 =A0=3D= '1' ) AND > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( TX_BUFFER_FULL =A0 =A0 = =A0=3D '0' ) AND > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( TX_WRITE_BUFFER_STB =3D '= 0' ) =A0) THEN > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --TX_DATA_I= N( 7 DOWNTO 0 ) <=3D PROJECT_NAME > >( lprj_MESS_CNT ); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 TX_DATA_IN = <=3D to_slv(project_name_stg > >( project_name_cnt )); > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF ( ( lprj_PERSON_TRAN =A0 =A0=3D '1' )= AND > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( TX_BUFFER_FULL =A0 =A0 = =A0=3D '0' ) AND > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( TX_WRITE_BUFFER_STB =3D '= 0' ) =A0) THEN > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 TX_DATA_IN = <=3D to_slv(person_mess_stg > >( person_mess_cnt )); > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 ELSIF ( ( lprj_RECEIVE_TRAN =A0 =3D '1' ) A= ND > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( TX_BUFFER_FULL =A0 =A0 = =A0=3D '0' ) AND > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ( TX_WRITE_BUFFER_STB =3D '= 0' ) =A0) THEN > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 TX_DATA_IN(= 7 DOWNTO 0 ) <=3D RECEIVE_MESS( RECEIVE_MAX ); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 END IF; > > =A0 =A0 =A0 =A0 =A0END IF; > > =A0 =A0 END IF; > >END PROCESS P16; > > As a software guy you must surely see the value in factoring-out > the common conditional expression > > =A0 TX_BUFFER_FULL=3D'0' AND TX_WRITE_BUFFER_STB=3D'0' > > but that's the least of my worries. =A0This code appears to be > some kind of data-stream generator that happens - just happens - > to be sending its data to a UART, rather than a memory or an > Ethernet interface or an LCD display or whatever. =A0It seems > grotesque that its control flow is so intimately tangled with > the internal details of the UART; such an approach is stacking > up many, many problems for the future as your design grows. > > Furthermore, it looks pretty strange to me that the code that > indexes/counts its way through the strings is so completely > disconnected from the code that picks up characters in > those strings; that's a good recipe for getting off-by-one > timing errors (as you've discovered). =A0Think about those > old software mantras about "coherence and coupling": > coherent (i.e. closely related) activities should go > together in a common piece of code such as a process; > coupling of one piece of activity to another is bad > and should be avoided - keep your functional blocks > as decoupled as possible. > > PLEASE give some consideration to establishing a clear, > simple, UNIFORM interface between your blocks. > > As I've pointed out before, the easiest way to do that is > often (not always, but often) to have a ready/valid handshake. > The data consumer asserts "ready" on any clock cycle in > which it can have data written to it. =A0The producer > asserts "valid" on any clock cycle where its data > output is useful. =A0On clock cycles where "ready" and > "valid" are BOTH true, both parties agree that an item > of data is transferred. =A0At this point: > 1.the producer must EITHER > =A0 (a) update its output to be the next data item in > =A0 =A0 =A0 sequence, leaving "valid" true; OR > =A0 (b) drop its "valid" signal to false so that the > =A0 =A0 =A0 consumer does not try to take data on the next clock. > 2.the consumer must EITHER > =A0 (a) drop its "ready" signal to false so that "valid" on > =A0 =A0 =A0 the next clock would not transfer any data, OR > =A0 (b) hold "ready" true, and be prepared to accept new > =A0 =A0 =A0 data on the next clock. > > In this way you can almost completely decouple the > producer and consumer, with only the data and this simple > two-wire clocked handshake between them. =A0Producers and > consumers can then be mixed-and-matched in a very simple way. > > It should be pretty easy to re-jig your UART control signals > to conform to this arrangement. =A0And it will be VERY easy > to rework your data producer to do likewise. > > Enjoy your weekend :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. all very good points. I didn't write this, my "fpga guy" did. all I know is that it did actually work, and I've only gotten so far as be sure it does actually work, and that for every message, he adds a new boolean semaphore; definitely not a very scalable solution. I'm sure that is how the redundant boolean checks creeped in. My first cleanup was to at least reduce the strings to something that I could actually read. The side effect being that the first character of the string got clobbered and that answer will reside in the spagetti code that you pointed out. Meantime its not immediately obvious to me from the testbench: http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/screencap/screencap10_= missingfirstletter.png I see the "T" getting in, to the datastream, but I haven't found where it got clobbered. I do know the code is a complete mess. The source code is here if anyone is interested: http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/source/LOKI_Top.vhd http://jleslie48.com/fpga_uartjl_01/11jlmod/ccuart01/source/Article: 137831
Hi all I was wondering what is the design for the lookup tables of the logic blocks in FPGAs such as the Virtex model from Xilinx? Does they use pass transistors as most of the academic papers show? or does they use transmission gates? Please provide reference if possible. Thanks.Article: 137832
Hi all I was wondering what is the design for the lookup tables of the logic blocks in FPGAs such as the Virtex model from Xilinx? Does they use pass transistors as most of the academic papers show? or does they use transmission gates? Please provide reference if possible. Thanks.Article: 137833
On Jan 23, 4:49 am, "Symon" <symon_bre...@hotmail.com> wrote: > "Uwe Bonnes" <b...@elektron.ikp.physik.tu-darmstadt.de> wrote in message > > news:glc2p3$er6$1@lnx107.hrz.tu-darmstadt.de... > > > Antti <Antti.Luk...@googlemail.com> wrote: > >> it seems that first references to the upcoming Spartan family are in > >> the wild already > > >>http://www.linkedin.com/in/ericschristiansen > > >> I assume the spartan-6 mentioned there is not a typo > >> (actually i am almost sure it isnt) > > > I neither find XILINX. spartan or fpga mentioned in that resume. > > Look harder? Try CTRL-F ? > > "o Control structure for the digital portion of the transceiver uses an > instantiated microBlaze processor running in a Xilinx Spartan 6 FPGA > o Component selection for the transceiver Common Public Radio Interface > (CPRI) > =A7 Selected SFP+ module used for the optical interface, and a Spartan 6 = FPGA > running CPRI IP to handle the framing, mapping, and interleaving function= s " > > What happened to 4 & 5? > HTH., Syms. I guess the felt the spartan and virtex names needed to be on the same level. Are they really bringing both out at the same time? That seems pretty extreme. I remember when at the 90 nm node they brought out the Spartan 3 first because they thought the cost advantage was more important in the "value" parts. Then they ignored the Spartan family and brought out the Virtex at 65 nm node because it was more cost effective to amortize the investment over the higer price chips. I wonder if the huge effort of bringing both out is going to pay off given the current economic situation. I'm sure this took a huge investment and if they don't sell enough chips, it maybe a case of very bad timing for Xilinx resulting in loss of market share. They say timing is everything. RickArticle: 137834
On Jan 30, 6:43=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > > What happened to 4 & 5? > > Looks like Xilinx marketing want to 'resync' as the Virtex 6 and > Spartan 6 > (and hey, it's a number =A0higher than Altera so that's worth something > in their > world, right ;) > > Anyone seen package choices for Spartan 6 yet ? > > Are Xilinx going to push prices, or leave the sub $1 / Low power area > to Actel ? I sure wish they would support the smaller leaded packages. A decent sized chip in a 100 pin QFP would be so nice; low price, easy assembly and good access to the pins for debug. I don't get why they haven't done this before. Every I/O adds cost. They won't get under $10 in moderate quanties until they pick some better packages. RickArticle: 137835
On Jan 30, 9:27=A0pm, abbas <xfiles.detec...@gmail.com> wrote: > Hi all > > I was wondering what is the design for the lookup tables of the logic > blocks in FPGAs such as the Virtex model from Xilinx? Does they use > pass transistors as most of the academic papers show? or does they use > transmission gates? Please provide reference if possible. > > Thanks. If you understand the difference between pass transistors and transmission gates, then you should be able to figure this out for yourself. RickArticle: 137836
On Jan 31, 8:06=A0am, rickman <gnu...@gmail.com> wrote: > On Jan 30, 6:43=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > > > > What happened to 4 & 5? > > > Looks like Xilinx marketing want to 'resync' as the Virtex 6 and > > Spartan 6 > > (and hey, it's a number =A0higher than Altera so that's worth something > > in their > > world, right ;) > > > Anyone seen package choices for Spartan 6 yet ? > > > Are Xilinx going to push prices, or leave the sub $1 / Low power area > > to Actel ? > > I sure wish they would support the smaller leaded packages. =A0A decent > sized chip in a 100 pin QFP would be so nice; low price, easy assembly > and good access to the pins for debug. =A0I don't get why they haven't > done this before. =A0Every I/O adds cost. =A0They won't get under $10 in > moderate quanties until they pick some better packages. > > Rick Sorry Rick I can not comment in public. I hope it all be known on monday. I have some comments, i make them public as soon as the info is no longer under NDA (that is i can comment on what xilinx has made public itself) AnttiArticle: 137837
I have two modules counter(28-bit) and led decoder(takes 4-bit input)....i want to display the value of counter through seven segment display(SSD). so my interest is to connect upper 4-bit of counter to 4- bit input of led decoder so that change in display on SSD can be seen easily ......i am using the board XSA-50 whose clk is 50 Mz so by using 4-bit counter,its value will be changed so fast that we can not visualize the value in seven segment display.... Some have any idea on it??......any idea will be greatly appreciated....Article: 137838
On Sat, 31 Jan 2009 02:16:42 -0800 (PST), GrIsH
<grishkunwar@gmail.com> wrote:
>I have two modules counter(28-bit) and led decoder(takes 4-bit
>input)....i want to display the value of counter through seven segment
>display(SSD). so my interest is to connect upper 4-bit of counter to 4-
>bit input of led decoder so that change in display on SSD can be seen
>easily ......i am using the board XSA-50 whose clk is 50 Mz so by
>using 4-bit counter,its value will be changed so fast that we can not
>visualize the value in seven segment display....
>
>Some have any idea on it??......any idea will be greatly
>appreciated....
Verilog:
assign LED[3:0] = counter[27:24];
VHDL:
LED(3 downto 0) <= counter(27 downto 24);
schematic:
counter_27 ------------ led_3
counter_26 ------------ led_2
counter_25 ------------ led_1
counter_24 ------------ led_0
counter_23 ------
....
counter_0 ------
the real question:
why did you need to ask?
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 137839Hi, the first question to clear is what the card is doing all this time. A good example design will lead the LTSSM (link training sequence state machine) status bits out to ports for observation. I haven't looked at the Xilinx core closely, but I know the Lattice examples do. If you hang a logic analyzer on these ports you can observe the sequences the state-machine is going through. How they are coded should be in the Xilinx documentation. The transitions here aren't particularly fast so an 'entry level' LA will probably do the job. If the LTSSM doesn't finally reach the L0 state, you have a problem. Data-Link layer 'DL_UP' is usually a separate signal. If that isn't set, you also have a problem. Basically the physical layer and data-link layers in the PCIe core must be active before you can do anything with it. It is conceivable that if there are problems here, your BIOS or OS loading phase could lock up. I've seen it before. Problems could be EMC related, board design etc. Another test I recommend is sticking the card in a Linux machine. If you don't have a linux machine it may well be ok to just boot from a Ubuntu DVD you can pick up in a magazine somewhere. You don't necessarily have to install it. If the card is recognisable you can see the complete configuration space header by logging in as root and typing lspci -vvv (You typically see less info if you don't log in as root) If that works and your using windows (you didn't say, I'm just assuming) your problem could well be driver related. By the way, in case you are not aware, a x8 card plugged in a x16 slot can end up working only as a x1 link. The PCIe spec allows this. Support for x2/x4/x8 configurations is optional. But this should not have anything to do with your problem. Good luck, Massi schrieb: > Hi everyone, I'm trying to program a Xilinx Virtex 5 (on Avnet PCI > Express Development Kit board). I downloaded the bistream generated by > the PIO example design which comes up with the PCI core (endpoint > block 1.9) but when I reboot the system in order to recognize the > board, the PC hangs forever. Do you have any idea about what it could > depend on? By the way, the board is a x8 lane, but it is plugged in a > x16 lane slot. > > Thanks in advance.Article: 137840
On Sat, 31 Jan 2009 02:16:42 -0800 (PST), GrIsH <grishkunwar@gmail.com> wrote: >I have two modules counter(28-bit) and led decoder(takes 4-bit >input)....i want to display the value of counter through seven segment >display(SSD). so my interest is to connect upper 4-bit of counter to 4- >bit input of led decoder so that change in display on SSD can be seen >easily ......i am using the board XSA-50 whose clk is 50 Mz so by >using 4-bit counter,its value will be changed so fast that we can not >visualize the value in seven segment display.... > >Some have any idea on it??......any idea will be greatly >appreciated.... I'm not sure what the question is because what you seem to be asking is trivial ie connecting top 4 bits of the bus to the led decoder inputs. Another poster gave you all the possible solutions so I won't repeat them here. If on the other hand you're really asking how you can make the digits stable while the counter is running then that's really not possible. At 50 MHz (20ns) the MSB of the counter toggles at around 2 seconds and LSB of the 4 bits you're looking at toggles at around 250 ms which I agree would be difficult to see. If you want to see the numbers clearly you have no choice to get either a slower clock speed or faster eyes. On the other hand, you can implement some capture logic and sample the value of the counter with an external signal which would give you stable values but not continuous change. You need to decide why you are looking at the counter. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 137841
well, if you understand the difference then please let me know. But if you don't, then don't pretend to be "Abo El3oreef" -- translates to: a person who pretends to be knowledgeable while he don't know anything! rickman wrote: > On Jan 30, 9:27=A0pm, abbas <xfiles.detec...@gmail.com> wrote: > > Hi all > > > > I was wondering what is the design for the lookup tables of the logic > > blocks in FPGAs such as the Virtex model from Xilinx? Does they use > > pass transistors as most of the academic papers show? or does they use > > transmission gates? Please provide reference if possible. > > > > Thanks. > > If you understand the difference between pass transistors and > transmission gates, then you should be able to figure this out for > yourself. > > RickArticle: 137842
Its the weekend, so no programming until after the super bowl. I deserve a break. One of my hobbies is a craft called paper modeling and by chance a brand new model came out almost at the exact time that my efforts to learn VHDL went into high gear. The irony of these two events struck me. The model is the character 'bit' from the movie "Tron": http://tektonten.blogspot.com/2009/01/tron-papercraft-bit.html and I'm looking forward to having these models on the mantlepiece of my office. I think they are very appropriate for this group.Article: 137843
Hi according to the screenshot here http://www.actel.com/products/software/smartdesign/default.aspx it seems that CoreABC can be used in Libero, but when trying to add a CoreABC instance it asks for CoreConsole to be installed and configured. and if that is done, then it will forget some of the connections made and if that project is closed and reopened then it says that in need to upgrade coreconsole design to new smart design flow, but then it says that the conversion is not supported for CoreABC CoreABC should be simple as A B C! But all attempts to use it with lates Libero version seem to fail AnttiArticle: 137844
On Jan 31, 8:53=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > according to the screenshot herehttp://www.actel.com/products/software/sm= artdesign/default.aspx > > it seems that CoreABC can be used in Libero, > but when trying to add a CoreABC instance it asks for CoreConsole to > be installed and configured. > and if that is done, then it will forget some of the connections made > and if that project is closed and reopened then it says that in need > to upgrade coreconsole design > to new smart design flow, but then it says that the conversion is not > supported for CoreABC > > CoreABC should be simple as A B C! > But all attempts to use it with lates Libero version seem to fail > > Antti issue solved. the stupid user always tries the one combination first that doesnt work. the problem seems to be that the minimum number of APB slaves is 2 ! trying to build a system with only one APB peripheral leads to different errors.. Antti has solved his own problemArticle: 137845
Hi Adam... I am not using flash for the nios program- all the SW is located at an internal ram.... :) GuyArticle: 137846
On Jan 31, 1:02=A0pm, maher <xfiles.detec...@gmail.com> wrote: > well, if you understand the difference then please let me know. But if > you don't, then don't pretend to be "Abo El3oreef" -- translates to: a > person who pretends to be knowledgeable while he don't know anything! Are you asking what the difference is or are you just being rude? This is the sort of stuff that can be figured out with a simple google search. Every question asked here does not have to be answered here. Search on "transmission gate vs pass transistor" and look at the first link displayed. RickArticle: 137847
On Jan 31, 4:36=A0pm, rickman <gnu...@gmail.com> wrote: > On Jan 31, 1:02=A0pm, maher <xfiles.detec...@gmail.com> wrote: > > > well, if you understand the difference then please let me know. But if > > you don't, then don't pretend to be "Abo El3oreef" -- translates to: a > > person who pretends to be knowledgeable while he don't know anything! Sorry if you understand my reply in a wrong way. I just replied the same way you replied my original message! > > Are you asking what the difference is or are you just being rude? > > This is the sort of stuff that can be figured out with a simple google > search. =A0Every question asked here does not have to be answered here. > Back to my original question: I don't ask what is the different between transmission gates and pass gates; I know exactly what the difference is. What I am asking about (as specified in my first post, sorry I changed my nick name from "abbas" to "maher") is the circuit level design of lookup tables in commercial FPGAs such as Vitretx-II pro from Xilinx. Simply, this is my question. I would be grateful to those who can reply and provide references. > Search on "transmission gate vs pass transistor" and look at the first > link displayed. > > RickArticle: 137848
abbas wrote: > I was wondering what is the design for the lookup tables of the logic > blocks in FPGAs such as the Virtex model from Xilinx? I would use a block ram as a ROM. The "design" would be a vhdl or verilog code template something like this: http://mysite.verizon.net/miketreseler/sync_rom.vhd -- Mike TreselerArticle: 137849
On Jan 31, 7:56=A0pm, maher <xfiles.detec...@gmail.com> wrote: > On Jan 31, 4:36=A0pm, rickman <gnu...@gmail.com> wrote: > > > On Jan 31, 1:02=A0pm, maher <xfiles.detec...@gmail.com> wrote: > > > > well, if you understand the difference then please let me know. But i= f > > > you don't, then don't pretend to be "Abo El3oreef" -- translates to: = a > > > person who pretends to be knowledgeable while he don't know anything! > > Sorry if you understand my reply in a wrong way. I just replied the > same way you replied my original message! > > > > > Are you asking what the difference is or are you just being rude? > > > This is the sort of stuff that can be figured out with a simple google > > search. =A0Every question asked here does not have to be answered here. > > Back to my original question: I don't ask what is the different > between transmission gates and pass gates; I know exactly what the > difference is. What I am asking about (as specified in my first post, > sorry I changed my nick name from "abbas" to "maher") is the circuit > level design of lookup tables in commercial FPGAs such as Vitretx-II > pro from Xilinx. Simply, this is my question. I would be grateful to > those who can reply and provide references. A transmission gate is a lot bigger, requiring two pass transistors and an inverter to drive the complemented one. A simple pass transistor will do nicely for nearly any digital signal gating. A transmission gate is typically used for analog signals where you need the resistance to remain relatively constant. A simple pass transistor has a variable resistance as the input voltage changes... ok for most digital stuff, but not so good for analog. I think if you actually understood the difference, you would understand why transmission gates are not used in FPGAs. These parts are all about density and pass transistors are used both for route switching and in the LUTs for the output mux from the memory elements (a RAM is just memory elements with their outputs muxed together.) What did you find when you searched on Google? Rick
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z