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I think I see what's wrong . . . "J. Boss" wrote: > Warning: unconnected input and output pins detected > Unconnected output pin: D1 ($I1) > Unconnected output pin: D10 ($I1) > Unconnected output pin: D11 ($I1) > Unconnected output pin: D12 ($I1) > Unconnected output pin: D13 ($I1) > Unconnected output pin: D14 ($I1) > Unconnected output pin: D15 ($I1) > Unconnected output pin: D2 ($I1) > Unconnected output pin: D3 ($I1) > Unconnected output pin: D4 ($I1) > Unconnected output pin: D5 ($I1) > Unconnected output pin: D6 ($I1) > Unconnected output pin: D8 ($I1) > Unconnected output pin: D9 ($I1) > You are using an incorrect IOPAD. You should use IOPAD16. Note that nowhere in this warning does it mention ... Unconnected output pin:D0 ($I1) This is because the IOPAD (a single wire, not a bus) has connected itself to only one line on the D[15:0]. However, it is a little unusual that it didn't connect to D15.Article: 22651
Hi i'm quite new in FPGA and CPLD world. I have to design a board with address decoding and a few event counters (16 bit counters) interfaced with an PC104 bus. Is it better to use CPLD or FPGA? Why? Thanks SimonArticle: 22652
I have a board that I would like to put a single digit indicator on. It is multi-layer and the opposite side is very busy. Has anyone come across a surface mountable part? Thanks in advance, Arnold BelandArticle: 22653
All, I'm trying an in system program of a CPLD (okay off topic, but I thought I would ask anyway) and the Xilinx jtag programmer software is looking for xc9536.adr. Where do I get this file????? We have Alliance 2.1i and the latest service packs. Where does this file come from??? I looked in /xc9500/data and we just have bsd files in there... Any thoughts? TomArticle: 22654
Forget it......I found them......all is well. TomArticle: 22655
It is a bit of a toss up, but you would likely find it easier to use a CPLD because you won't have to worry with loading the design on powerup. This can be a problem when you are using the chip as your main address decoder. It can't decode accesses to itself until it is booted up and it needs to be accessed to be booted! If your counters are not too large, you can fit your design in a small to medium CPLD with 64 to 128 macrocells. These parts come in ISP or Flash versions to facilitate reprogramming after being installed on the board. Simon Bilodeau wrote: > Hi i'm quite new in FPGA and CPLD world. > > I have to design a board with address decoding and a few event counters (16 > bit counters) interfaced with an PC104 bus. > > Is it better to use CPLD or FPGA? Why? > > Thanks > > Simon Rick Collins Arius, Inc rick.collins@XYarius.com Remove the XY to email me. The reply to address is not valid.Article: 22656
Hi, in general FPGA have lot's of FF and "limited" logic before the FF's (e.g. LUT of 4-1). CPLD on the other hand have few FF and lot's of logic before the FF's. from the very limited thing you wrote I would guess you can do it with almost any device out there, and my guess is that pld will be better solution. one thing you might want to consider is while you might be able to fit your design into a 16 FF pld, if there is a chance you would like to add more thing in the future maybe a pld with few extra FF is more advisable , maybe something like a 32 FF pld solution. also in some cases you might choose from the begining a package that will enable you to do "upgrade" in same footprint. have a nice day Illan In article <9qhU4.91$3F3.1719@wagner.videotron.net>, "Simon Bilodeau" <simon.bilodeau@htrc.com> wrote: > Hi i'm quite new in FPGA and CPLD world. > > I have to design a board with address decoding and a few event counters (16 > bit counters) interfaced with an PC104 bus. > > Is it better to use CPLD or FPGA? Why? > > Thanks > > Simon > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22657
In comp.arch.embedded Arnold Beland <acbel@brookings.net> wrote: > I have a board that I would like to put a single digit indicator on. It is > multi-layer and the opposite side is very busy. Has anyone come across a > surface mountable part? Yes, there is at least one part that is a lead-formed version of a through hole part (it's a dual 0.4" high), and some very, very expensive Japanese parts that are also extremely thin. I don't know where to get them in small (< 1K pcs) quantities, though. Best regards, -- =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Spehro Pefhany --"it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com Contributions invited->The AVR-gcc FAQ is at: http://www.BlueCollarLinux.com =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=Article: 22658
Arnold Beland wrote: > > I have a board that I would like to put a single digit indicator on. It is > multi-layer and the opposite side is very busy. Has anyone come across a > surface mountable part? Have you completely ruled out seven individual LED lamps in the appropriate pattern? No, it's not as nifty as a real display made of bars, but it *is* readable. Tim.Article: 22659
Who is the manufacturer and what part is it? I have also been looking for this (I need >10K EAU). Dave Miller "Spehro Pefhany" <speff@interlog.com> wrote in message news:Q8jU4.11555$f12.266717@news1.rdc1.on.wave.home.com... > In comp.arch.embedded Arnold Beland <acbel@brookings.net> wrote: > > I have a board that I would like to put a single digit indicator on. It is > > multi-layer and the opposite side is very busy. Has anyone come across a > > surface mountable part? > > Yes, there is at least one part that is a lead-formed version of a through > hole part (it's a dual 0.4" high), and some very, very expensive Japanese > parts that are also extremely thin. > > I don't know where to get them in small (< 1K pcs) quantities, though. > > Best regards, > -- > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- = > Spehro Pefhany --"it's the network..." "The Journey is the reward" > speff@interlog.com Info for manufacturers: http://www.trexon.com > Embedded software/hardware/analog Info for designers: http://www.speff.com > Contributions invited->The AVR-gcc FAQ is at: http://www.BlueCollarLinux.com > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- =Article: 22660
JX wrote: > > Hi, All, > > My supervisor ask me to design some USB inferace with > FPGA, where can I find any resource to implement that? > > Thanks a lot! > Jesse you could try http:\\www.usb.org --Lasse (+)--------------------------(+) | Lasse Langwadt Christensen | | Aalborg, Denmark | (+)--------------------------(+)Article: 22661
Andy Holt wrote: > snip > Furthermore, it appears that the price from amazon.co.uk is considerably > less than that from amazon.com (how odd!) snip > and as long as you are in the EU buying from amazom.co.uk and not amazon.com will have the addionation advantage that you don't have to pay the extra tax etc. as you have to if you buy from amazon.com :) --Lasse (+)--------------------------(+) | Lasse Langwadt Christensen | | Aalborg, Denmark | (+)--------------------------(+)Article: 22662
Douglas,
Tiockp is the relevant time for outputs clocked in the IOB. It's the time
from clock edge at the IOB K pin to output pad valid, but you do need to
take the adjustments into account for drive strength, slew rate, and I/O
type.
Tioop is for outputs which are not clocked in the IOB. It's the time from
the IOB O pin to output pad valid, but you'd need to add the delay getting
to the IOB O pin, which includes routing delays and CLB delays.
Pin-to-pin output parameters are, paraphrased, "what's the delay from the
clock input pad to an output pad whose IOB is clocked?" If you use a DLL,
the internal clock net is delayed 0ns (that's zero ns) from the input clock
pad, so the delay from the clock pad is the same as the delay from the
internal clock net, i.e. Tiockp. (Okay, purists, the former is 0.2ns greater
than the latter, worst case, which is probably due to the delay through the
IBUFG.) If you don't use a DLL, there's an additional delay from the clock
pad through a global clock buffer to the internal clock net--the DLL is
useful because it compensates for this delay.
If you're clocking your outputs at the IOBs and you're using a DLL, I think
the Tickofdll is the relevant parameter, with adjustments. If you're not
using a DLL, then use Tickof.
If you're not clocking your outputs, you'll need to implement your design to
get the correct timing, which the timing analyzer provides (you won't need
to know or care about Tioop). But that's rather risky, because routing
delays can easily dwarf the 3-5ns Tickof, and a preliminary design which
shows promising timing could turn into a final design with bad timing.
The safest approach, if you can justify it, is to assume you can't use a
DLL, design with Tickof, and then go ahead and use the DLL.
Marc
Article: 22663You'll want to put light pipes over those if you do. I think Optrex has them. Tim Shoppa wrote: > Arnold Beland wrote: > > > > I have a board that I would like to put a single digit indicator on. It is > > multi-layer and the opposite side is very busy. Has anyone come across a > > surface mountable part? > > Have you completely ruled out seven individual LED lamps in the > appropriate pattern? No, it's not as nifty as a real display > made of bars, but it *is* readable. > > Tim. -- P.S. Please note the new email address and website url -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 22664
Hello, I am a *very* new user to this FPGA stuff and I am using the schematic capture feature in Altera MAX+Plus II 9.6 Baseline for my design and have the following questions: 1) I need some custom D and T flip-flops - by custom I mean that I want some with ENABLE, some with CLEAR, some with PRESET and various combinations of the above, all with programmable polarity and programmable clock polarity too. I cannot seem to find a way to take the generic D/T flip-flop and modify it for my needs. Is this possible? Or am I stuck with using inverters and tying the unused inputs of the f/f's to Vcc/GND as appropriate? I really do not want to use any LPM stuff for this. 2) I am using the LPM module for my custom multiplexer and demux modules and when the module is placed on the sheet, two boxes show up - one with the mux/demux itself and one on the upper right hand corner with the mux/demux specifications (width, etc.). Is there a way to turn off or hide this annoying specification box? And is there a way to move this box without moving the mux/demux symbol too? 3) Is there a way create "bubbles" (for inversion) at the input of logic gates? There are gates with these bubbles on *all* the inputs, but I want to be able to place these inverters on just some of them. I like the bubble scheme instead of actual NOT gates since it saves space on the schematic. Thank you for your time! AshokArticle: 22665
Check out Associated Professional Systems (http://www.associatedpro.com). "Jean-Luc Nagel" <jean-luc.nagel@imt.unine.ch> wrote in message news:3921610D.2219F214@imt.unine.ch... > Hello, > > I'm looking for a FPGA prototyping board with a PCI > interface, but also with a PC104+ interface (i.e. PCI PC104) > > So far I found only a PC104 (ISA) board for prototyping from > nova-engineering (http://www.nova-eng.com/). > > > Thank you in advance, > Jean-Luc >Article: 22666
"James T. White" wrote: > Check out Associated Professional Systems (http://www.associatedpro.com). Thank you for your answers. Unfortunately they have only PC104 boards and no PC104+...Article: 22667
Hi, I do not know at the moment of any tool which goes directly from C input to an FPGA Edif netlist. You need first to go from C to VHDL RTL code and then from there on to the edif netlist: At the moment I am using the following set of tools for this flow A|RT Designer Pro (http://www.frontierd.com) for the C to VHDL translation Leonardo Spectrum (http://www:exemplar.com) for the C to EDIF netlist translation Modelsim (http://www.model.com) for simulation For the last two steps there are alternatives. m_rajanikant@my-deja.com wrote in message <8fq6ke$jcl$1@nnrp1.deja.com>... >Hi, >I heard of a C to FPGA netlist complier, Can someone tell me where I >can find this > >Thanks >Raj, ASU > > > >Sent via Deja.com http://www.deja.com/ >Before you buy.Article: 22668
If there is no space for holes but height is not so important, why don't you use SMT-DIP sockets and 7seg displays that fit into an DIP14? Would be much cheaper (I think) than any of these special SMT devices an should be available even in single quantities. Regard, Jens Spehro Pefhany wrote: > > In comp.arch.embedded Arnold Beland <acbel@brookings.net> wrote: > > I have a board that I would like to put a single digit indicator on. It is > > multi-layer and the opposite side is very busy. Has anyone come across a > > surface mountable part? > > Yes, there is at least one part that is a lead-formed version of a through > hole part (it's a dual 0.4" high), and some very, very expensive Japanese > parts that are also extremely thin. > > I don't know where to get them in small (< 1K pcs) quantities, though. > > Best regards, > -- > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= > Spehro Pefhany --"it's the network..." "The Journey is the reward" > speff@interlog.com Info for manufacturers: http://www.trexon.com > Embedded software/hardware/analog Info for designers: http://www.speff.com > Contributions invited->The AVR-gcc FAQ is at: http://www.BlueCollarLinux.com > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=Article: 22669
In article <Q8jU4.11555$f12.266717@news1.rdc1.on.wave.home.com>, Spehro Pefhany <speff@interlog.com> writes >In comp.arch.embedded Arnold Beland <acbel@brookings.net> wrote: >> I have a board that I would like to put a single digit indicator on. It is >> multi-layer and the opposite side is very busy. Has anyone come across a >> surface mountable part? > >Yes, there is at least one part that is a lead-formed version of a through >hole part (it's a dual 0.4" high), and some very, very expensive Japanese >parts that are also extremely thin. > >I don't know where to get them in small (< 1K pcs) quantities, though. > >Best regards, www.flint.co.uk -- Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031, Gerald Coe | .demon.co.uk | 68302, 64180, 80C188EB cpu modules. http://www.devantech.demon.co.uk | Full custom uP control systems designed.Article: 22670
Arnold Beland wrote: > > I have a board that I would like to put a single digit indicator on. It is > multi-layer and the opposite side is very busy. Has anyone come across a > surface mountable part? Try a GAL16V8 in a 20-pin PLCC package.Article: 22671
Paul Burke wrote: > > Arnold Beland wrote: > > > > I have a board that I would like to put a single digit indicator on. It is > > multi-layer and the opposite side is very busy. Has anyone come across a > > surface mountable part? > > Try a GAL16V8 in a 20-pin PLCC package. Wow, you mean if I pump enough current through some of those pins that the GAL16V8 will visibly glow? Cool! And I thought NED's (Noise Emitting Diodes) were a neat idea! Tim.Article: 22672
In sci.electronics.design Tim Shoppa <shoppa@trailing-edge.com> wrote: > Wow, you mean if I pump enough current through some of those pins > that the GAL16V8 will visibly glow? Cool! Maybe if it's one of the ones with the quartz window you could make a digit with the glowing bonding wires? I don't think the shape is right though. Best regards, -- =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Spehro Pefhany --"it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com Contributions invited->The AVR-gcc FAQ is at: http://www.BlueCollarLinux.com =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=Article: 22673
Patrick, You could try the Ballyinx board from Nallatech (http://www.nallatech.com/dime/ballyinx/index.htm) which can provide up to a V800, if that is enough, directly to the PCI64/66 Bus, with expansion DIME slots that can take a range of modules. One of these modules has dual XCV1000s so you could put an additional 4 x XCV1000 onto the card if needed. The Ballyinx is the reference card Xilinx uses for the PCI64/66 Logicore so it can handle you need for using their core. Malachy > -----Original Message----- > From: Patrick Schulz [mailto:schulz@rumms.uni-mannheim.de] > Posted At: 10 May 2000 09:58 > Posted To: fpga > Conversation: appropriate ASIC Prototyping Board > Subject: appropriate ASIC Prototyping Board > > > Hi all, > > we are targeting an PCI-based network interface ASIC > prototype on VIRTEX1000(E), > but I found only very few boards which meet our requirements > (PCI_64, VIRTEX1000(E)). > One of this is the DN2000k10 from the Dini Group > (http://www.dinigroup.com). The problem > with this board is, that it is not compatible with the PCI > LogicCore from Xilinx and I'm > not willing to design a PCI-Interface. > > Does anyone has experience with this board? > Does anyone has an idea for a appropriate board?? > > Thanks Patrick > > -- > Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) > University of Mannheim - Dep. of Computer Architecture > 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de > Phone: +49-621-181-2720 Fax: +49-621-181-2713 >Article: 22674
John, You could try the Ballynuey card from Nallatech (http://www.nallatech.com/dime/ballynuey2/index.htm). This card has 4 DIME slots which can take a range of modules including one of the modules which has dual FPGAs (the Ballyblue), this would allow you to scale the card with the number of FPGAs that you require. Malachy > -----Original Message----- > From: John Fielden [mailto:john.fielden@abcmotorola.com] > Posted At: 11 May 2000 23:33 > Posted To: fpga > Conversation: Reccomend an ASIC emulation board > Subject: Reccomend an ASIC emulation board > > > I need a multi FPGA board to do ASIC verification. So far, > I've looked at > WildStar (by Annapolis Micro) and RSPE (by Viasat). > > Can anyone reccomend another board I should look at? > > Thanks, > > John > >
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