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It seems like every time there's a question on Xilinx hard macros on this board, there's a lot of problems. But here it goes anyway: I'm doing a PAR for a small-sized "psuedo-dsp", which is used multiple times in a larger design. I'm trying to make it into a hard macro for those multiple instantiations. The big problem I'm having is in FPGA editor, how do you rename all the external macro pins, if there are literally hundreds of them? I couldn't figure out a way to automate the process, since the editor uses the actual component pin names (not the instance names). Another issue - How do you connect the clock net (in my case, fanout of 1000+) to one single external macro pin? (External macro pins are applied to pins, not nets) This problem comes up with any net with a huge fanout. Any help greatly appreciated, thanks. FrankArticle: 60576
> > The solution seems promising, what kind of wireless technology can be > used ? can I use 802.11 or blue tooth or any other. > Whatever you can find a USB device for. 802.11 and blue tooth should both work. You might have problems getting documentation on how to program these devices though. I would suggest starting with one that has Linux drivers. Those usually have open documentation and the Linux driver source is always a good starting point for questions. Regards, Andras TantosArticle: 60577
I did a quick & dirty project based on the OpenCores USB 1.1 design and drove the D+ and D- pins straight from the FPGA. I wasn't concerned about strict compliance to the USB spec... I got the project to work fine, but I only tried it on a couple of computers. Different USB hosts might complain about the direct D+ D- interface. I did have to do some mods to the OpenCore USB design. As I looked though it I found some things I was not real happy with. There was no problem meeting timing with the Xilinx Spartan-2 chip I used. John Providenza "Ken Land" <kland1@neuralog1.com> wrote in message news:<vme5iv66sv911@news.supernews.com>... > Is it free? :) > > That is very interesting and that is what I went looking for. I imagined > the logic in the FPGA would wiggle D+ and D- appropriately. I understand > that the 480Mbps of 2.0 might be tough in a garden variety FPGA, but 1.1 > might be doable. > > I wonder if the special LVDS pins of a Cyclone or Stratix would do 2.0? Of > course going to Stratix would negate any BOM savings. > > Ken > > "Antti Lukats" <antti@case2000.com> wrote in message > news:80a3aea5.0309152348.5ffd5049@posting.google.com... > > "Kenneth Land" <kland1@neuralog1.com> wrote in message > news:<vmcl99c2s5jgc0@news.supernews.com>... > > > Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > > > > > > I looked very closely at the 1.1 version and found it took only 6 pins > and > > > $1.75 transceiver chip. > > > > > > Ken > > > > there is a japanese design (VHDL, and Visual basic host example) > > that uses no tranceiver at all, ie USB DM,DP directly to FPGa > > > > anttiArticle: 60578
> PJ wrote: > > > Hello, > > > > I am implementing a 128 point real Radix-2 fft, data and coefficient > > widths are 16 bit. > > I am synthezising it for use in an FPGA. However, it is taking a very > > long time to synthesize. (approx 3 days using Leonardo on a 2 GHz > > machine with 512 MByte RAM) I am using a 20K1000 Altera FPGA. The ram > > required by the fft will be internal to the FPGA Hiya, I have noted with some synthesizers that if it cannot infer your RAM "correctly" it will try to build it out of registers (as opposed to the dedicated RAM on the FPGA). This can end up taking a _very_ long time for only reasonably large RAMs. You might consider synthesizing each module in your design separately until you find the part that causes the problem. If it isn't already structured thus it might be wise to do so as this may also help. Later, Andyman.Article: 60579
> Wow, microblaze has a forum?!? I sure wish Altera would take a que and do > the same for Nios. Why not bypass Altera and start a yahoo group for the Nios? SteveArticle: 60580
John Providenza <johnp3+nospam@probo.com> wrote: : I did a quick & dirty project based on the OpenCores USB 1.1 : design and drove the D+ and D- pins straight from the FPGA. : I wasn't concerned about strict compliance to the USB spec... : I got the project to work fine, but I only tried it on a couple : of computers. Different USB hosts might complain about the : direct D+ D- interface. : I did have to do some mods to the OpenCore USB design. As I looked : though it I found some things I was not real happy with. There was : no problem meeting timing with the Xilinx Spartan-2 chip I used. Do you plan to contribute the mods back? It would be appreciated... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 60581
John, That's pretty cool. I might try it some day after I get some more experience under my belt. My problem was that I needed an fpga IP solution at an OTS price and reliability, but all I found were extremes. Either the core was "free" and not guaranteed fully compiant or the price was sky high. So I wound up sticking with my old reliable NetChip @ $8. Ken "John Providenza" <johnp3+nospam@probo.com> wrote in message news:349ef8f4.0309161316.62c75235@posting.google.com... > I did a quick & dirty project based on the OpenCores USB 1.1 > design and drove the D+ and D- pins straight from the FPGA. > I wasn't concerned about strict compliance to the USB spec... > > I got the project to work fine, but I only tried it on a couple > of computers. Different USB hosts might complain about the > direct D+ D- interface. > > I did have to do some mods to the OpenCore USB design. As I looked > though it I found some things I was not real happy with. There was > no problem meeting timing with the Xilinx Spartan-2 chip I used. > > John Providenza > > > "Ken Land" <kland1@neuralog1.com> wrote in message news:<vme5iv66sv911@news.supernews.com>... > > Is it free? :) > > > > That is very interesting and that is what I went looking for. I imagined > > the logic in the FPGA would wiggle D+ and D- appropriately. I understand > > that the 480Mbps of 2.0 might be tough in a garden variety FPGA, but 1.1 > > might be doable. > > > > I wonder if the special LVDS pins of a Cyclone or Stratix would do 2.0? Of > > course going to Stratix would negate any BOM savings. > > > > Ken > > > > "Antti Lukats" <antti@case2000.com> wrote in message > > news:80a3aea5.0309152348.5ffd5049@posting.google.com... > > > "Kenneth Land" <kland1@neuralog1.com> wrote in message > > news:<vmcl99c2s5jgc0@news.supernews.com>... > > > > Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? > > > > > > > > I looked very closely at the 1.1 version and found it took only 6 pins > > and > > > > $1.75 transceiver chip. > > > > > > > > Ken > > > > > > there is a japanese design (VHDL, and Visual basic host example) > > > that uses no tranceiver at all, ie USB DM,DP directly to FPGa > > > > > > anttiArticle: 60582
Anyway, I would rather reduce by a factor of 2 the releases and service packs, if this reduce the bugs. Tullio On Tue, 16 Sep 2003, rickman wrote: > > Don't be surprised about the service packs. The "features" that are > part of each release are planned well in advance. When bugs are > encountered, they priortize them and only fix the "critical" bugs prior > to release. The lesser bugs and other features are then planned into > later releases, again according to priority. > > A conversation I had with a Xilinx person indicated that they have bug > fixes and new features planned at least two service packs ahead. I > think it is pretty good that Xilinx was able to release the first > service pack so soon. To me this shows that they did a good job of > triage, planning and execution on both the 6.1 release and the first > service pack. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX > ---------Article: 60583
rickman wrote: > Lasse Langwadt Christensen wrote: > >>Antti Lukats wrote: >> >>>"Kenneth Land" <kland1@neuralog1.com> wrote in message news:<vmcl99c2s5jgc0@news.supernews.com>... >>> >>> >>>>Have you looked at the USB 1.1 and 2.0 IP Cores at www.opencores.com? >>>> >>>>I looked very closely at the 1.1 version and found it took only 6 pins and >>>>$1.75 transceiver chip. >>>> >>>>Ken >>> >>> >>>there is a japanese design (VHDL, and Visual basic host example) >>>that uses no tranceiver at all, ie USB DM,DP directly to FPGa >>> >>>antti >> >>I've thought about that, two pins programmed for 3V3-cmos should be good >>for tx and rx of SE0 but I never got around to checking if one of the >>differential standards on the FPGA would be within spec for USB? >> >>-Lasse > > > It has been awhile since I looked at the USB spec, but I seem to recall > that there is a non-standard state that is used to signal the rate or > some other aspect of the interface. I want to say this state is both > signals high or both low at the same time. Am I out to lunch on this? > > If there is a non-standard state on these pins, you would not be able to > use an LVDS driver. You would need two independant outputs. > single ended zero (SE0) is both both pins low and afair you have to both detect and generate that, my idea was to use two standard cmos IO's for that and wire a diffential set in parallel. -LasseArticle: 60584
Hi Ray/Andyman, Thanks for replying. Ray .... Is there a good explanation on radix-4 ffts ? If I can mod the code quickly, I will certainly do it. As regarding shared hardware, I thought about that when implementing my design, but I really couldn't figure out a way to do it. Are you talking about reducing the number of stages ? Did you use RAM to provide the hardware sharing ? I have let the synthesis tools generate the multiplier. I just used the '*' function. This is one area I think I could make good space saving. I have seen your articles about multipliers on your website. Would a DA type multiplier save me much space ? What is the most efficient multiplier in terms of flop count, and is there VHDL code or verilog code available. I'll gladly write it myself, if I can get some pointers. I can trade speed for gate count. My problem now is the lack of time I have to get this project completed. Andyman I have implemented RAM in my design, and thankfully it synthesis to RAM fine. However in saying that...that is for very small designs. This certainly might be a problem. I am using leonardo spectrum, and will give synplify a try next. If you found any solutions...I would be glad to hear. Thank you both for your time and your replies. Good luck PJ Ray Andraka <ray@andraka.com> wrote in message news:<3F664CBB.86459E77@andraka.com>... > It very heavily depends on your implementation. The fact that it is > radix2 and > not radix 4 or higher tells me already that your implementation is not a > very > efficient one. A radix 4 kernel is very little added complexity over a > radix 2 > kernel and cuts the processing time and area considerable. Depending on > your > speed requirements and your design prowess, you can certainly fit a 128 > point > real-only FFT in a much smaller part than a 1M gate part. As your speed > requirements decrease, you can take advantage of iterative or shared > hardware > to reduce the gate count considerably. I did a 4096 point design in a > Xilinx > XCV1000 that does the complex transform in 68 us (the floorplan and a > brief > description are on the gallery page on my website). That one only > occupies > about 40% of the FPGA and includes some floating point stuff as well as > windowing multipliers and some other goodies. It takes intimate > knowledge > of the FPGA structure and of algorithms to achieve that level of density > (the customer called the design "a work of art"), but even a novice can > achieve a density/performance level of half that design with some > carefully > thought out design. > > PJ wrote: > > > Hello, > > > > I am implementing a 128 point real Radix-2 fft, data and coefficient > > widths are 16 bit. > > I am synthezising it for use in an FPGA. However, it is taking a very > > long time to synthesize. (approx 3 days using Leonardo on a 2 GHz > > machine with 512 MByte RAM) I am using a 20K1000 Altera FPGA. The ram > > required by the fft will be internal to the FPGA > > > > Will this design take up all the space on the device. From past > > experience, can someone give me an indication of what area of the > > device the fft will occupy. > > > > Surely if it takes up most of the device, then it will be too big, as > > I have other features to implement in the FPGA also !! > > > > Thank you > > PJ > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 60585
Hi folks, We're looking for a high density serial flash part to hold microblaze uclinux kernel and file system images. The problem with commodity serial flash parts (SST, Nexflash etc) seems to be that they aren't really available in high densities (~4 - 8 MB) yet. If someone can correct me on this then please do! Anyway I'm wondering if we could potentially use a Xilinx platform flash part to hold both an fpga configuration and "random data". I know about SystemACE, but we can't afford that many pins. For the same reason I don't want to use regular parallel flash parts. The idea is that the FPGA configures with a microblaze bitstream, contained in the BRAM is a small bootloader that then sucks the kernel and filesystem image (potentially several megabytes) out of serial flash, copies it into external memory, then off it goes. With the serial flash parts I've seen so far, we'd need at least 2 or 3 of them to fit everything we need (plus level translators since this has to share an IO bank with 2.5V DDR, whereas serial flash devices generally seem >2.8V). It would be lovely if we could just put an 8MB xilinx platform flash part on the board and use it to store both the configuration and our software images. Any thoughts? Thanks, JohnArticle: 60586
Can anyone tell me how to avoid redoing all the Nios block port connections whenever I edit the processor config? Whenever I add something to the Nios config in SOPC builder and update the block, all of my connections are broken and all I know to do is reconnect them one at a time manually. This takes quite awhile. Is there anyway to have the update preserve the existing connections? It seems to be based only on physical possition within the graphical editor which seems strange to me. Thanks, KenArticle: 60587
On 16 Sep 2003 13:34:32 -0700, alann@accom.com (Alan Nishioka) wrote: >Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<qoocmv4dr277d3hu3tem6qbik3ap5ju1g7@4ax.com>... >> Does anyone know what to do with the pin on V2P called "RSVD"? >> >> I guess I'm meant to leave it open, but I haven't found anything in >> the datasheet or the Xilinx answers database that says for sure. > >http://direct.xilinx.com/bvdocs/userguides/ug012.pdf >Table 5-1 page 345 in the Virtex II-Pro Platform FPGA User Guide says >RSVD Reserved pin - do not connect So it does! Thanks for that. Allan.Article: 60588
I just got the board yesterday and I am happy with it. Shipping was $28 US to Australia as for the customs when you order mention that problem and I think they can find a solution. "Sergio Tassinari" <xszyjk@yahoo.it> wrote in message news:bk71aj$mm2$1@stargate1.inet.it... > Hi all! > I'd like to buy an FPGA prototyping board and, > after some searches, I am oriented to the Digilent Digilab 2. > They sell directly, but I live in Italy, and I am a little > scared about customs and shipping fees. > > Is there anybody out there living in Europe that has bought > a board from Digilent? > How much did you pay for shipping and customs charges? > > Many thanks! > > Sergio Tassinari > >Article: 60589
I am interesting in the systemc's using on the simulation.But I can't find any literal about how to use systemc together with VHDL or Verilog. Anybody can help? Best Rgds. wosiqiuArticle: 60590
Hi There, Has anyone used this device before. I'm looking into USB communication with my FPGA device (Altera's Cyclone), using VB on PC side. I have found some documentation regarding this transreceiver, however the pdf is not in detail. Pls advice. CheersArticle: 60591
John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<bk841k$7hf$1@bunyip.cc.uq.edu.au>... > Hi folks, > > We're looking for a high density serial flash part to hold microblaze > uclinux kernel and file system images. The problem with commodity > serial flash parts (SST, Nexflash etc) seems to be that they aren't > really available in high densities (~4 - 8 MB) yet. If someone can > correct me on this then please do! sorry, I am waiting also for an FPGA with config loader from MMC card! not avail. systemace is nice. you could do systemace-mmc controller with some small fpga not as nice as systemace, but would work. using platform flash for linux image storge would be real tricky at least. might be theoreatically possible but you would need to use JTAG to get the data asmuch as I understand., or add small logic that disables the configuration of the FPGA and restart config, and 'fetch' the stuff 'appended' to bitstream this would be fast download. anttiArticle: 60592
Thanks a lot for all your replies! It seems to me that, while the shipping charges are obviously fixed, the customs ones are variable from country to contry... Anyway, though the customs fee are a lot of money, the total cost remains acceptable for a board like the one from Digilent. I think I'll buy it. Thanks again. Ciao, SergioArticle: 60593
Jon Elson wrote: > Hello, > > Has anyone bought anything from www.dragonsources.com? > I'm having trouble finding any distributor in the US that will sell > the XCS10-3PC84C (old, 5V Spartan) in less than 300 pc quantities, > or for less than $42 ea. These guys claim they have them for $12 > ea., but I don't know if they are for real. They are apparently > in China, or thereabouts. Farnell might have them in stock: http://www.farnell.comArticle: 60594
"John Williams" <jwilliams@itee.uq.edu.au> ha scritto nel messaggio news:bk841k$7hf$1@bunyip.cc.uq.edu.au... > It would be lovely if we could just put an 8MB xilinx > platform flash > part on the board and use it to store both the > configuration and our > software images. I think it's possible! You can store your custom code as it was a separate "firmware", like if you have a second FPGA attached. Then the platform flash will do the rest. Look at the app notes that show how to connect more than a FPGA to a configuration flash/PROM. -- LorenzoArticle: 60595
Hello Frank, you could try to automate the renaming process by using xdl (Xilinx Design Language). Convert your nmc file into an xdl (ASCII) file and run some script on it. Help can be found under: $Xilinx/help/data/xdl. Regards ChristianArticle: 60596
Hello Daniel, I'm sorry, I dont know how to constraint VCC sites, either. If you do partial reconfiguration Xilinx Answer Record 17622 maybe interesting for you. Xilinx discourages from using VCC sites to drive constants. Regards ChristianArticle: 60597
The 6.1i/6.1i SP1 unisim DCM model doesn't work in a simulation that works with the model included in 5.2i SP3. Has anyone else experience the same problem? What has been changed? Why is the model changed? /Patrik ErikssonArticle: 60598
Here is a solution that I can't yet find a hole in. Put a comparator on the output of the flip flop(ff1) and call its output "meta" comparator indicates meta when ff1 output is just above a logic 1 min down to just below a logic 0 max. now create the next flip flop when meta then ff2 = not ff2 (if ff1 is metastable its input was changing) else ff2 = ff1. ff2 will never be meta stable as long as timing for meta is met. We can now use ff1 in a state machine by creating a combinatorial signal that reflects what ff1 is doing or trying to do. when meta then ff1_meta_hard = ff2 else ff1_meta_hard = ff1. even if you don't shoot me down I don't expect thousands of comparators in Vertex 4! :-)Article: 60599
On Tue, 16 Sep 2003 11:19:13 -0700, "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote: >The Spartan-3 pinout tables are described in the Spartan-3 data sheet, which >also provides a direct link to a ZIP file containing all the ASCII text >tables. > >The Spartan-3 applications team slightly modified the text format to make it >easier to parse with a simple script. The individual .csv files in the zip file http://www.xilinx.com/bvdocs/publications/s3_pin.zip have *different* formats (numbers of columns, etc.). That means a parser must cope with a number of special cases, as well as handling the completely different format used for Virtex (etc.) parts. Is it possible to make all the formats the same? (This is a rhetorical question and doesn't require an answer.) Allan. [Currently modifying scripts to cope with the new "easier to parse" file formats. The new parser is much larger than the old one.]
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