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Theron Hicks <hicksthe@egr.msu.edu> schrieb in im Newsbeitrag: 384FD4C6.5CACADCA@egr.msu.edu... > FPGA (XCS05XL) PROM > DIN <----- DATA > CCLK -----> CLK > DONE -----> CE (Is this > direction correct?) Yes, it is. > INIT_bar -----> OE/reset_bar > > my guess for the other signals > > FPGA INPUTS OTHER SIGNALS > M0 ----- open circuit(??) > M1 ----- open circuit(??) Do not leave this pins open. The internal pull up resistors of approx 90k Ohms are not enough for supressing possible noise which may generate strange bevavior to the FPGA. Better pull it up with 4K7. I don't have worked with the XCS FPGAs for a longer time. So, I have forgotten the exact connectrions for some signal... except the M Signals. PS : The devices will boot proberbly using 2.2V, an XCS10XL and an ATMEL 17LV128. Once this was a design error mada by me .. but it worked :-) HolgerArticle: 19276
Andy Peters wrote: > > I suppose there is a problem naming the instances. My placer/router > >is the XACT6000 and there is no option to control the generation of > instance > >names in SDF file. Is there some config in Synopsys analyzer to make the > >names of instances compatible with the names of SDF? Or this problem needs > >another solution ? > > Have you compiled the Xilinx simulation libraries? All the VITAL libraries were analyzed and the .sim files were generated without any problem. And the simulation without backannotation is working fine, too. -- | Walter Soto Encinas Jr | | PhD Student | | IFSC / USP | | Brazil |Article: 19277
"F.Rodriguez" wrote: > > This is original message from the CAN LIST > > -- CANLIST message -- > > The European Space Agency has released the VHDL source code of the > prototype CAN controller core. Information can be found at the following > address: > > ftp://ftp.estec.esa.nl/pub/ws/wsd/CAN/can.htm Many, many thanks - I failed to find this by searching the ESA site. Jonathan BromleyArticle: 19278
If you are worried about the rise time of your PSU, you can hold off config until it has risen by holding INIT low... Dave Hawke. XilinxArticle: 19279
Hi,
I heard that there are now some benchmarks that are being used to
compare different FPGA architectures and that Media Bench was one of
them. Does anyone know where you can get this, or where other benchmark
suits that are geared toward FPGA's are? Thanks,
Tom Fry
University of Washington
zaphod@ee.washington.edu
Article: 19280This is a multi-part message in MIME format. --------------A53CEEECC5BE3831CCCD32A6 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Jan Gray wrote: > [ stuff about multiport SRAMS in FPGAs, concentrating on 3-port RRW ] > > * 2 2-port SRAMs and do the two RR accessses and the W access in one cycle. A 25% more area efficient implementation would use 1 2-port and 1 1-port. - John --------------A53CEEECC5BE3831CCCD32A6 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John L. Smith Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: John L. Smith n: Smith;John L. org: Visicom Imaging Products adr: 10052 Mesa Ridge Court;;;San Diego;CA;92121;USA email;internet: jsmith@visicom.com title: Principal Engineer tel;work: 858-320-4102 tel;fax: 858-?????? note: http://www.visicom.com/products/Vigra/index.html x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------A53CEEECC5BE3831CCCD32A6--Article: 19281
What's your chain topology? Do you have other devices in the chain? I have 2 GALs and 2 Max 7128A's and dont have problems under NT or Win98 with a ByteBlaster. How do the TCK,TMS and TDI look on a scope? Are you getting a good connect on the VCC pin? The JTAG interface powers from the Target VCC pin. I had a lot of problems with the Lattice isp cable, it was sensitive to parallel port timing, it would work on one system, only when it was daisy-chained through a Zip drive. I never got it work my NT system, using a Soyo motherboard. You might try putting a 1uf cap on TCK to slow it down, just to see if you are having a marginal setup problem with TMS and TDI. On Thu, 09 Dec 1999 00:00:46 -0500, Andrew Reddig <andyr@tekmicro.com> wrote: >Subject tells the story. We have started to have a lot of problems >lately programming Altera devices through JTAG. We have both a >"BitBlaster" (serial interface to JTAG port) and a ByteBlasterMV >(parallel port interface to JTAG). We have had a wide range of problems >on many different designs. > >The common thread is that the device fails to program and MAX-Plus >either reports that the device is unknown, not installed, JTAG chain is >bad, or else does an examine/program and then fails with verify errors. >In the latter case, we can often get exactly the same # of verify errors >each time. > >This happens with two different computers, a couple of different >versions of MAX-Plus, and both the BitBlaster and the ByteBlasterMV. It >also happens with both single EPLD systems and cards that have five >devices in a chain. > >The only common thread is that the problem seemed to start when we >started using MAX7000A's, although it sometimes happens with 7000S >devices as well. > >We've checked pinouts, clocks, signals; all look fine. We've tried >using the ByteBlasterMV with both 3.3V and 5V, no difference. We've >buzzed out the cables, tried terminating TCK, and nothing works. But, >every now and then, you can press "Program" 55 times and get it to work >on the 55th. Sometimes, you can program all 5 chips in a chain a few >times without complaint, then it starts failing again. > >Anybody seen this kind of thing? Any ideas? We're pulling our hair >out. > >Thanks for any suggestions.Article: 19282
Walter Soto Encinas Junior wrote in message <3850342F.803CC92C@icmc.sc.usp.br>... >Andy Peters wrote: > >> > I suppose there is a problem naming the instances. My placer/router >> >is the XACT6000 and there is no option to control the generation of >> instance >> >names in SDF file. Is there some config in Synopsys analyzer to make the >> >names of instances compatible with the names of SDF? Or this problem needs >> >another solution ? >> >> Have you compiled the Xilinx simulation libraries? > > All the VITAL libraries were analyzed and the .sim files were generated >without any problem. And the simulation without backannotation is working >fine, too. Nope, not them : the Xilinx unisim and simprim libraries. See: http://www.xilinx.com/techdocs/2561.htm for details. -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu The secret of Slurm is on a need-to-know basis.Article: 19283
Have you looked at the new XC1800 series FLASH (JTAG ISP) SPROM from Xilinx? "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:384FD4C6.5CACADCA@egr.msu.edu... | Can someone dirrect me to a specific ap note on how to connect a | configuration prom to a Spartan XCS05XL series FPGA. I would prefer to | avoid OTP devices. So far I have found information on the XC17S05. | This is, of course, a OTP device. I have only one FPGA and one EEPROM. | Based on that info I think that this is correct: | | FPGA (XCS05XL) PROM | DIN <----- DATA | CCLK -----> CLK | DONE -----> CE (Is this | direction correct?) | INIT_bar -----> OE/reset_bar | | my guess for the other signals | | FPGA INPUTS OTHER SIGNALS | M0 ----- open circuit(??) | M1 ----- open circuit(??) | PWR_DOWN_bar ----- held low until power is stable | | The data sheet on the Spartan configuration prom shows a reset input on | the FPGA but I can't find that in the data sheet (except for the one | generated in my design) so I assume that that is really the PWR_DOWN_bar | signal. In my case the power could come up comparitively slowly. (I am | note certain how long, but 50 mSec is only 3 full cycles at 60 Hz.) I | note that the ap notes talk about power supply rise time (1 to 3 volts) | being less than 50 mSec. Is there a _simple_ hardware work around for | this problem such as holding some pin(s) low? I would rather not switch | the FPGA power supply. | | Obviously the In-Circuit-Programable device would use some more signals | on the configuration PROM. What are they and how do I connect them? | Again specific examples would be greatly appreciated. I would rather | get this correct the first time. While I am at it what ISP device is | appropriate for the XCS05XL Spartan FPGA? As a second alternative a | reprogramable but not ISP device would be a second choice. Thanks so | much for your patience and help. |Article: 19284
This is a multi-part message in MIME format. --------------C6A4AF46111C2F39B9C3E945 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit My previous post was wrong, you can't build a 3-port 1-cycle RRW memory from just a 2-port and a 1-port. Both sub-RAMs have to be updated in the same cycle. John L. Smith wrote: > > Jan Gray wrote: > > > [ stuff about multiport SRAMS in FPGAs, concentrating on 3-port RRW ] > > > > * 2 2-port SRAMs and do the two RR accessses and the W access in one cycle. > > A 25% more area efficient implementation would use 1 2-port and 1 > 1-port. > > - John > > ------------------------------------------------------------------------ > > John L. Smith <jsmith@visicom.com> > Principal Engineer > Visicom Imaging Products > > John L. Smith > Principal Engineer <jsmith@visicom.com> > Visicom Imaging Products HTML Mail > 10052 Mesa Ridge Court Work: 858-320-4102 > San Diego Fax: 858-?????? > CA Netscape Conference Address > 92121 Netscape Conference DLS Server > USA > http://www.visicom.com/products/Vigra/index.html > Additional Information: > Last Name Smith > First Name John L. > Version 2.1 --------------C6A4AF46111C2F39B9C3E945 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John L. Smith Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: John L. Smith n: Smith;John L. org: Visicom Imaging Products adr: 10052 Mesa Ridge Court;;;San Diego;CA;92121;USA email;internet: jsmith@visicom.com title: Principal Engineer tel;work: 858-320-4102 tel;fax: 858-?????? note: http://www.visicom.com/products/Vigra/index.html x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------C6A4AF46111C2F39B9C3E945--Article: 19285
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Article: 19286
Walter,
It appears to be a naming style issue. Note that the SDF file does not have
the round braces on the 0 (ie COUNT(0) vs COUNT_0_) but the netlist does.
You'll probably need to modify your Synopsys script, ala:
/***********************************************************/
/* Need to set up name rules based on the language type */
/* prevents problems with sdf files */
bus_naming_style = "%s_%d"
bus_dimension_separator_style = "_"
define_name_rules PROASIC -allowed "A-Z a-z 0-9_" \
-first_restricted "_ 0-9" \
-last_restricted "_"
default_name_rules = PROASIC
You can force the new naming style after compilation and before writing out
your netlist with the following command.
change_names -h -rule PROASIC
Sorry for the Actel twist.
Walter Soto Encinas Junior <soto@icmc.sc.usp.br> wrote in message
news:385023E4.722A4379@icmc.sc.usp.br...
> Hi
>
> This is a question from a recent Synopsys user. I did a small
design
> to XC6200 using structural VHDL. I have the VITAL compatible library with
> XC6200 primitives (AND, OR, and so on).
>
> I analyzed this design for simulation. The high level
(behavioral)
> simulation works well. But I can't backannotate the design with the
timing
> parameters generated by the placer/router tool, for accurate gate-level
> simulation. These parameters are in SDF format, and looking into the
file,
> it makes sense. Look:
>
> (CELL
> (CELLTYPE "AND2B1")
> (INSTANCE COUNT_COL/COUNT_0_INI_1_C_MUX)
> (DELAY
> (ABSOLUTE
> (PORT I0 (9.476:9.476:9.476) (8.143:8.143:8.143))
> (IOPATH I0 O (0:0:0) (0:0:0))
> (PORT I1 (3.040:3.040:3.040) (3.575:3.575:3.575))
> (IOPATH I1 O (0:0:0) (0:0:0))
> ...
>
> When I read the design the messages are:
>
> # vhdlsim -fi_all -sdf_typ -sdf_top /tb_addr/c_addr -sdf addr.sdf
CFG_TB_ADDR
>
> **Error: vhdlsim,259:
> (SDF File: addr.sdf Line: 20) instance
> /TB_ADDR/C_ADDR/COUNT_COL/COUNT_0_INI_1_C_MUX not found.
>
> ... and a lot of messages about other instances
>
> Looking into the design tree, using vhdlsim, I found the path to
the
> cell shown above.
>
> # pwd
> /TB_ADDR/C_ADDR/COUNT_COL/COUNT(0)/INI/C_MUX
> # ls
> TIMINGCHECKSON MSGON TIPD_I1 I1
> VITALBEHAVIOR
> INSTANCEPATH TPD_I0_O TIPD_I0 I0 I1_IPD
> XON TPD_I1_O O WIREDELAY I0_IPD
>
> I suppose there is a problem naming the instances. My
placer/router
> is the XACT6000 and there is no option to control the generation of
instance
> names in SDF file. Is there some config in Synopsys analyzer to make the
> names of instances compatible with the names of SDF? Or this problem needs
> another solution ?
>
> Sorry for the long posting. But it is very, very important! Thanks
in
> advance.
>
> --
>
> | Walter Soto Encinas Jr |
> | PhD Student |
> | IFSC / USP |
> | Brazil |
Article: 19287Hi We have a board with 8 Altera MAX7000 CPLD's in the JTAG chain. Most of them are MAX7128A's and MAX7064A's with one MAX7256A. The devices work fine and I can program them successfully using the ByteBlaster. However, approximately every 10'th time I reprogram the MAX7256, it dies. It actually programs successfully, but them fails during the VERIFY phase. After this the ByteBlaster software can not see the JTAG chain anymore. Also, the MAX7256 temperature rises within seconds so that it is too hot to touch. Has anybody ever came across this? Any suggestions? I've check the layout and power supply and decoupling, it seems fine. Regards, Lourens ================================================================ Lourens Geldenhuys Tel: +27 (0)12 665 1480 Project Engineer Fax: +27 (0)12 665 1495 Mecalc (Pty) Ltd e-mail: lourens@mecalc.co.za 86 Oak Avenue, Highveld Technopark, Centurion, South Africa ================================================================Article: 19288
I want to implement distributed ROMs in a Virtex so I used COREgen (latest update) The docs say that the old .coe initialization files are supported. I still wonder why I got so many error messages... I then tried with .mif files. COREgen lets you choose the radix (binary or hex) used in these text files. Well... Choose whatever you want, it'll work only with binary radix files. Makes me want to throw all this junk through the window... Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 19289
Hello, I was wondering if anyone has had any experience with the various Virtex-based prototyping boards out on the market (e.g., Avnet, VCC, etc.). Any recommendations would be appreciated. Thanks. Sincerely, Hugh Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19290
From memory XACT6000 creates incorrect SDF when VHDL blocks are used. i.e.
instead of <block_label>/<instantiation> you get
<block_label>_<instantiation>
> /TB_ADDR/C_ADDR/COUNT_COL/COUNT(0)/INI/C_MUX
Instead of
(INSTANCE COUNT_COL/COUNT_0_INI_1_C_MUX)
try
(INSTANCE COUNT_COL/COUNT_0/INI_1/C_MUX)
David Robinson
Article: 19291Nicolas Matringe <nicolas@dotcom.fr> a écrit dans le message : 385118FA.151650B9@dotcom.fr... > I want to implement distributed ROMs in a Virtex so I used COREgen > (latest update) > The docs say that the old .coe initialization files are supported. I > still wonder why I got so many error messages... > I then tried with .mif files. COREgen lets you choose the radix (binary > or hex) used in these text files. Well... Choose whatever you want, > it'll work only with binary radix files. > > Makes me want to throw all this junk through the window... > > Nicolas MATRINGE DotCom S.A. > Conception electronique 16 rue du Moulin des Bruyeres > Tel 00 33 1 46 67 51 11 92400 COURBEVOIE > Fax 00 33 1 46 67 51 01 FRANCE J'ai eu le même problème, en fait pour l'instant les fichiers MIF ne fonctionnent que si les valeurs sont en binaire. Cependant avec Logiblox on peut spécifier la base mais c'est mal adapté au Virtex (...) Rémi SEGLIE CELOGICArticle: 19292
this is a test, two groups.Article: 19293
test message two, single groupArticle: 19294
> Can you post your Verilog?
>
> Bob Perlman
Bob and other friends,
thank you very much for your responses. I have all been busy all the
time, so I have just found time to pass the Verilog code.
The dataflow is like this:
e1_buff e1
+--------------FF-------FF--------------FF----------+
| 25 25 6 |
| e2_buff e2 |
| +----------FF-------FF--------------FF------+ |
| | 25 25 6 | |
_|___|__ _|___|__
| | | |
| 25 MHz | | 6 MHz |
| domain | | domain |
|________| |________|
| | | |
| | | |
| | f1_empty f1 f1_buff | |
| | | | | | |
| | V V V | |
| +----FF-------FSM-----FF--------FF----------+ |
| 25 25 6 |
| |
| |
| f2_empty f2 f2_buff |
| | | | |
| V V V |
+-------FF-------FSM-----FF--------FF---------------+
25 25 6
Very very simplified Verilog code:
always @ (posedge clk25m)
begin
e1_buff0 <= e1;
e2_buff0 <= e2;
e1_buff <= e1_buff0;
e2_buff <= e2_buff0;
casex ({e1_buff, g1})
<25_MHz_clock_domain>
endcase
casex ({e2_buff, g2})
<25_MHz_clock_domain>
endcase
casex ({state_25m, rd_en, f1_empty, f2_empty})
<FSM_which_outputs_are_f1_and_f2>
endcase
end
always @ (posedge clk6m)
begin
f1_buff <= f1;
f2_buff <= f2;
end
always @ (negedge clk6m)
begin
if (some_signal)
begin
casex ({state_6m, f1_buff, f2_buff})
<FSM_which_outputs_are_e1_and_e2>
endcase
end
else
begin
dsin <= `HIGH;
e1 <= `HIGH;
e2 <= `HIGH;
end
end
1. 6 MHz and 25 MHz lojics are above, all modeled in the same Verilog file.
2. Some buffered signals modeled separately, some are modeled in another ALWAYS.
3. 25 MHz logics include several case blocks in parallel (I think so,
-Synplify!!-).
4. Non-blocking assignments (NBAs) used, but no transport delay model #DELAY.
Q1: Not important to put different clock domains in the same Verilog file. Is
it?
Q2: Shall the buffers be modeled separetely? Does Synplify-Xilinx behave
different?
Q3: Shall I pay attention to model separate case in the same ALWAYS, rather than
completely separate (i.e. each must have its own ALWAYS)?
Q4: Shall I give transport delay?
Postlayout simulations are correct, lab tests fail. Problem: FSMs must toggle
at every of their own clock executions, i.e. their state registers, 1-bit each,
must toggle 0-1-0-1-0-1... but lab test show 0-1-0-1-1-0-1-0 sometimes.
Design Entry: Verilog
Synthesizer: Synplify v5.21
P&R: Design Manager M1.5 patched
Technology: Xilinx XC4044XLA
Utku
Article: 19295Hi All, Here is the problem : I was using Quartus for synthesis and P+R. However, as my design progressed, there were some verilog statements that Quartus will not handle. So, I started to use Synplify for synthesis, and import the vqm file into Quartus and let it fly. However, I have since started to use dual port and single port rams. I used the MegaWizard in Quartus to generate the ram files, and pushed it through synthesis using Quartus, and it was fine (except for the verilog statements it was choking on). However, once I tried the same design files in Synplify, it whined that it could not find the module lpm_ram_dp and lpm_ram_dq. I assume there must be some file (like xc4000.v for 4000 series Xilinx parts) that I have to include with the design. Is this true? Thanks, Xanatos.Article: 19296
Yes, you just have to include the "BSCAN" part in your design and connect it to the TDI, TDO, TMS and TCK IOparts. After configuration you will have full JTAG access plus the ability to define user defined JTAG instructions. Andrew Xanatos wrote: > Hello All, > > Is it possible for a JTAG to work on a Xilinx XC4000 series FPGA after the > bitfile has been downloaded and configured. I need the JTAG to work on the > FPGA after configuration. I have a feeling it does, but I would like to > confirm this to be sure. > > Thanks, > Xan > > (if email, remove the delme part in my hotmail address)Article: 19297
We've made some progress on this. The ByteBlaster we were using turned out to have an intermittent fault in a cable. We got a new one this AM and it seems to work OK. We still have a couple of issues that we are tracking down, but nothing like it was. Thanks for the input. --- Andy R. Free Spirit wrote: > > What's your chain topology? > Do you have other devices in the chain? > I have 2 GALs and 2 Max 7128A's and dont have > problems under NT or Win98 with a ByteBlaster. > How do the TCK,TMS and TDI look on a scope? > Are you getting a good connect on the VCC pin? > The JTAG interface powers from the Target VCC pin. > I had a lot of problems with the Lattice isp cable, > it was sensitive to parallel port timing, it would > work on one system, only when it was daisy-chained > through a Zip drive. I never got it work my NT system, > using a Soyo motherboard. > You might try putting a 1uf cap on TCK to slow it down, > just to see if you are having a marginal setup problem with > TMS and TDI. > On Thu, 09 Dec 1999 00:00:46 -0500, Andrew Reddig <andyr@tekmicro.com> wrote: > > >Subject tells the story. We have started to have a lot of problems > >lately programming Altera devices through JTAG. We have both a > >"BitBlaster" (serial interface to JTAG port) and a ByteBlasterMV > >(parallel port interface to JTAG). We have had a wide range of problems > >on many different designs. > > > >The common thread is that the device fails to program and MAX-Plus > >either reports that the device is unknown, not installed, JTAG chain is > >bad, or else does an examine/program and then fails with verify errors. > >In the latter case, we can often get exactly the same # of verify errors > >each time. > > > >This happens with two different computers, a couple of different > >versions of MAX-Plus, and both the BitBlaster and the ByteBlasterMV. It > >also happens with both single EPLD systems and cards that have five > >devices in a chain. > > > >The only common thread is that the problem seemed to start when we > >started using MAX7000A's, although it sometimes happens with 7000S > >devices as well. > > > >We've checked pinouts, clocks, signals; all look fine. We've tried > >using the ByteBlasterMV with both 3.3V and 5V, no difference. We've > >buzzed out the cables, tried terminating TCK, and nothing works. But, > >every now and then, you can press "Program" 55 times and get it to work > >on the 55th. Sometimes, you can program all 5 chips in a chain a few > >times without complaint, then it starts failing again. > > > >Anybody seen this kind of thing? Any ideas? We're pulling our hair > >out. > > > >Thanks for any suggestions. -- Andrew Reddig andyr@tekmicro.com TEK Microsystems, Incorporated 781.270.0808 One North Avenue Fax 781.270.0813 Burlington, MA 01803 Web http://www.tekmicro.comArticle: 19298
Hello does anyone know of any FPGA to ASIC conversion CAD tools? Where I could get some on the net and have ago? cheersArticle: 19299
Tom, Check out my article in the May 27, 1999 issue of EDN (http://www.ednmag.com/ednmag/reg/1999/052799/11cs.htm) >Hi, > I heard that there are now some benchmarks that are being used to >compare different FPGA architectures and that Media Bench was one of >them. Does anyone know where you can get this, or where other benchmark >suits that are geared toward FPGA's are? Thanks, > >Tom Fry >University of Washington >zaphod@ee.washington.edu > Brian Dipert Technical Editor: Memory, Multimedia and Programmable Logic EDN Magazine: The Design Magazine Of The Electronics Industry http://www.ednmag.com 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (voice), (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** mailto:bdipert@NOSPAM.pacbell.net Visit me at http://members.aol.com/bdipert
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