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>I have heard that the Win95 Xilinx software is currently being beta tested >- but our maintenance just expired. :-( Funny that, mine has just expired too. What a coincidence. Wonder why? Could it be the asking price for the next 12 months ?? :) Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5776
You may also find the following press release from Xilinx interesting. It discusses their HardWire pricing for PCI. See: http://www.xilinx.com/prs_rls/pciplus.htm -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Peter <z80@dserve.com> wrote in article <332b6cb7.205106597@news.alt.net>... | | >Could it be that the consortium | >members want no challenges from those who are not big enough to do hardwired | >gate arrays? | | Even if your hypothesis might be wrong, your observation is entirely | correct. One just cannot make a cheap PCI card, without an ASIC. | |Article: 5777
Hello.
We can help you to remote_design PCI controller for your devices.
Moore info from request. Please use only E-mail rastr@lan.novsu.ac.ru
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Oleg Kamaletdinov
Article: 5778In article <3325BA09.7C95@a1.nl>, jhmol@a1.nl says... > >Richard Schwarz wrote: >> >> Anybody had any experience with the ACTEL RAM BASED FPGAs? > >having a fine-grained (synthesis-friendly!) architecture. I'm very >curious what ACTEL comes up withArticle: 5779
Stuart Clubb wrote: Try Aptix at: http://www.aptix.com Probably not cheap, but looks_real_nice. :-) Take a look at http://www.erols.com/aaps . The ST-FPGA module has 4 XILINX 208pin QFP chips and a ton of IO pins. The board was originally developed for ASIC design testing.You can put whatever type chips you want on the boards.Article: 5780
In message <858277750.13643@dejanews.com>
rcgipson@ix.netcom.com writes:
> has anyone ever duplicated a 74hc195 with a pld? i've a need
> to add a 195 and some other circuitry in a single chip.
> thanks for the reply.
> roger
> -------------------==== Posted via Deja News ====-----------------------
> http://www.dejanews.com/ Search, Read, Post to Usenet
I've never done a 195 but its only a 4-bit shift register with some
fancy logic on the first stage input - and it only shifts right with
parallel load. If you do it in logic equations it will only be 5
P-terms per output, thats if you need every function. It would fit
in a 16V8 except for the asynchronous reset, but a 22V10 would take
care of that and leave you 4 or 5 inputs and outputs for your other circuitry.
Rgds,
Geoff Bostock
FPGA and PLD Design consultant - http://www.users.zetnet.co.uk/gbostock
Article: 5781Hi, Does anone out there know where I can obtain a copy of the EDIF Format Specification- any on-line sites with info etc. on EDIF would also be appreciated. I'd be grateful if you could e-mail the info and I'll post a summary to the newsgroup Thanks in anticipation Craig Slorach (craigs@elec.gla.ac.uk)Article: 5782
Rich K. wrote: > > ... looking through the xilinx data book, i didn't see the optional > hard reset pin for the jtag tap controller, which figures into the seu > results, and tap controller upsets have been observed on other > manufacturer's chips with jtag with no hard reset. having gone through a > number of data books, i only saw that quicklogic implemented the hard reset > on their parts. personally, with like 200+ pins on these parts, for > military and space and other critical apps, i like the hard reset on the > tap controller and would give up the 1 i/o pin. > > ... > > rk I just saw, most of the Altera FPGAs (eg. Flex 8K and 10K series - I wouldn't like to discuss whether these parts are FPGAs or not) have the optional nTRST pin for resetting the JTAG state machine. So I decided to use it in my current design. Botond -- Kardos, Botond - at Innomed Medical Co. Ltd. in Hungary eMail: kardos@mail.matav.hu phone/fax: (36 1) 268-0934Article: 5783
frank_xie@writeme.com wrote: > > For some reasons, I need to know the total numbers of the Product Term > that are used in my design, but the MaxPlusII compiler report only gives > me the sharable expander numbers. So does anyone know where to find it? > Please don't tell me to count them one by one :-) The device I use is > MAX7000 series. > Sorry, I just don't know, but try sending a message to sos@altera.com. They really gave me usable answers in about 24 hours. Botond -- Kardos, Botond - at Innomed Medical Co. Ltd. in Hungary eMail: kardos@mail.matav.hu phone/fax: (36 1) 268-0934Article: 5784
Hans Tiggeler <ees1ht@ee.surrey.ac.uk> wrote in article <5gb56l$b8d@info-server.surrey.ac.uk>... | In article <3325BA09.7C95@a1.nl>, jhmol@a1.nl says... [snip] | >I fully agree with you. I believe this technology will be the first | >SRAM-based technology on the marktet | >having a fine-grained (synthesis-friendly!) architecture. | It sure is. The basic building block is a logic module which can be configured | to any function with 2 input. There is also one with 3 inputs and one with an | additional d-type ff. What we now need is affordable HDL synthesisers *sign*, From the description, it appears that this architecture is similar to some other already on the market including: Xilinx XC6200 http://www.xilinx.com/products/fpgaspec.htm#XC6200 http://www.vcc.com/products/pci6200.html Atmel AT6000 http://www.atmel.com/atmel/products/products3.html Motorola MPA http://design-net.com/fpga/ All of these devices have a fine-grained architecture. Some synthesis tools find this architecture easier but many tools now have algorithms that support the 4-input look-up table (LUT) architectures common across the coarse-grained architectures. -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagicArticle: 5785
Thomas D. Tessier wrote: > > Erik Jessen wrote: > > > > I would recommend looking at Synario's ECS schematic-capture/waveform > > display tool. it was very solid for us, and had a lot of nice features > > (VHDL, Verilog, EDIF netlisting, can netlist to PCB layout tools, etc.). > > > > We used it with Modeltech and Exemplar, and liked it a lot. We had > > probably 20-30 copies of ECS. > > > > Erik > > Check out Veribest at http://www.veribest.com > > They are currently OEMing FPGA Express and have a very good PCB tool. > > Have fun. > > -- > +-----------------------------------------------------------------------+ > : ttessier@talcian.com | Phone: 303.440.0570 > : > : Thomas Tessier | FAX: 303.441.5811 > : > : | WWW: http://www.talcian.com > : > +------------------------Have a nice > Day--------------------------------+ also, take a look at OrCAD's latest offering at http://www.orcad.com/express/exp_chnl.htmArticle: 5786
> any experience with Accolade-Tools (VHDL-Simulation and FPGA-Synthesis) ? I downloaded their demo and it died a horrible death under NT 4.0. Initially their tech support was helpful, but they never did deliver on their promise to get back to me regarding their investigations into why it died. ---Joel KolstadArticle: 5787
Well here's my 2 cents worth. Rays LFSR is an easy way of generating a sequence for the address refresh, since the order of the Row refreshes is unimportant as long as the cycle round regularly. Easiest refresh is using a Cas Before Ras (CBR) cycle. The load and shift 'trick' for address generation works fine. If you can afford the delays of not using any fast page mode, you can arrange your data for real time apps so you use a different ROW for each access sequentially, if you can do this you can keep the area of the RAM chip you are using refreshed just by using it, of course if you pause for too long at any stage you may lose data however I found I was cycling RAM about 4 time faster than the refresh period so this was not a problem, Note also the important refresh time is for the whole chip, it is not important to refresh lines at even time intervals so long as the whole chip gets done in the required time. Using this approach if greater bandwidth is need use cheap 32bit 72pin PC simms instead of the old 8 bit 32 pin SIMMs. Otherwise you need to find a gap to deep your refresh. Finding a gap in some data stream easpecially video to perform regular refreshes can be awkard, since to do a refresh takes approx 100ns, for the refresh access followed by the precharge period. In article <33242E6E.76C3@geocities.com>, Christos Dimitrakakis <olethros@geocities.com> writes >I am considering the usage of a Xilinx FPGA as a DSP chip that also >controls memory access to a single SIMM. The FPGA will be the only >device accessing the memory. >Are there any app notes/example designs on using the Xilinx as memory >decoders? >Furthermore, I have no knowledge of SIMM operation, so if anyone could >fill me in on that I would be very grateful :) -- Andrew PapageorgiouArticle: 5788
Xilinx XC9500 FastFlash Seminar Topics Technology Seminar *FastFlash Technology Insight Electronics invites you to a free half-day seminar on the Xilinx XC9500 FastFLASH CPLD family and its design software tools. Breakfast and lunch provided. Receive a free copy of the latest evaluation software *XC9500 Architecture Overview and Xilinx Applinx CD - ROM which includes application notes, design and applications files, databook, and more! Date: March 19, 1997 *Pin Locking Architecture with Superior EX’s Time: 8:00 AM - 12:00 Noon Location: Holiday Inn, Gaithersburg (301) 948-8900 *XC9500 Sotware Tools and (ISP) Operation and Demo. 2 Montgomery Village Ave. Call Insight Electronics at 800-677-7716 XILINXArticle: 5789
In article <L3ZHANG.18.3324A6E7@ELECOM2.watstar.uwaterloo.ca>, L3ZHANG@ELECOM2.watstar.uwaterloo.ca (Louis Zhang) wrote: > Unfortunately, unlike the discrete RAM and RAM cell in ASIC, the RAM cell in > Xilinx 4000 has address and data setup/hold time requirements. Whenever I read "hold time" my blood pressure goes up 10 mm. The XC4000E data sheet lists hold time as 0, i.e. ZERO. So, don't worry about hold time. And EVERY clocked device has a set-up time. Just for the record... Peter Alfke, Xilinx ApplicationsArticle: 5790
In article <01bc30ac$e2c746b0$0307e38f@zimbo>, "Joel Kolstad" <Joel.Kolstad@Techne-Sys.com> wrote: >> any experience with Accolade-Tools (VHDL-Simulation and FPGA-Synthesis) ? > >I downloaded their demo and it died a horrible death under NT 4.0. > And it's REAL unstable under W95Article: 5791
Don Husby wrote: > > Steve Bird steveb@vizef.demon.co.uk wrote: > > I guess you didn't like it... > > I haven't tried it. > This was supposed to be humor. Here's the smiley :) > > For the humor impaired: > Galileo and Leonardo are products from Exemplar logic > Renoir is a is a product of Mentor Graphics > This was not intended to cast aspersions on any these products. > > Here's some more smiley's :) :) Don't worry, it put a smile on my face - I thought is was very good ! Nice to see the grind hasn't robbed us all of our sense of humour. reminds me of the ( probably global saying ) 'He who can smile when it's all going wrong, has just thought of someone to blame ' :-) - jimArticle: 5792
Andreas Kugel wrote: Todd A. Kline wrote: > > We are currently using ViewSynthesis and ViewPLD for FPGA and PLD/CPLD > designs. > We find ViewSynthesis optimizes the Xilinx FPGAs very poorly and ViewPLD > is buggy, unstable, and poorly supported. I would be very grateful for > any feedback on the following products: > > 1) Exemplar > > 2) Synario > > 3) Minc (PLD/CPLD) + Synplicity (FPGA). > > I have done some benchmarking on Synplicity and found that it optimized > better then ViewSynthesis, but I'd prefer a unified VHDL/ABEL solution. > > I also must say that I have a GREAT prejudice against Synario. I have > found DataIO support to be on a par with VIEWlogic, that is to say > horrible. I also have doubts about DataIO's commitment to EDA > products. Does any one remember FutureNet/Gates? > > For these reasons I find my self leaning to Exemplar but only because I > know next to nothing about them. Ignorance is, after all, bliss. > > Your feedback is eagerly anticipated. > > Todd Synplicity is a very fast synthesis tool but gives almost no feedback about what it has done (at least in last years release 2.99). Exemplar gave a very good impression in a demo. You might also want to check the accolade tools (I believe their address is http://www.acc-eda.com) or synopsys fpga express. -- Andreas Kugel, Karolinenstr. 4 76135 Karlsruhe, Germany Phone: (49) 721 377865, Fax (49) 721 937 49 12 E-mail: akugel@t-online.de The foundation tools from XILINX are a great VHDL/ABEL/SCHEMATIC/ROUTER combination. Check them out at http://www.erols.com/aapsArticle: 5793
Does anyone know how to make the old AA dongles work on a Pentium 166 or a 6x86 P200+. I have tested several machines with the old AA dongle and have found it only to run on pentium machines up to a 150MHz. I have also tried using the dongle on an ISA parallel port in these fast machines but with no sucess. Thanks GeoffArticle: 5794
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IMPORTANT ANNOUNCEMENT
ISPD-97 Hotel Reservation & Symposium Registration
Due to a combination of high demand and various logistic
difficulties with the 1-800-EMBASSY reservation center, Embassy
Suites has just added some more rooms to the ISPD-97 block and has
moved the hotel reservation deadline to FRIDAY, MARCH 21.
Also, the hotel will now directly accept reservations at
* 1-707-253-9540 (ask for the Reservations Dept)
If you STILL have any difficulty with hotel registration despite
this, please e-mail to abk@cs.ucla.edu with your telephone contact;
someone from the ISPD-97 organization or the hotel will call you to
finalize a registration or else direct you to another hotel if our
room block is sold out.
We are also extending the deadline for early registration over the
weekend, to MONDAY, MARCH 17 (postmark or fax deadline).
----------------------------------------------------------------------------
Advance Program
1997 International Symposium on Physical Design
Embassy Suites at Napa Valley, Napa, California
April 14--16, 1997
http://www.cs.virginia.edu/~ispd97/
The International Symposium on Physical Design provides a new and high-quality
forum for the exchange of ideas and results in critical areas related to the
physical design of VLSI systems. The Symposium is an outgrowth of the
ACM/SIGDA Physical Design Workshops held during the years 1987-1996. Its scope
includes all aspects of physical design, from interactions with behavior-
and logic-level synthesis, to back-end performance analysis and verification.
This year's inaugural Symposium focuses on the challenges of high-performance
deep-submicron design, as well as the necessary interactions between physical
design and higher-level synthesis tasks. An outstanding slate of technical
papers has been selected for oral and poster presentation. These developments
are complemented by invited presentations that set forth the contexts and
visions for key areas -- process technology, system architecture, circuit
design and design methodology -- with an emphasis on their implications for
relevant R&D in physical design. The Symposium concludes with a panel of
leading experts who each present their unique perspectives as to the critical
R&D needs of the field.
%%==========================================================================%%
%% Monday, April 14 %%
%%==========================================================================%%
0830-0840 Chairs' Welcome
A. B. Kahng and M. Sarrafzadeh
0840-1010 Keynote Address
* Physical Design: Past and Future, T. C. Hu (UCSD), E. S. Kuh (UCB)
1010-1030 Break
1030-1230 Session 1: Placement and Partitioning
Chairs: D. Hill (Synopsys)
J. Frankle (Aristo Technology)
* Faster Minimization of Linear Wirelength for Global Placement,
C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet,
K. Yan (UCLA, Cadence and IBM)
* Network Flow Based Multi-Way Partitioning with Area and Pin Constraints,
H. Liu, D. F. Wong (UT-Austin)
* Partitioning-Based Standard-Cell Global Placement with An Exact Objective,
D. J. Huang, A. B. Kahng (UCLA and Cadence)
* VLSI/PCB Placement with Obstacles Based on Sequence Pair,
H. Murata, K. Fujiyoshi, M. Kaneko (JAIST and Tokyo Inst. of Tech.)
1230--1430 Lunch (Speaker)
* The Quarter Micron Challenge: Integrating Physical and Logic Design
R. Camposano (Synopsys)
1430--1600 Session 2: Synthesis and Layout
Chairs: R. Camposano (Synopsys)
C. Sechen (Washington)
* Timing Driven Placement in Interaction with Netlist Transformations,
G. Stenz, B. R. Riess, B. Rohfleisch, F. M. Johannes (TU-Munich)
* Regular Layout Generation of Logically Optimized Datapaths,
R.X.T. Nijssen, C.A.J. van Eijk (TU-Eindhoven)
* Minimizing Interconnect Energy Through Integrated Low-Power Placement
and Combinational Logic Synthesis,
G. Holt, A. Tyagi (Iowa State)
1600--1630 Break
1630--1830 Session 3: Contexts (Invited)
* Design Technology Trends Based on NTRS Evolution,
P. Verhofstadt, C. D'Angelo (SRC)
* Microprocessor Architecture, Circuit, and Physical Design Trends,
R. Panwar (Sun)
1900--2100 Dinner (Speaker)
* Lithography and Dimensional Trends for Future Processes -- Implications
for Physical Design
P. K. Vasudev (Sematech)
%%==========================================================================%%
%% Tuesday, April 15 %%
%%==========================================================================%%
0830--1000 Session 4: Routing
Chairs: T. S. Moh (Silicon valley Research)
D. F. Wong (UT-Austin)
* On Two-Step Routing for FPGAs,
G. G. Lemieux, S. D. Brown, D. Vranesic (Toronto)
* A Simple and Effective Greedy Multilayer Router for MCMs,
Y.-J. Cha (Electronic & Telecomm Research Institute),
C. S. Rim (Sogang U.), K. Nakajima (Maryland)
* Performance Driven Global Routing for Standard Cells,
J. Cong and P. Madden (UCLA)
1000--1030 Break
1030--1200 Session 5: Steiner Tree Constructions
Chairs: M. Marek-Sadowska (UCSB)
N. Sherwani (Intel)
* Min-Cost Flow based Min-Cost Rectilinear Steiner Distance-Preserving
Tree Construction,
J. D. Cho (SungKyunKwan)
* Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence
Problem with Applications to VLSI Physical Design,
J. Cong, A. B. Kahng, K.-S. Leung (UCLA and Cadence)
* Provably Good Routing Tree Construction with Multi-Port Terminals,
C. Bateman, C. S. Helvig, G. Robins, A. Zelikovsky (Virginia)
1200--1330 Lunch
1330--1500 Session 6: Back-End Design Methodology
Chairs: C.-K. Cheng (UCSD)
M. Weisel (Intel)
* A Roadmap of CAD Tool Changes for Sub-Micron Interconnect Problems,
L. Scheffer (Cadence)
* C5M - A Control Logic Layout Synthesis System for High-performance
Microprocessors,
J. Burns, J. Feldman (IBM)
* A VLSI Artwork Legalization Technique Based on a New Criterion of
Minimum Layout Perturbation,
F.-L. Heng, Z. Chen, G. E. Tellez (IBM)
1500--1545 Session 7: Poster Presentations
Chairs: G. Robins (Virginia)
J. D. Cho (SungKyunKwan)
* A Pseudo-Hierarchical Methodology for High Performance
Microprocessor Design,
A. Bertolet, K. Carpenter, K. Carrig, A. Chu, A. Dean, F. Ferraiolo,
S. Kenyon, D. Phan, J. Petrovick, G. Rodgers, D. Willmott (IBM);
T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott,
R. Weiss (Cadence)
* Concurrent Transistor Sizing and Buffer Insertion by Considering
Cost-Delay Tradeoffs,
J. Kim, C. Bamji (Cadence); Y. Jiang, S. Sapatnekar (Iowa State)
* Towards a New Benchmarking Paradigm in EDA,
N. Kapur, D. Ghosh, F. Brglez (NCSU)
* How Good are Slicing Floorplans?,
F. Y. Young, D. F. Wong (UT-Austin)
* Slicibility of Rectangular Graphs and Floorplan Optimization,
P. DasGupta, S. Sur-kolay (Indian Institute of Management)
* Power Optimization for FPGA Look-Up Tables,
M. J. Alexander (Washington State)
* A Matrix Synthesis Approach to Thermal Placement,
C. C.-N. Chu, D. F. Wong (UT-Austin)
* Preserving HDL Synthesis Hierarchy for Cell Placement
Y.-W. Tsay, W.-J. Fang, A. C.-H. Wu and Y.-L. Lin (Tsing Hua)
1545--1715 Session 8: Poster Session
Authors display and discuss one-on-one the posters presented in Poster
Presentation session.
1900--2200 Banquet
%%==========================================================================%%
%% Wednesday, April 16 %%
%%==========================================================================%%
0830--1000 Session 9: Performance Optimization
Chairs: W. W.-M. Dai (UCSC)
L. Jones (Motorola)
* EWA: Exact Wire Sizing Algorithm,
R. Kay, G. Bucheuv, L. Pileggi (CMU)
* Minimization of Chip Size and Power Consumption of High Speed VLSI Buffers,
D. Zhou, X. Y. Liu, X. L. Wang (UNC-Charlotte)
* Closed Form Solution to Simultaneous Buffer Insertion/Sizing and
Wire Sizing,
C. C.-N. Chu, D. F. Wong (UT-Austin)
1000--1030 Break
1030--1230 Session 10: Design Methodology Futures (Invited)
* Chip Hierarchical Design System (CHDS): A Foundation for Timing-Driven
Physical Design into the 21st Century}
R. G. Bushroe (Sematech/HP), S. DasGupta (IBM), R. Steele (Sematech/Intel)
* Physical Design 2010: Back to the Future?
A. R. Newton (UCB)
1230--1430 Lunch (Speaker)
* Physical Design Realities for Digital's StrongARM and Alpha Microprocessors
W. J. Grundmann (DEC)
1430--1700 Session 11: Core Directions (or, Do The Right Thing) (Invited)
* Physical Design Challenges of Performance
D. P. LaPotin (IBM Austin Research Lab)
* Panel: Physical Design R&D: What's Missing?
Moderator: G. Smith (Dataquest)
W. W.-M. Dai (UCSC)
E. Hsieh (Avant!)
M. Hunt (Cadence)
K. Keutzer (Synopsys)
D. P. LaPotin (IBM Austin Research Lab)
N. Sherwani (Intel Hillsboro)
1700 Symposium Closes
%%==========================================================================%%
%% Symposium Organization %%
%%==========================================================================%%
General Chair: A. B. Kahng (UCLA and Cadence)
Past Chair: G. Robins (Virginia)
Steering Committee:
J. P. Cohoon (Virginia),
S. DasGupta (IBM),
S.-M. Kang (Illinois),
B. Preas (Xerox PARC)
Technical Program Chair: M. Sarrafzadeh (Northwestern)
Technical Program Committee:
C.-K. Cheng (UCSD),
W. W.-M. Dai (UCSC),
J. Frankle (Aristo Technology),
D. D. Hill (Synopsys),
J. A. G. Jess (Eindhoven),
L. Jones (Motorola),
Y.-L. Lin (Tsing Hua),
C. L. Liu (Illinois),
M. Marek-Sadowska (UCSB),
C. Sechen (Washington),
K. Takamizawa (NEC),
M. Wiesel (Intel),
D. F. Wong (UT-Austin),
E. Yoffa (IBM)
Publicity Chair: M. J. Alexander (Washington State)
Local Arrangements Chair: J. Lillis (UCB)
Treasurer: S. B. Souvannavong
Sponsors:
ACM Special Interest Group on Design Automation, in cooperation with
IEEE Circuits and Systems Society
Additional Support From:
Avant! Corporation,
Cadence Design Systems, Inc.,
Intel Corporation,
Synopsys Inc., and the
U. S. National Science Foundation.
%%==========================================================================%%
%% Hotel Accommodations and Travel %%
%%==========================================================================%%
ISPD-97 is being held at the Embassy Suites at Napa Valley (formerly the
Inn at Napa Valley) in Napa, California. The hotel is located 55 miles north
of San Francisco, CA in the beautiful Napa Valley. Evans Airport Service
provides daily service between Embassy Suites at Napa Valley and San Francisco
International Airport (SFO) approximately every two hours. On Saturdays and
Sundays, the first departure from SFO is at 8:15am. A one-way fare is $18.00,
and advance reservations are required. Phone 1-707-255-1559 or
FAX 1-707-255-0753. The Embassy Suites at Napa Valley is located at:
1075 California Boulevard
Napa, CA 94559
Phone: 1-707-253-9540
Fax: 1-707-253-9202
Hotel Reservations:
1-707-253-9540 (ask for the Reservations Dept)
1-800-362-2779 (Central Embassy Suites reservation service.)
A block of rooms is being held for the nights of Sunday through Wednesday
(April 13 through April 16). Room rates are $105 per night for single or
double occupancy. Any individual cancellations within 48 hours from the
date of arrival will be billed for (1) night's stay, plus tax.
+---------------------------------------------------------+
| Please make room reservations directly with the hotel |
| at either 1-707-253-9540 or 1-800-362-2779, mentioning |
| ``GROUP CODE ACM''. |
+---------------------------------------------------------+
The number of rooms available at this rate is limited, and are only being
held through March 21. Early room reservation is highly recommended.
For attendees wishing to stay over Friday and Saturday night, a special rate
of $129 per night, subject to room availablity, has been arranged for
April 11--12 and April 17--19.
%%==========================================================================%%
%% ISPD-97 Advance Registration Form %%
%%==========================================================================%%
Name: _______________________________________________________
Company/University: _________________________________________
Responsibility/Title: _______________________________________
Address: ____________________________________________________
City: _______________________________ State: ________________
Country: ______________________ Postal Code: ________________
Phone: ________________________ Fax: ________________________
Email: ______________________________________________________
Food Choices:
[ ] Vegetarian meals only
[ ] Swordfish or [ ] Filet Mignon (Monday dinner)
Advance Late
(Through March 17) (After March 17)
ACM/IEEE Members [ ] $350 [ ] $425
Non-Members [ ] $425 [ ] $500
Full-Time Students [ ] $175 [ ] $225
Student ID is required if registering as a student.
ACM or IEEE Member No. _____________________________
Registration fee includes meals and Banquet. A limited number of
additional Banquet tickets are available.
_______ Extra Banquet tickets at $50/each.
Payment may be submitted via personal or company check in US funds only and
drawn on a US bank, made payable to ``ACM/1997 International Symposium on
Physical Design''. Payment may also be made with credit card (circle):
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Signature: ___________________________ Date: ________________
Please mail or FAX (credit card only) your completed registration form to:
ISPD-97 Symposium Registration
Sally Souvannavong, Treasurer
P.O. Box 395
Pullman, WA 99163-0395
FAX: 1-509-335-3818
Email registration will not be accepted. Cancellations must be in writing
and must be received by March 31, 1997. Questions concerning symposium
registration should be directed to Sally Souvannavong at 1-509-334-3162,
Email: ispd97@eecs.wsu.edu.
%%==========================================================================%%
%% Additional Information %%
%%==========================================================================%%
Check in at Your Convenience:
The symposium registration desk will be open from 4pm to 6pm on Sunday,
April 13th. On Monday, the registration desk will open at 7:30am and
will remain open until 5:00pm.
Experience Springtime in Napa Valley:
Napa Valley weather is very pleasant in April, with an average high temperature
of 78 degrees F and low of 64 degrees F. Attractions include world-famous
wineries offering daily tours, golf and outdoor-recreation facilities, and
easy access to Marine World--Africa USA. Contact the Napa Valley Tourist
Bureau (1-800-523-4353) or Visitors Bureau (1-707-226-7459), or visit the
following websites for additional information:
ISPD-97 Website -- http://www.cs.virginia.edu/~ispd97/
Napa Valley Virtual Visit -- http://www.napavalley.com/cgi-bin/home.o
Conference and Visitors Bureau -- http://www.napavalley.com/nvcvb.html
Driving Directions from East Bay:
Take Hwy 80 to Hwy 37 west, 2 miles to Hwy 29 north, 12 miles to 1st Street
exit to California Boulevard (first left turn off freeway).
Driving Directions from San Francisco:
Take Hwy 101 to Hwy 37 east, 7 miles to Hwy 121 north, then east 15 miles
to Hwy 29 north, 2 miles to 1st Street exit to California Boulevard
(first left turn off freeway).
Article: 5795
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IMPORTANT ANNOUNCEMENT
ISPD-97 Hotel Reservation & Symposium Registration
Due to a combination of high demand and various logistic
difficulties with the 1-800-EMBASSY reservation center, Embassy
Suites has just added some more rooms to the ISPD-97 block and has
moved the hotel reservation deadline to FRIDAY, MARCH 21.
Also, the hotel will now directly accept reservations at
* 1-707-253-9540 (ask for the Reservations Dept)
If you STILL have any difficulty with hotel registration despite
this, please e-mail to abk@cs.ucla.edu with your telephone contact;
someone from the ISPD-97 organization or the hotel will call you to
finalize a registration or else direct you to another hotel if our
room block is sold out.
We are also extending the deadline for early registration over the
weekend, to MONDAY, MARCH 17 (postmark or fax deadline).
----------------------------------------------------------------------------
Advance Program
1997 International Symposium on Physical Design
Embassy Suites at Napa Valley, Napa, California
April 14--16, 1997
http://www.cs.virginia.edu/~ispd97/
The International Symposium on Physical Design provides a new and high-quality
forum for the exchange of ideas and results in critical areas related to the
physical design of VLSI systems. The Symposium is an outgrowth of the
ACM/SIGDA Physical Design Workshops held during the years 1987-1996. Its scope
includes all aspects of physical design, from interactions with behavior-
and logic-level synthesis, to back-end performance analysis and verification.
This year's inaugural Symposium focuses on the challenges of high-performance
deep-submicron design, as well as the necessary interactions between physical
design and higher-level synthesis tasks. An outstanding slate of technical
papers has been selected for oral and poster presentation. These developments
are complemented by invited presentations that set forth the contexts and
visions for key areas -- process technology, system architecture, circuit
design and design methodology -- with an emphasis on their implications for
relevant R&D in physical design. The Symposium concludes with a panel of
leading experts who each present their unique perspectives as to the critical
R&D needs of the field.
%%==========================================================================%%
%% Monday, April 14 %%
%%==========================================================================%%
0830-0840 Chairs' Welcome
A. B. Kahng and M. Sarrafzadeh
0840-1010 Keynote Address
* Physical Design: Past and Future, T. C. Hu (UCSD), E. S. Kuh (UCB)
1010-1030 Break
1030-1230 Session 1: Placement and Partitioning
Chairs: D. Hill (Synopsys)
J. Frankle (Aristo Technology)
* Faster Minimization of Linear Wirelength for Global Placement,
C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet,
K. Yan (UCLA, Cadence and IBM)
* Network Flow Based Multi-Way Partitioning with Area and Pin Constraints,
H. Liu, D. F. Wong (UT-Austin)
* Partitioning-Based Standard-Cell Global Placement with An Exact Objective,
D. J. Huang, A. B. Kahng (UCLA and Cadence)
* VLSI/PCB Placement with Obstacles Based on Sequence Pair,
H. Murata, K. Fujiyoshi, M. Kaneko (JAIST and Tokyo Inst. of Tech.)
1230--1430 Lunch (Speaker)
* The Quarter Micron Challenge: Integrating Physical and Logic Design
R. Camposano (Synopsys)
1430--1600 Session 2: Synthesis and Layout
Chairs: R. Camposano (Synopsys)
C. Sechen (Washington)
* Timing Driven Placement in Interaction with Netlist Transformations,
G. Stenz, B. R. Riess, B. Rohfleisch, F. M. Johannes (TU-Munich)
* Regular Layout Generation of Logically Optimized Datapaths,
R.X.T. Nijssen, C.A.J. van Eijk (TU-Eindhoven)
* Minimizing Interconnect Energy Through Integrated Low-Power Placement
and Combinational Logic Synthesis,
G. Holt, A. Tyagi (Iowa State)
1600--1630 Break
1630--1830 Session 3: Contexts (Invited)
* Design Technology Trends Based on NTRS Evolution,
P. Verhofstadt, C. D'Angelo (SRC)
* Microprocessor Architecture, Circuit, and Physical Design Trends,
R. Panwar (Sun)
1900--2100 Dinner (Speaker)
* Lithography and Dimensional Trends for Future Processes -- Implications
for Physical Design
P. K. Vasudev (Sematech)
%%==========================================================================%%
%% Tuesday, April 15 %%
%%==========================================================================%%
0830--1000 Session 4: Routing
Chairs: T. S. Moh (Silicon valley Research)
D. F. Wong (UT-Austin)
* On Two-Step Routing for FPGAs,
G. G. Lemieux, S. D. Brown, D. Vranesic (Toronto)
* A Simple and Effective Greedy Multilayer Router for MCMs,
Y.-J. Cha (Electronic & Telecomm Research Institute),
C. S. Rim (Sogang U.), K. Nakajima (Maryland)
* Performance Driven Global Routing for Standard Cells,
J. Cong and P. Madden (UCLA)
1000--1030 Break
1030--1200 Session 5: Steiner Tree Constructions
Chairs: M. Marek-Sadowska (UCSB)
N. Sherwani (Intel)
* Min-Cost Flow based Min-Cost Rectilinear Steiner Distance-Preserving
Tree Construction,
J. D. Cho (SungKyunKwan)
* Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence
Problem with Applications to VLSI Physical Design,
J. Cong, A. B. Kahng, K.-S. Leung (UCLA and Cadence)
* Provably Good Routing Tree Construction with Multi-Port Terminals,
C. Bateman, C. S. Helvig, G. Robins, A. Zelikovsky (Virginia)
1200--1330 Lunch
1330--1500 Session 6: Back-End Design Methodology
Chairs: C.-K. Cheng (UCSD)
M. Weisel (Intel)
* A Roadmap of CAD Tool Changes for Sub-Micron Interconnect Problems,
L. Scheffer (Cadence)
* C5M - A Control Logic Layout Synthesis System for High-performance
Microprocessors,
J. Burns, J. Feldman (IBM)
* A VLSI Artwork Legalization Technique Based on a New Criterion of
Minimum Layout Perturbation,
F.-L. Heng, Z. Chen, G. E. Tellez (IBM)
1500--1545 Session 7: Poster Presentations
Chairs: G. Robins (Virginia)
J. D. Cho (SungKyunKwan)
* A Pseudo-Hierarchical Methodology for High Performance
Microprocessor Design,
A. Bertolet, K. Carpenter, K. Carrig, A. Chu, A. Dean, F. Ferraiolo,
S. Kenyon, D. Phan, J. Petrovick, G. Rodgers, D. Willmott (IBM);
T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott,
R. Weiss (Cadence)
* Concurrent Transistor Sizing and Buffer Insertion by Considering
Cost-Delay Tradeoffs,
J. Kim, C. Bamji (Cadence); Y. Jiang, S. Sapatnekar (Iowa State)
* Towards a New Benchmarking Paradigm in EDA,
N. Kapur, D. Ghosh, F. Brglez (NCSU)
* How Good are Slicing Floorplans?,
F. Y. Young, D. F. Wong (UT-Austin)
* Slicibility of Rectangular Graphs and Floorplan Optimization,
P. DasGupta, S. Sur-kolay (Indian Institute of Management)
* Power Optimization for FPGA Look-Up Tables,
M. J. Alexander (Washington State)
* A Matrix Synthesis Approach to Thermal Placement,
C. C.-N. Chu, D. F. Wong (UT-Austin)
* Preserving HDL Synthesis Hierarchy for Cell Placement
Y.-W. Tsay, W.-J. Fang, A. C.-H. Wu and Y.-L. Lin (Tsing Hua)
1545--1715 Session 8: Poster Session
Authors display and discuss one-on-one the posters presented in Poster
Presentation session.
1900--2200 Banquet
%%==========================================================================%%
%% Wednesday, April 16 %%
%%==========================================================================%%
0830--1000 Session 9: Performance Optimization
Chairs: W. W.-M. Dai (UCSC)
L. Jones (Motorola)
* EWA: Exact Wire Sizing Algorithm,
R. Kay, G. Bucheuv, L. Pileggi (CMU)
* Minimization of Chip Size and Power Consumption of High Speed VLSI Buffers,
D. Zhou, X. Y. Liu, X. L. Wang (UNC-Charlotte)
* Closed Form Solution to Simultaneous Buffer Insertion/Sizing and
Wire Sizing,
C. C.-N. Chu, D. F. Wong (UT-Austin)
1000--1030 Break
1030--1230 Session 10: Design Methodology Futures (Invited)
* Chip Hierarchical Design System (CHDS): A Foundation for Timing-Driven
Physical Design into the 21st Century}
R. G. Bushroe (Sematech/HP), S. DasGupta (IBM), R. Steele (Sematech/Intel)
* Physical Design 2010: Back to the Future?
A. R. Newton (UCB)
1230--1430 Lunch (Speaker)
* Physical Design Realities for Digital's StrongARM and Alpha Microprocessors
W. J. Grundmann (DEC)
1430--1700 Session 11: Core Directions (or, Do The Right Thing) (Invited)
* Physical Design Challenges of Performance
D. P. LaPotin (IBM Austin Research Lab)
* Panel: Physical Design R&D: What's Missing?
Moderator: G. Smith (Dataquest)
W. W.-M. Dai (UCSC)
E. Hsieh (Avant!)
M. Hunt (Cadence)
K. Keutzer (Synopsys)
D. P. LaPotin (IBM Austin Research Lab)
N. Sherwani (Intel Hillsboro)
1700 Symposium Closes
%%==========================================================================%%
%% Symposium Organization %%
%%==========================================================================%%
General Chair: A. B. Kahng (UCLA and Cadence)
Past Chair: G. Robins (Virginia)
Steering Committee:
J. P. Cohoon (Virginia),
S. DasGupta (IBM),
S.-M. Kang (Illinois),
B. Preas (Xerox PARC)
Technical Program Chair: M. Sarrafzadeh (Northwestern)
Technical Program Committee:
C.-K. Cheng (UCSD),
W. W.-M. Dai (UCSC),
J. Frankle (Aristo Technology),
D. D. Hill (Synopsys),
J. A. G. Jess (Eindhoven),
L. Jones (Motorola),
Y.-L. Lin (Tsing Hua),
C. L. Liu (Illinois),
M. Marek-Sadowska (UCSB),
C. Sechen (Washington),
K. Takamizawa (NEC),
M. Wiesel (Intel),
D. F. Wong (UT-Austin),
E. Yoffa (IBM)
Publicity Chair: M. J. Alexander (Washington State)
Local Arrangements Chair: J. Lillis (UCB)
Treasurer: S. B. Souvannavong
Sponsors:
ACM Special Interest Group on Design Automation, in cooperation with
IEEE Circuits and Systems Society
Additional Support From:
Avant! Corporation,
Cadence Design Systems, Inc.,
Intel Corporation,
Synopsys Inc., and the
U. S. National Science Foundation.
%%==========================================================================%%
%% Hotel Accommodations and Travel %%
%%==========================================================================%%
ISPD-97 is being held at the Embassy Suites at Napa Valley (formerly the
Inn at Napa Valley) in Napa, California. The hotel is located 55 miles north
of San Francisco, CA in the beautiful Napa Valley. Evans Airport Service
provides daily service between Embassy Suites at Napa Valley and San Francisco
International Airport (SFO) approximately every two hours. On Saturdays and
Sundays, the first departure from SFO is at 8:15am. A one-way fare is $18.00,
and advance reservations are required. Phone 1-707-255-1559 or
FAX 1-707-255-0753. The Embassy Suites at Napa Valley is located at:
1075 California Boulevard
Napa, CA 94559
Phone: 1-707-253-9540
Fax: 1-707-253-9202
Hotel Reservations:
1-707-253-9540 (ask for the Reservations Dept)
1-800-362-2779 (Central Embassy Suites reservation service.)
A block of rooms is being held for the nights of Sunday through Wednesday
(April 13 through April 16). Room rates are $105 per night for single or
double occupancy. Any individual cancellations within 48 hours from the
date of arrival will be billed for (1) night's stay, plus tax.
+---------------------------------------------------------+
| Please make room reservations directly with the hotel |
| at either 1-707-253-9540 or 1-800-362-2779, mentioning |
| ``GROUP CODE ACM''. |
+---------------------------------------------------------+
The number of rooms available at this rate is limited, and are only being
held through March 21. Early room reservation is highly recommended.
For attendees wishing to stay over Friday and Saturday night, a special rate
of $129 per night, subject to room availablity, has been arranged for
April 11--12 and April 17--19.
%%==========================================================================%%
%% ISPD-97 Advance Registration Form %%
%%==========================================================================%%
Name: _______________________________________________________
Company/University: _________________________________________
Responsibility/Title: _______________________________________
Address: ____________________________________________________
City: _______________________________ State: ________________
Country: ______________________ Postal Code: ________________
Phone: ________________________ Fax: ________________________
Email: ______________________________________________________
Food Choices:
[ ] Vegetarian meals only
[ ] Swordfish or [ ] Filet Mignon (Monday dinner)
Advance Late
(Through March 17) (After March 17)
ACM/IEEE Members [ ] $350 [ ] $425
Non-Members [ ] $425 [ ] $500
Full-Time Students [ ] $175 [ ] $225
Student ID is required if registering as a student.
ACM or IEEE Member No. _____________________________
Registration fee includes meals and Banquet. A limited number of
additional Banquet tickets are available.
_______ Extra Banquet tickets at $50/each.
Payment may be submitted via personal or company check in US funds only and
drawn on a US bank, made payable to ``ACM/1997 International Symposium on
Physical Design''. Payment may also be made with credit card (circle):
Mastercard Visa American Express
Credit Card # _______________________________________________
Expiration Date: ______________ Total Payment: ______________
Name as it appears on credit card: __________________________
Signature: ___________________________ Date: ________________
Please mail or FAX (credit card only) your completed registration form to:
ISPD-97 Symposium Registration
Sally Souvannavong, Treasurer
P.O. Box 395
Pullman, WA 99163-0395
FAX: 1-509-335-3818
Email registration will not be accepted. Cancellations must be in writing
and must be received by March 31, 1997. Questions concerning symposium
registration should be directed to Sally Souvannavong at 1-509-334-3162,
Email: ispd97@eecs.wsu.edu.
%%==========================================================================%%
%% Additional Information %%
%%==========================================================================%%
Check in at Your Convenience:
The symposium registration desk will be open from 4pm to 6pm on Sunday,
April 13th. On Monday, the registration desk will open at 7:30am and
will remain open until 5:00pm.
Experience Springtime in Napa Valley:
Napa Valley weather is very pleasant in April, with an average high temperature
of 78 degrees F and low of 64 degrees F. Attractions include world-famous
wineries offering daily tours, golf and outdoor-recreation facilities, and
easy access to Marine World--Africa USA. Contact the Napa Valley Tourist
Bureau (1-800-523-4353) or Visitors Bureau (1-707-226-7459), or visit the
following websites for additional information:
ISPD-97 Website -- http://www.cs.virginia.edu/~ispd97/
Napa Valley Virtual Visit -- http://www.napavalley.com/cgi-bin/home.o
Conference and Visitors Bureau -- http://www.napavalley.com/nvcvb.html
Driving Directions from East Bay:
Take Hwy 80 to Hwy 37 west, 2 miles to Hwy 29 north, 12 miles to 1st Street
exit to California Boulevard (first left turn off freeway).
Driving Directions from San Francisco:
Take Hwy 101 to Hwy 37 east, 7 miles to Hwy 121 north, then east 15 miles
to Hwy 29 north, 2 miles to 1st Street exit to California Boulevard
(first left turn off freeway).
Article: 5796
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Article: 5797The AA (and AB and AC) dongles don't seem to work with machines that run their parallel port faster than older machines. In particular, most new machines support a fast parallel port mode called ECP mode. If you check in your BIOS setup, you may find that you can disable it by selecting commpatibility mode. this may solve your problems. good luck, Philip Freidin In article <5gf2n3$mnj$1@wolfman.xtra.co.nz> fourd@xtra.co.nz (Four D Electronics) writes: >Does anyone know how to make the old AA dongles work on a Pentium 166 or a >6x86 P200+. > >I have tested several machines with the old AA dongle and have found it only >to run on pentium machines up to a 150MHz. > >I have also tried using the dongle on an ISA parallel port in these fast >machines but with no sucess. > >Thanks GeoffArticle: 5798
I'm maybe old fashion but I'm using PEEL16V8 and I'm trying to
compile a PDF file in Palasm package and I can't find that device in the
device list.
If there is any one out there that have that extension or knows how
to do that, that will be agreat help for me.
Thanx,
Gabby.
--
Gabby Shpirer
Digital Jerusalem
Article: 5799
Gabby Shpirer wrote:
>
> I'm maybe old fashion but I'm using PEEL16V8 and I'm trying to
> compile a PDF file in Palasm package and I can't find that device in the
> device list.
Hi,
A dumb question, I'm sure, but why aren't you using ICT's rather
wonderful ICTPLACE software? They give it away, it's far friendlier
than Palasm, with a worthwhile simulator, and will read PDFs in if you
want to convert. Have a rummage round http://www.ictpld.com, see if
there's a downloadable version or talk to your distributor. You'll also
be able to use the fun features of the ICT devices that Palasm doesn't
know about.
hope that helps,
Steve
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