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> So, is it possible to use clock pins as general-purpose inputs? For Altera Cyclone X, you can use clock-inputs as general-purpose inputs with some restrictions, most important: - No internal pullups possible - No fast I/O-register It is not possible to use them as output. I guess, the same applies also for the Arria-parts, but I have not double-checked. Regards, Thomas www.entner-electronics.comArticle: 152476
Hi, I would like to know which is the smallest (read cheapest) board with a Spartan3 that can be programmed directly by a usb cable. I just need a couple to test a design that must be operated remotely and in the need of a change in the fpga I would not bother the other party with much software/hardware issues. Budget is very tight, there are no many requirements for the board itself, a bunch of I/O (less than 20) and I would need to add a serial LCD, a couple of quad encoders and some buttons. Serial port and/or USB data exchange at plus. Ideally, I use a Xylo-LM that has a very easy programming method, sadly way overbudget. TIA. Giuseppe MarulloArticle: 152477
"Robert Baer" <robertbaer@localnet.com> wrote in message news:LdadnbDZuLc6WsTTnZ2dnUVZ_hCdnZ2d@posted.localnet... > Just because a program compiles does not mean it will work... It's not Xilinx, it's Altera.Article: 152478
On 8/28/2011 7:23 AM, Giuseppe Marullo wrote: > Hi, > I would like to know which is the smallest (read cheapest) board with a > Spartan3 that can be programmed directly by a usb cable. > > I just need a couple to test a design that must be operated remotely and > in the need of a change in the fpga I would not bother the other party > with much software/hardware issues. > > Budget is very tight, there are no many requirements for the board > itself, a bunch of I/O (less than 20) and I would need to add a serial > LCD, a couple of quad encoders and some buttons. > > Serial port and/or USB data exchange at plus. > > Ideally, I use a Xylo-LM that has a very easy programming method, sadly > way overbudget. > > TIA. > > Giuseppe Marullo I have been using Opal Kelly 3050 boards. They can be configured via USB, have IP that lets you do I/O through USB and have a reasonable number of I/O pins. The 3050 use Spartan XC33S4000 parts. There are 3010, 3005 and 3001 that have smaller parts on them, but I have not used them. They are not cheap, the 3050's are about $750 US. The smaller boards go down to $175 US. Their customer service is not stellar and their docs are kind of weak. Last time I contacted their customer service, I was told to RTFM until I told them that what I needed was not in the FM. Good Luck, BobHArticle: 152479
On 28/08/11 06:58, John Larkin wrote: > Hi, > > I'm designing a pretty horrible board (33 page schematic!) that will > use an Altera Arria II GX in the 572BGA package. There are 240 pure > I/O pins in this package, and 12 dedicated clock pins. I'm getting > close to using up all the i/o pins, and starting to do silly things to > save a pin here and there. Don't blame me, blame customer feature > creep! > > So, is it possible to use clock pins as general-purpose inputs? The > documentation doesn't say so, but it does imply somewhere that clock > nets can be used for non-clock functions like async resets, so there > should be some not-too-disgusting way to used them as slow static > inputs. > > Pity they didn't dual-purpose the clock pins. It's not often you need > 12 clocks. > > Any thoughts/experience here? > > Thanks > > John > > I think the people at comp.arch.fpga might be more experienced at this. WernerArticle: 152480
On Sun, 28 Aug 2011 08:11:22 +0100, "TTman" <pcw1.cad@ntlworld.com> wrote: > >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:3jsi579k5mhhectd2ej80jhme53h348ib5@4ax.com... >> Hi, >> >> I'm designing a pretty horrible board (33 page schematic!) that will >> use an Altera Arria II GX in the 572BGA package. There are 240 pure >> I/O pins in this package, and 12 dedicated clock pins. I'm getting >> close to using up all the i/o pins, and starting to do silly things to >> save a pin here and there. Don't blame me, blame customer feature >> creep! >> >> So, is it possible to use clock pins as general-purpose inputs? The >> documentation doesn't say so, but it does imply somewhere that clock >> nets can be used for non-clock functions like async resets, so there >> should be some not-too-disgusting way to used them as slow static >> inputs. >> >> Pity they didn't dual-purpose the clock pins. It's not often you need >> 12 clocks. >> >> Any thoughts/experience here? >> >> Thanks >> >> John >> >> >Does PS boot mode save a pin or two ?.. > We're doing that already... a mere 29 million bits! JohnArticle: 152481
On Sun, 28 Aug 2011 02:32:47 -0700 (PDT), Thomas Entner <thomas.entner99@gmail.com> wrote: > >> So, is it possible to use clock pins as general-purpose inputs? > >For Altera Cyclone X, you can use clock-inputs as general-purpose >inputs with some restrictions, most important: >- No internal pullups possible >- No fast I/O-register > >It is not possible to use them as output. > >I guess, the same applies also for the Arria-parts, but I have not >double-checked. > >Regards, > >Thomas > >www.entner-electronics.com The Arria GZ parts say specifically that clock pins can be I/Os. It's not clear on the GX if they can be inputs. We're using the A2 45GX. My schematic names signals like SIG3_F for FPGA i/o SIG4_FS serdes SIG5_FD special/dedicated SIG6_FI FPGA input, i/o or (maybe) clock pin and I let The Brat (our layout person) pick whichever FPGA pins that route best. There's an ARM processor with similar rules, SIG5_U etc. JohnArticle: 152482
On Sun, 28 Aug 2011 18:06:39 +0300, "scrts" <mailsoc@[remove@here]gmail.com> wrote: > >"Robert Baer" <robertbaer@localnet.com> wrote in message >news:LdadnbDZuLc6WsTTnZ2dnUVZ_hCdnZ2d@posted.localnet... >> Just because a program compiles does not mean it will work... > >It's not Xilinx, it's Altera. > Ohhh, that was mean. True, but mean. JohnArticle: 152483
On Mon, 29 Aug 2011 00:47:56 +0800, Werner <wdahn@netfront.net> wrote: >On 28/08/11 06:58, John Larkin wrote: >> Hi, >> >> I'm designing a pretty horrible board (33 page schematic!) that will >> use an Altera Arria II GX in the 572BGA package. There are 240 pure >> I/O pins in this package, and 12 dedicated clock pins. I'm getting >> close to using up all the i/o pins, and starting to do silly things to >> save a pin here and there. Don't blame me, blame customer feature >> creep! >> >> So, is it possible to use clock pins as general-purpose inputs? The >> documentation doesn't say so, but it does imply somewhere that clock >> nets can be used for non-clock functions like async resets, so there >> should be some not-too-disgusting way to used them as slow static >> inputs. >> >> Pity they didn't dual-purpose the clock pins. It's not often you need >> 12 clocks. >> >> Any thoughts/experience here? >> >> Thanks >> >> John >> >> > >I think the people at comp.arch.fpga might be more experienced at this. > >Werner Right. I did crosspost there. JohnArticle: 152484
On Sun, 28 Aug 2011 10:10:00 -0700, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Sun, 28 Aug 2011 18:06:39 +0300, "scrts" ><mailsoc@[remove@here]gmail.com> wrote: > >> >>"Robert Baer" <robertbaer@localnet.com> wrote in message >>news:LdadnbDZuLc6WsTTnZ2dnUVZ_hCdnZ2d@posted.localnet... >>> Just because a program compiles does not mean it will work... >> >>It's not Xilinx, it's Altera. >> > >Ohhh, that was mean. True, but mean. Even Xilinx will tell you about illegal I/O assignments.Article: 152485
On Sun, 28 Aug 2011 10:08:19 -0700, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Sun, 28 Aug 2011 02:32:47 -0700 (PDT), Thomas Entner ><thomas.entner99@gmail.com> wrote: > >> >>> So, is it possible to use clock pins as general-purpose inputs? >> >>For Altera Cyclone X, you can use clock-inputs as general-purpose >>inputs with some restrictions, most important: >>- No internal pullups possible >>- No fast I/O-register >> >>It is not possible to use them as output. >> >>I guess, the same applies also for the Arria-parts, but I have not >>double-checked. >> >>Regards, >> >>Thomas >> >>www.entner-electronics.com > >The Arria GZ parts say specifically that clock pins can be I/Os. It's >not clear on the GX if they can be inputs. We're using the A2 45GX. > >My schematic names signals like > >SIG3_F for FPGA i/o >SIG4_FS serdes >SIG5_FD special/dedicated >SIG6_FI FPGA input, i/o or (maybe) clock pin > >and I let The Brat (our layout person) pick whichever FPGA pins that >route best. There's an ARM processor with similar rules, SIG5_U etc. Are you using I/O banking? I tend to code such things into the schematic symbol, rather than signal names. Also, be careful if you use external RAM I/O macros. Some of these are picky about I/O assignments.Article: 152486
On Sun, 28 Aug 2011 12:38:07 -0500, "krw@att.bizzzzzzzzzzzz" <krw@att.bizzzzzzzzzzzz> wrote: >On Sun, 28 Aug 2011 10:08:19 -0700, John Larkin ><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On Sun, 28 Aug 2011 02:32:47 -0700 (PDT), Thomas Entner >><thomas.entner99@gmail.com> wrote: >> >>> >>>> So, is it possible to use clock pins as general-purpose inputs? >>> >>>For Altera Cyclone X, you can use clock-inputs as general-purpose >>>inputs with some restrictions, most important: >>>- No internal pullups possible >>>- No fast I/O-register >>> >>>It is not possible to use them as output. >>> >>>I guess, the same applies also for the Arria-parts, but I have not >>>double-checked. >>> >>>Regards, >>> >>>Thomas >>> >>>www.entner-electronics.com >> >>The Arria GZ parts say specifically that clock pins can be I/Os. It's >>not clear on the GX if they can be inputs. We're using the A2 45GX. >> >>My schematic names signals like >> >>SIG3_F for FPGA i/o >>SIG4_FS serdes >>SIG5_FD special/dedicated >>SIG6_FI FPGA input, i/o or (maybe) clock pin >> >>and I let The Brat (our layout person) pick whichever FPGA pins that >>route best. There's an ARM processor with similar rules, SIG5_U etc. > >Are you using I/O banking? I tend to code such things into the schematic >symbol, rather than signal names. Also, be careful if you use external RAM >I/O macros. Some of these are picky about I/O assignments. All the banks are 3.3 volts, and no DRAM, so any i/o pin is as good as any other. The main clock is a mere 125 MHz. The schematic symbol for the FPGA is in fact a bunch of separate blocks, "gates" to PADS: a couple for PCIe, one for each i/o bank, one for core power, one for ground, one for config. Each bank block has its own Vccio pins. We are doing PCI Express, but those pins are hard dedicated, so I can assign off-pages to the specific FPGA pins involved, locking them down, and preplan the routing for those. JohnArticle: 152487
Giuseppe, take a look at the XULA from Xess: http://www.xess.com/prods/prod048.php They have a cheaper version which is exactly like this but has a smaller FPGA. I don't have any experience with this board myself, but have a much older board from them (the XSA-100) which I like a lot. -- JecelArticle: 152488
Giuseppe Marullo wrote: >I would like to know which is the smallest (read cheapest) board with a >Spartan3 that can be programmed directly by a usb cable. Probably not what you have in mind: < $200 ? http://www.kickstarter.com/projects/794668827/aliencortex-av $75 for 500K http://papilio.cc/index.php?n=Papilio.Papilio -- Roberto Waltman [ Please reply to the group, return address is invalid ]Article: 152489
On Sun, 28 Aug 2011 10:49:03 -0700, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Sun, 28 Aug 2011 12:38:07 -0500, "krw@att.bizzzzzzzzzzzz" ><krw@att.bizzzzzzzzzzzz> wrote: > >>On Sun, 28 Aug 2011 10:08:19 -0700, John Larkin >><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sun, 28 Aug 2011 02:32:47 -0700 (PDT), Thomas Entner >>><thomas.entner99@gmail.com> wrote: >>> >>>> >>>>> So, is it possible to use clock pins as general-purpose inputs? >>>> >>>>For Altera Cyclone X, you can use clock-inputs as general-purpose >>>>inputs with some restrictions, most important: >>>>- No internal pullups possible >>>>- No fast I/O-register >>>> >>>>It is not possible to use them as output. >>>> >>>>I guess, the same applies also for the Arria-parts, but I have not >>>>double-checked. >>>> >>>>Regards, >>>> >>>>Thomas >>>> >>>>www.entner-electronics.com >>> >>>The Arria GZ parts say specifically that clock pins can be I/Os. It's >>>not clear on the GX if they can be inputs. We're using the A2 45GX. >>> >>>My schematic names signals like >>> >>>SIG3_F for FPGA i/o >>>SIG4_FS serdes >>>SIG5_FD special/dedicated >>>SIG6_FI FPGA input, i/o or (maybe) clock pin >>> >>>and I let The Brat (our layout person) pick whichever FPGA pins that >>>route best. There's an ARM processor with similar rules, SIG5_U etc. >> >>Are you using I/O banking? I tend to code such things into the schematic >>symbol, rather than signal names. Also, be careful if you use external RAM >>I/O macros. Some of these are picky about I/O assignments. > >All the banks are 3.3 volts, and no DRAM, so any i/o pin is as good as >any other. The main clock is a mere 125 MHz. > >The schematic symbol for the FPGA is in fact a bunch of separate >blocks, "gates" to PADS: a couple for PCIe, one for each i/o bank, one >for core power, one for ground, one for config. Each bank block has >its own Vccio pins. Sure, I do the same, except I'll break things down into functional blocks rather than just along bank boundaries. I never reuse symbols for FPGAs. You can still code the pin-swapping information into the pin names. >We are doing PCI Express, but those pins are hard dedicated, so I can >assign off-pages to the specific FPGA pins involved, locking them >down, and preplan the routing for those. Sure, name them with their function and I/O pin number and mark them as non-swappable. Again, there is no need to identify these pins by their signal names. Doesn't hurt, just adds more mess to the naming convention.Article: 152490
Thanks to all for your answers, really good advices. I need a very cheap board, so Papilio and/or Xula are best suited for the task (2 x 175$ is too much, I could buy another Xylo-LM). I need to build a "high speed" HST IAMBIC keyer. The device is very simple, 2 digital input for the paddles and some user interface to set the WPM speed, sensitivity and sidetone frequency. The output will be one digitally optocoupled and a little amplified loudspeaker. The device must be standalone in operation, without a computer so probably a serial 16x2 LCD will provide feedback. It needs to be tested by a skilled "brass pounder", that does not know much of fpga and is 600km apart. I don't want him to experience the wonderful parallel cable circus, every time he discover something to be changed, that's the reason for the USB programming. I would like to have a twin system to remotely help him to update the bitfile, thus the need of a cheap board, since I have to buy two. I just have the basic stuff working, still need to add the LCD and the encoders to let the user to set the WPM and so on and I doubt it will fit in the 50k part. Xula is really low price, small and give me most of what I want (except maybe usb data transfer), and even DRAM. Papilio, on the other side, has a serial port embedded into the USB but lacks the DRAM (that I don't need) and is much bigger (250k is really okay). If Xula would be able to talk with a program using just the USB could be the best fit, otherwise Papilio. Any other contender? Giuseppe MarulloArticle: 152491
On Aug 28, 6:47=A0pm, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > Thanks to all for your answers, really good advices. > > I need a very cheap board, so Papilio and/or Xula are best suited for > the task (2 x 175$ is too much, I could buy another Xylo-LM). > > I need to build a "high speed" HST IAMBIC keyer. > > The device is very simple, 2 digital input for the paddles and some user > interface to set the WPM speed, sensitivity and sidetone frequency. > The output will be one digitally optocoupled and a little amplified > loudspeaker. The device must be standalone in operation, without a > computer so probably a serial 16x2 LCD will provide feedback. This isn't an appropriate FPGA application, unless your keyer needs to work at 50,000,000 words per minute. Look into the Arduino family of microcontroller boards, maybe? -- john, KE5FXArticle: 152492
On 8/28/2011 6:47 PM, Giuseppe Marullo wrote: > Thanks to all for your answers, really good advices. > > I need a very cheap board, so Papilio and/or Xula are best suited for > the task (2 x 175$ is too much, I could buy another Xylo-LM). > > I need to build a "high speed" HST IAMBIC keyer. > > The device is very simple, 2 digital input for the paddles and some user > interface to set the WPM speed, sensitivity and sidetone frequency. > The output will be one digitally optocoupled and a little amplified > loudspeaker. The device must be standalone in operation, without a > computer so probably a serial 16x2 LCD will provide feedback. > > It needs to be tested by a skilled "brass pounder", that does not know > much of fpga and is 600km apart. > > I don't want him to experience the wonderful parallel cable circus, > every time he discover something to be changed, that's the reason for > the USB programming. > > I would like to have a twin system to remotely help him to update the > bitfile, thus the need of a cheap board, since I have to buy two. > > I just have the basic stuff working, still need to add the LCD and the > encoders to let the user to set the WPM and so on and I doubt it will > fit in the 50k part. > > Xula is really low price, small and give me most of what I want (except > maybe usb data transfer), and even DRAM. > > Papilio, on the other side, has a serial port embedded into the USB but > lacks the DRAM (that I don't need) and is much bigger (250k is really > okay). > > If Xula would be able to talk with a program using just the USB could be > the best fit, otherwise Papilio. > > Any other contender? > > > Giuseppe Marullo This seems like an ideal application for a microcontroller. NXP is selling some little ARM M0 demo boards for $30US and ST is selling some ARM M3 demo boards for $12US. The NXP uses GCC and Eclipse open source tool chains and the ST board uses an IAR demo version. Both have generous amounts of Flash memory for code and RAM. Both use USB for programming and debugging. '73 BobH KE7FEFArticle: 152493
On 8/28/2011 7:23 PM, John Miles wrote: > On Aug 28, 6:47 pm, Giuseppe Marullo > <giuseppe.marullonos...@iname.com> wrote: >> Thanks to all for your answers, really good advices. >> >> I need a very cheap board, so Papilio and/or Xula are best suited for >> the task (2 x 175$ is too much, I could buy another Xylo-LM). >> >> I need to build a "high speed" HST IAMBIC keyer. >> >> The device is very simple, 2 digital input for the paddles and some user >> interface to set the WPM speed, sensitivity and sidetone frequency. >> The output will be one digitally optocoupled and a little amplified >> loudspeaker. The device must be standalone in operation, without a >> computer so probably a serial 16x2 LCD will provide feedback. > > This isn't an appropriate FPGA application, unless your keyer needs to > work at 50,000,000 words per minute. Look into the Arduino family of > microcontroller boards, maybe? > > -- john, KE5FX Sorry John. I have to disagree here. It might just be that an Arduino would be less expensive - maybe not - but this is a perfect project for someone who is into Ham Radio and wants to learn about FPGAs/CPLDS and/or HDLs. The basic iambic keyer with dot and dash memories will fit in a Xilinx XC9536XL which is $1.18. I don't think you can build an Arduino for that price. I actually used a Digilent Nexys2 board for my keyer. Then I added a PS/2 keyboard interface so I could type. Then I added a split-screen Color VGA display (128 x 64 characters). I use the display memory for receive and transmit buffers. Someday I'll add the signal processing for a tone decoder and then morse code decoder. Yes it is a little weird to do this with a 50 MHz clock but then again the clock is PLL'd to 108.33 MHz for the VGA pixel clock... I use the Nexys2 board just because it is fast and easy (i.e., fun). Later I'll build a circuit card. ... it's better than a vending machine or a traffic light. Rob. WA3TGF.Article: 152494
Giuseppe Marullo <giuseppe.marullonospam@iname.com> wrote: > Any other contender? DLP Design have two modules, but IMO they're kind of expensive for what you're getting: <http://www.dlpdesign.com/fpga/> Avnet's Spartan-3A Evaluation Kit was cheap, but I'm not sure if it's available anymore. Software support was also kind of iffy. <http://www.xilinx.com/products/boards-and-kits/aes_sp3a_eval400_avnet.htm> -aArticle: 152495
On 08/29/2011 12:23 AM, Giuseppe Marullo wrote: > Hi, > I would like to know which is the smallest (read cheapest) board with a > Spartan3 that can be programmed directly by a usb cable. > > I just need a couple to test a design that must be operated remotely and > in the need of a change in the fpga I would not bother the other party > with much software/hardware issues. > > Budget is very tight, there are no many requirements for the board > itself, a bunch of I/O (less than 20) and I would need to add a serial > LCD, a couple of quad encoders and some buttons. > > Serial port and/or USB data exchange at plus. > > Ideally, I use a Xylo-LM that has a very easy programming method, sadly > way overbudget. > > TIA. > > Giuseppe Marullo Not Spartan 3 but Spartan 6: http://www.sioi.com.au/shop/product_info.php/products_id/47 28.13 euros for a Spartan 6, 4Mb Flash, 32MB DDR SDRAM, 38 IO expansion plus separate 6 IO expansion You can program it with a JTAG cable that has the Xilinx 14 pin JTAG connector. StephenArticle: 152496
>> Any other contender? > > DLP Design have two modules, but IMO they're kind of expensive for what > you're getting:<http://www.dlpdesign.com/fpga/> Yes, expensive compared to Xula and/or Papilio, I did know about them, nice product. > > Avnet's Spartan-3A Evaluation Kit was cheap, but I'm not sure if it's > available anymore. Software support was also kind of iffy. > <http://www.xilinx.com/products/boards-and-kits/aes_sp3a_eval400_avnet.htm> > > -a I was not able to locate one either, and I would like a reasonable support. >This isn't an appropriate FPGA application, unless your keyer needs to >work at 50,000,000 words per minute. Look into the Arduino family of >microcontroller boards, maybe? > >-- john, KE5FX John, you are right, but I should have said that this is not a commercial product, just a hw shell for a "virtual keyer". Once the design would be proven ok, I could release under GPL / openhardware and everyone would implement it as they please. I already have a K42 from www.k1el.com that performs flawlessly at human speeds (up to 60-100 WPM) but this is done for different reasons: 1) HST competitions Look here: http://www.youtube.com/watch?v=wUBGrO9Vs1k&feature=related Probably your Arduino could have some problem with gals like these... 2) Learn Verilog and testbenches I have a very basic knowledge of both (and sometimes you could see my naif questions in this newsgroup) 3) Try to build a "absolute precision" keyer, sometimes a pic or arduino seems not perfect. I want the maximum precision available in terms of uniformity of response and timing accuracy 4) wet my feet for building a standaline CW decoder, that seems so rare animal this days. If I wanted a fast MCU, I would have just used a Isopod that would have done a very fast keyer without hassles in minutes using IsoMax/Forth. >This seems like an ideal application for a microcontroller. NXP is >selling some little ARM M0 demo boards for $30US and ST is selling >some ARM M3 demo boards for $12US. The NXP uses GCC and Eclipse open >source tool chains and the ST board uses an IAR demo version. Both >have generous amounts of Flash memory for code and RAM. Both use USB >for programming and debugging. I wanted it to be a cheap FPGA project, so a MCU is not an option anyway. I have a LPC2138 and I got sick trying to put RTOS on it, my FPGA board does have it side by side of a Spartan 3E 500 and would be a very powerful combination. I regularly lose myself in the quirk of Eclipse/ZC something plugin for debugging, makefiles and so on. >It might just be that an Arduino would be less expensive - maybe not - >but this is a perfect project for someone who is into Ham Radio and >wants to learn about FPGAs/CPLDS and/or HDLs. >Rob. WA3TGF. Bingo! Maybe I didn't say it explicitly but this is the reason, plus the fact that a FPGA is way more "realtime" than a MCU. I would like to talk with you offlist, please contact me at giuseppe.marullo @ nospam.iname.com (remove nospam.) Great info, great people here (as always)! Giuseppe Marullo IW2JWW - JN45RQArticle: 152497
On Aug 29, 12:08=A0am, Rob Doyle <radioe...@gmail.com> wrote: > On 8/28/2011 7:23 PM, John Miles wrote: > > > > > > > > > > > On Aug 28, 6:47 pm, Giuseppe Marullo > > <giuseppe.marullonos...@iname.com> =A0wrote: > >> Thanks to all for your answers, really good advices. > > >> I need a very cheap board, so Papilio and/or Xula are best suited for > >> the task (2 x 175$ is too much, I could buy another Xylo-LM). > > >> I need to build a "high speed" HST IAMBIC keyer. > > >> The device is very simple, 2 digital input for the paddles and some us= er > >> interface to set the WPM speed, sensitivity and sidetone frequency. > >> The output will be one digitally optocoupled and a little amplified > >> loudspeaker. The device must be standalone in operation, without a > >> computer so probably a serial 16x2 LCD will provide feedback. > > > This isn't an appropriate FPGA application, unless your keyer needs to > > work at 50,000,000 words per minute. =A0Look into the Arduino family of > > microcontroller boards, maybe? > > > -- john, KE5FX > > Sorry John. =A0I have to disagree here. > > It might just be that an Arduino would be less expensive - maybe not - > but this is a perfect project for someone who is into Ham Radio and > wants to learn about FPGAs/CPLDS and/or HDLs. > I don't disagree there, but... > The basic iambic keyer with dot and dash memories will fit in a Xilinx > XC9536XL which is $1.18. =A0I don't think you can build an Arduino for > that price. ... he started out asking for a Spartan3 board, which is a bit much if he wants to build a keyer and be done with it. He didn't mention that he wanted to learn about FPGA development, but he *did* mention that he had a tight budget, so... horses for courses. > I actually used a Digilent Nexys2 board for my keyer. =A0Then I added > a PS/2 keyboard interface so I could type. =A0Then I added a split-screen > Color VGA display (128 x 64 characters). =A0I use the display memory for > receive and transmit buffers. =A0Someday I'll add the signal processing > for a tone decoder and then morse code decoder. =A0Yes it is a little > weird to do this with a 50 MHz clock but then again the clock is PLL'd > to 108.33 MHz for the VGA pixel clock... > > I use the Nexys2 board just because it is fast and easy (i.e., fun). > Later I'll build a circuit card. > > ... it's better than a vending machine or a traffic light. > > Rob. =A0WA3TGF. Yep, Nexys2s are great boards. Good for climbing the USB learning curve as well as coming up to speed on FPGAs. Very well documented, and very inexpensive considering what you get... -- john, KE5FXArticle: 152498
Steve wrote: > On 08/29/2011 12:23 AM, Giuseppe Marullo wrote: >> Hi, >> I would like to know which is the smallest (read cheapest) board with a >> Spartan3 that can be programmed directly by a usb cable. >> >> I just need a couple to test a design that must be operated remotely and >> in the need of a change in the fpga I would not bother the other party >> with much software/hardware issues. >> >> Budget is very tight, there are no many requirements for the board >> itself, a bunch of I/O (less than 20) and I would need to add a serial >> LCD, a couple of quad encoders and some buttons. >> >> Serial port and/or USB data exchange at plus. >> >> Ideally, I use a Xylo-LM that has a very easy programming method, sadly >> way overbudget. >> >> TIA. >> >> Giuseppe Marullo > > Not Spartan 3 but Spartan 6: > > http://www.sioi.com.au/shop/product_info.php/products_id/47 > > 28.13 euros for a Spartan 6, 4Mb Flash, 32MB DDR SDRAM, 38 IO expansion > plus separate 6 IO expansion > > You can program it with a JTAG cable that has the Xilinx 14 pin JTAG > connector. > > Stephen > Another spartan 6 possibility with the USB built-in: http://www.em.avnet.com/ctf_shared/evk/df2df2usa/xlx-s6-lx9-microboard-pb040811.pdf $89.00 US at Avnet. I'm not sure if the 2 PMOD connectors have enough I/O for you, though. -- GaborArticle: 152499
Hi, i wanted to know whether there exists any software that can be used to know whether all the balls of my bga grid are properly fixed in place or not. Actually i am using spartan 3 xc3s4000 and maxim 28544 in my design and i cannot program the maxim through FPGA. When same code is used on another design, maxim gets programmed. So it made me think to look for some kind of software that can tell me if there's exists a connection between my FPGA and maxim.Or in other words it can verify if my FPGA stuffing is right or not. Regards --------------------------------------- Posted through http://www.FPGARelated.com
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