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While I don't see one on their web page, I would try VAutomation. You can find their web site at: http://www.vautomation.com -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Tore H. Larsen <thl@scase.no> wrote in article <333A2CC5.6747@scase.no>... | Hi, | anyone know if Xilinx or Atmel or any other FPGA producers | have 6809 MPU-core support? | | Tore | -- | ####\ Tore H. Larsen | #@ * > Scase AS - Bergen - Norway | # _" E-mail: thl@internet.no or torela@idt.ntnu.no | ##### Vc: +47-55951200 | |Article: 5951
The license code written into a schematic file is based on the license file not on the contents of the schematic. Even an empty schematic file generated by a 'full' Workview should fail to load into a restricted Actel seat. ViewDraw does not have the ability to analyze the design and adjust this code. Another work-around would be to generate empty schematic sheets with one of the Actel seats. These files should then be useable by all and the restrictive license code should be retained. (Of course, you would want to test this.) I doubt that VL would change ViewDraw itself, but maybe they could create a small utility to analyze and mung your files after the fact. P.S. As a Viewlogic stockholder, I recommend sending them more money.Article: 5952
|The license code written into a schematic file is based on the license |file not on the contents of the schematic. Even an empty schematic file |generated by a 'full' Workview should fail to load into a restricted |Actel seat. ViewDraw does not have the ability to analyze the design |and adjust this code. A program which "fixes-up" the magic number in Viewdraw's schematic files (and allows designs done in a "full" version to load in one of the restricted versions) has been circulating in the EDA industry for as long as Viewdraw has been around. It has been used to enable tech support of users of the "full" Viewdraw, who send in schematics which the sales office is unable to open using their restricted version. Obviously its existence is supposed to be secret. I know someone who has a copy which is about 7-8 years old, did work but doesn't work now, most likely because it is totally program version specific. It is a small program, so it would not be hard to disassemble. As far as I can tell, the magic number is based on the restricted vendor name (e.g. "Actel" or "Xilinx" etc) and some other stuff. This also prevents designs done on an Actel-restricted WV being opened on a Xilinx-restricted WV. |Another work-around would be to generate empty schematic sheets with one |of the Actel seats. These files should then be useable by all and the |restrictive license code should be retained. (Of course, you would want |to test this.) This wont work, I am sure. A company which tries so hard to screw every cent out of every customer would not make such a basic mistake. Also, the magic number includes the filename, so this would be a real pain even if it worked.Article: 5953
Peter wrote: > Like most (not all) people who use digital logic, I have no use for a > 500k gate device now, in 1998, and almost certainly not in 2005 > either. > > Peter. > I could use 500K gates yesterday. The problem is that the FPGA version would likely spew forth molten silicon as soon as it got near my target clock rate of 125 MHz. I want fast, dense, and low power. At these clock rates, power (hence heat) is a real problem. This will probably become the decision factor in Custom/Standard/Array/FPGA choices. Low voltage helps, but FPGAS will always have a lot of capacitive overhead in programmable interconnect. I wish them the best, but you can't fool mother nature (unless you are really clever) regards, tomArticle: 5954
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Article: 5957
Hi, VHDL friends:
I have successfully simulated a 8085 VHDL model in Synopsys.
But when the design_analyzer complained about clock rising
edge specification when synthesizing it. The error msg is:
The use of clock edge specification not supported.
The design lines are as follows:
-------------------------------------
elsif (X1 = '1') and (not X1'stable) then -- Begin processing on
--positive edge of clock
CLKOUT <= '0' after 1 ns;
--if bit2int(TSTATES) = 1 then ALE <= '1'; end if;
if TSTATES = "0001" then ALE <= '1'; end if;
-------------------------------------
How to model rising edges? Thanks a lot! -- Jian
Article: 5958Hello every one: For the past 15 months major FPGA manufacturers have been shifting their process thechnologies from 0.8u to all the way down to 0.35u. This has resulted in an order of magnitude increase in the gate count for the highest density FPGAs. Are the FPGAs in a position to offer a cost-effective hassle-free solution to system level integration compared to ASICs and gate arrays for densities below 100K and volumes of less than 5K? Can the tools easily handle different IP cores from different providers? Has any one implemented multiple IP cores in one FPGA? Any comments are appreciated. Regards, Kayvon Irani Los AngelesArticle: 5959
Tore H. Larsen wrote: > > Hi, > anyone know if Xilinx or Atmel or any other FPGA producers > have 6809 MPU-core support? What sort of "support" are you looking for? suport in interfacing to a 6809 or a synthesizable 6809 itself. We have synthesizable 8 and 16 bit microprocessors available now. Unfortunately, Moto has a very large legal staff and lots of patents on even their old micros like the 6809. So... even if you find someone with a synthesizable 6809, you really can't use it or Moto will be on your case so fast you won't know what hit you! Another problem is that any 8 bit microprocessor is MUCH cheaper using the original silicon rather than implementing it in an FPGA. Micros require a lot of decode logic which FPGAs are really terrible at. Our tiny 6502 8 bit uProc which is only 4000 ASIC gates requires an entire Xilinx 4010 or 32% of an ALtera 10K50! -- Eric Ryherd eric@vautomation.com VAutomation Inc. Synthesizable VHDL and Verilog Cores 20 Trafalgar Sq. #443 http://www.vautomation.com Nashua NH 03063 (603) 882-2282 FAX:882-1587Article: 5960
In article <3336073E.5444@geocities.com>, Christos Dimitrakakis <olethros@geocities.com> wrote: > My largest problem now is that the registers must be loadable with new > values. > Erm.. how am I going to do that without multiplexing? What's wrong with multiplexing? Don't forget, in the Xilinx architecture, you have a "free" 4-input look-up table in front of each register bit. So multiplexing may perhaps not cost anything. I still don't understand what you are doing in detail... Peter Alfke, Xilinx ApplicationsArticle: 5961
In article <333E43D7.710@bc.sympatico.ca>, Tom Burgess <Tom_Burgess@bc.sympatico.ca> wrote: . Low voltage helps, but FPGAS will always have a lot of > capacitive overhead in programmable interconnect. I wish them the > best, but you can't fool mother nature (unless you are really clever) > Then let's try to be really clever. I think ( and there will be exceptions ) that 500 000 gates usually don't all have to move at 125 MHz. Designers will have to put some thoughts into that. Unnecessary movement of internal and external nodes causes unnecessary heat, and the designer should reduce such unnecessary movement. Just because a circuit has a short delay does not mean one should always exercise it at that rate. Smart guys know that, but it bears repeating, because this power limitation is new to most of us. Peter Alfke, Xilinx ApplicationsArticle: 5962
I am with Human Resources for the Small Internetworks Business Unit (formerly Grand Junction) at Cisco Systems. We develop switches, routers, and hubs that focus on small and medium-sized companies. Revenue-wise we are the fastest growing Business Unit at Cisco Systems with 30+% growth over the last five quarters. We are currently looking for senior and intermediate ASIC Engineers (digital) as well as senior and intermediate Systems Engineers (embedded CPU, FPGA) to join our team. We are located in San Jose, California. If you, or anyone you know is interested, please contact me or send me your resume. I will be happy to talk with you further about the positions. To send your resume: fax: 408-527-8048 or email: lshevock@cisco.com No agencies please -- To send your resume: fax: 527-0180 or email: lshevock@cisco.com No agencies pleaseArticle: 5963
>I could use 500K gates yesterday. I realise this is getting off-topic, but what are you putting inside those 500k gates? I would say probably not random logic. It would take years to design. Much more likely it will be RAM, a CPU, or something like that. In both these cases the equivalent RAM or a CPU will be *far* cheaper to have externally. Even with ASICs (which in volume are far cheaper than FPGAs) this is generally true. I have spent a lot of time looking at costs of putting things like that in ASICs, and unless one is going for a million + pieces, and gets very close to a vendor who offers both ASICs and the CPU and really wants your business, it is not worth doing. OTOH, if money is no object, I can see plenty of uses for a 500k gate FPGA. But most users are not in that category. There is one exception: ASIC prototyping. But even then a 500k-gate ASIC would generally be filled with RAM/ROM/CPU or some other regular structure, so the main advantage of FPGA prototyping (a simple netlist transfer) is lost because such large blocks tend to be done separately, and in the case of most CPU cores the developer is not allowed to see the netlist anyway. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5964
Peter wrote: > > >I could use 500K gates yesterday. > > I realise this is getting off-topic, but what are you putting inside > those 500k gates? What do you think is in those hot new 3-D graphics Chips. I worked on a project where we had two 300K parts we wished we could put into one 500K part because of the overhead associated with transfering data between the two. > > I would say probably not random logic. It would take years to design. > Much more likely it will be RAM, a CPU, or something like that. In > both these cases the equivalent RAM or a CPU will be *far* cheaper to > have externally. A specific algorthim which can be defined works good. Some would say it's ramdom logic. To look at the die picture I have you would say it is random logic, but instead it is a bunch of adders, multipliers, dividers and control logic. > > Even with ASICs (which in volume are far cheaper than FPGAs) this is > generally true. I have spent a lot of time looking at costs of putting > things like that in ASICs, and unless one is going for a million + > pieces, and gets very close to a vendor who offers both ASICs and the > CPU and really wants your business, it is not worth doing. Functionality per package. If you have a market that needs a small footprint then they are willing to pay the price. I agree with you when I analyze the cost of ASIC's I often wonder why! But there are more reasons then cost. Reguarding the power problem it is a real problem. If that 300K device that I worked on had a pipeline stage for every math element then the power disipation would be around 20 Watts...instead I took a multi-cycle design approach and the power was a managable 10 Watts. The bigger they get the more power they want! Why do you think all the FPGA manufactures are coming out with 3.3V parts? It's not that they think 3.3V systems will take over the world its that they needed to reduce the power from the devices. Happy Designing Tom Tessier -- +-----------------------------------------------------------------------+ : ttessier@talcian.com | Phone: 303.440.0570 : : Thomas Tessier | FAX: 303.441.5811 : : | WWW: http://www.talcian.com : +------------------------Have a nice Day--------------------------------+Article: 5965
Kayvon Irani wrote: > > Hello every one: > > For the past 15 months major FPGA manufacturers have been shifting their > process thechnologies from 0.8u to all the way down to 0.35u. This has resulted > in an order of magnitude increase in the gate count for the highest density > FPGAs. Are the FPGAs in a position to offer a cost-effective hassle-free > solution to system level integration compared to ASICs and gate arrays for > densities below 100K and volumes of less than 5K? Can the tools easily handle > different IP cores from different providers? Has any one implemented multiple > IP cores in one FPGA? Any comments are appreciated. By IP Cores do you mean soft/firm/hard cores. The problems I see are that soft cores have been designed with ASIC technologies in mind and they don't necessarily migrate well into an FPGA chip. Most FPGA IP are in the form of Hard cores that is everyone has an implementation of the PCI bus. Do they all have an implementation of a 6502 uController or a customized DSP? Which tools are you talking about? The FPGA backend tools...lets hope they can place and route the largest design. The synthesis tools...If you have a workstation then you are OK but what about NT solutions? I think for any system solution the trade-offs need to be made. Your target of 100K in volumes of 5K looks good but lets say that in order to take the market you need a 250MHz design. You can't do that with an FPGA. I also posed this question to the Design SuperCon97 panel on IP Cores but they were at a loss to answer. I think most people are still using 1-core from 1-vendor per chip...but that has got to change with 1M+ gates available now. So the question still stands anyone willing to talk about multiple IP from different sources? Tom Tessier -- t2design 249 Lois Drive Louisville, CO 80027 +-----------------------------------------------------------------------+ : ttessier@talcian.com | Phone: (303)665-6402 : : Thomas Tessier | FAX: (303)441-5811 : +------------------------Have a nice Day--------------------------------+Article: 5966
I recently purchased a second hand 486 and found a larg( network?)ISA card in it.On the biggest chip is inscribed XILINX xc2018-50.Can somenone tell me what it is and what it is worth? WimArticle: 5967
It is an FPGA (Field Programmable Gate Array), of about 1800 gate equivelents (hence xx18) and is worth about $2. Austin Franklin ..darkroom@ix.netcom.com. Wim Vanderstraeten <win@netwise.be> wrote in article <5hpa1q$pb4@news2.Belgium.EU.net>... > I recently purchased a second hand 486 and found a larg( network?)ISA > card in it.On the biggest chip is inscribed XILINX xc2018-50.Can > somenone tell me what it is and what it is worth? > Wim > > >Article: 5968
Hi, As a part of our course project we are required to develop a download software to download data in the .mcs file to the XC3020 PCB. This is what we gather from manuals regarding the .mcs file format obtained using XACT s/w: o First line == Info regarding the format of the file o From the second to the last but one line the data in every line will look as below:- :YYxxxxxxTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTgg <----------- YY no of bytes --------> where + every symbol is one nibble of data + gg is the validation constraint + TT is the data byte to be downloaded on to the xc3020 o Last line == Info regarding the format of the file We have a query here. Does the TT data bytes include the format of transferring the data like the preamble, start bits, stop bits, etc. If not then we have realised that the number of data bytes(TT) to be downloaded is more than what is expected. Then there must be some bits in the TT data bytes which have to be neglected. If the preamble, start & stop bits are indeed in the TT data bytes then we have observed in the .mcs file that the first 5 TT data bytes in the second line which will be the (preamble + length count + 4 high bits) is different from what is specified in the data book for xc3020. Can anybody throw some light on this ? Thanks in advance for any help -Abhinav Kumar (E-mail : abhinav@cse.iitb.ernet.in)Article: 5969
Jian Shen wrote: > > Hi, VHDL friends: > > I have successfully simulated a 8085 VHDL model in Synopsys. > But when the design_analyzer complained about clock rising > edge specification when synthesizing it. The error msg is: > The use of clock edge specification not supported. > > The design lines are as follows: > ------------------------------------- > elsif (X1 = '1') and (not X1'stable) then -- Begin processing on > --positive edge of clock > CLKOUT <= '0' after 1 ns; > --if bit2int(TSTATES) = 1 then ALE <= '1'; end if; > if TSTATES = "0001" then ALE <= '1'; end if; > ------------------------------------- > > How to model rising edges? Thanks a lot! -- Jian The supported clock edge specification supported by Synopsys (that I am aware of) is the following: elsif X1'event and X1 = '1' then -- rewrite of above line There may be others, but this works. -- Regards, Brandon Azbell Texas Instruments Technical Staff - ASIC Applications and Design Chicago Design Center b-azbell@ti.comArticle: 5970
On Wed, 26 Mar 1997 15:04:27 -0700, Vitit Kantabutra
<cad@inventor.isu.edu> wrote:
Hi,
>I have a new algorithm for division that retires 2-3 bits per iteration,
>yet is much simpler than Radix-4 SRT because it uses no lookup table.
>It only needs 2-bit comparisons plus a little simple logic. The article
>is in the proceedings of ICCD '96.
>Let me know if you are interested.
do you have the articel on your Web-page? If not may you please send
it to me by e-mail?
Thanks.
Robert M. Muench
SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany
--> Private answer to: r.m.muench+ieee.org <--
==>>> replace the + with @ <<<==
PGP-Fingerprint:
08 E9 EE 9F 33 ED 46 11 A5 CD BE FC 9D ED 75 14
Article: 5971In article <E7y3D2.Czx@bhishma.cse.iitb.ernet.in>, Abhinav Kumar <abhinav@cse.iitb.ernet.in> writes >Hi, > As a part of our course project we are required to develop a download >software to download data in the .mcs file to the XC3020 PCB. This is what >we gather from manuals regarding the .mcs file format obtained using XACT s/w: > > o First line == Info regarding the format of the file > o From the second to the last but one line the data in every line > will look as below:- > > :YYxxxxxxTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTgg > <----------- YY no of bytes --------> > where > + every symbol is one nibble of data > + gg is the validation constraint > + TT is the data byte to be downloaded on to the > xc3020 > o Last line == Info regarding the format of the file > > We have a query here. Does the TT data bytes include the format of >transferring the data like the preamble, start bits, stop bits, etc. If not >then we have realised that the number of data bytes(TT) to be downloaded is >more than what is expected. Then there must be some bits in the TT data >bytes which have to be neglected. > > If the preamble, start & stop bits are indeed in the TT data bytes >then we have observed in the .mcs file that the first 5 TT data bytes in the >second line which will be the (preamble + length count + 4 high bits) is >different from what is specified in the data book for xc3020. > >Can anybody throw some light on this ? > > Thanks in advance for any help > -Abhinav Kumar > (E-mail : abhinav@cse.iitb.ernet.in) > > Do you really need to know about the preamble and postamble bit stream. Usually people tend to write the bitstream/bytestream to the device and check the DONE/PROG pins etc. Xilinx provide some software which generates an .MCS (Intel Hex) file and then you can convert that to whatever format you wish. I remember they hade a program called MAKESRC which generated a source file from the bitstream/.MCS file. This was very usefule in that you could comple the data into your software and index it in an array. I've used this technique very successfully. I hope this answers your questions or am I barking up the wrong tree ? Regards, Gareth Baron %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % % Morphesys Ltd. Tel: +44 (0)802 754 512 % % % % EMail: Gareth@trsys.demon.co.uk % % % % http://www.trsys.demon.co/ % % % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Article: 5972
Wim, you wrote: >>I recently purchased a second hand 486 and found a larg( >>network?)IScard in it.On the biggest chip is inscribed XILINX >>xc2018-50.Can somenone tell me what it is and what it is worth? Wim Hope you won't be disappointed that this part is only worth a few dollars -- well under $10, in fact. The part is a Xilinx FPGA of the now-discontinued XC2000 family. This was the first commercial family of FPGAs and had a long life -- but Xilinx is now three or four generations down the road. The IS card was probably an add-in card as FPGAs are not generally found on standard equipment in PCs -- FPGAs are too expensive for really high-volume production (even today, although they now can be used in higher volume than at the time that board was designed). Or it was an early generation product which was later redesigned for high-volume production. At the time of design, the FPGA was probably comparatively one of the most expensive components, but today an XC2000 device is practically worthless. Sorry! :-) Rhondalee Rohleder (FPGA market analyst) Pace Technologies / Pace_Research@compuserve.com -- R. Rohleder Pace_Research@compuserve.comArticle: 5973
Did enyone knows where I can find 8051/8032 romless core for xilinx FPGA XC40xx family? Davor Kovacec SITEK s.r.l.Article: 5974
There was a company in business last year called Xess that was selling a pcb with an 8051 and an FPGA on board. Did they fold or can anyone tell me how to get in touch with them? Thanks.
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