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Austin Franklin wrote: > > > My question to you is; how would you do this using your library? Would > > you need to add a "special" counter, or do you have some sort of > > "universal" counter which allows you to add some custom logic in the CLB > > which brings out the carry chain? > > Ray's method is pretty much the same as what I do. You do have to realize > that taking the carry out of a 1 bit in the CLB vs a 2 bit in the CLB > requires a different 'function' block be hooked to the 2 bit slice counter > symbol.... Obviously, the starting bit can be different too...you might > use only one of the bits of the start CLB too......and also, what type of a > counter, loadable, up/down, up or down etc....makes the building blocks > different... > > If you use Viewlogic, and tell me how many bits you need, what the starting > bit is, whether you want it to count up/down etc. I can send you one in a > few minutes..... > > Austin Thanks for offering Austin, but I am using Foundation. Just for the record, it is a loadable, enabled, 8 bit up counter with a terminal count output (the carry of course). One thought that has occured to me is the fact that for an 8 bit counter, I could just do the TC in a CLB without using the carry chain. In fact, that might be even faster than using the carry since the carry has a significant overhead getting into and out of the chain. After I read Ray's post, it would appear that it might be possible to use FMAPs to combine the logic with the carry. I have been searching the Xilinx web site all morning looking for info on how to use RPMs to make counters without sucess. Where can I get info on this? Even if the circuit would be faster by putting my carry detect in a separate CLB, I would like to know how to make RPMs in the future. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13501
Has anybody had any trouble getting the dongle'd Metamor VHDL compiler to work under NT & if so how does one get around the problem ?Article: 13502
In article <725rjk$5m$1@ffx2nh2.uu.net>, "Joel Kolstad" <JKolstad@Electroglas.Com> wrote: > Well, it's probably me... but damn it... I'm running Foundation 1.5 here, > and getting the schematic capture portion of the package to talk to the > simulator is nearly impossible. I'll tell it to simulate a macro, it'll > open up the simulator, and then I'll start adding probe points. The > simulator COMPLETELY IGNORES the probe points I'm clicking on, when it > should be adding them to its own list. I'll click over on the simulator and > add some signals, and schematic captures completely ignores what's been > added! Better still, sometimes schematic capture won't even let me add any > probe points at all, just completely ignoring mouse clicks! > > You go ahead and step time in the simulator, and the signals listed do > reasonable things, but schematic just sits there with its probe points > displaying nothing at all. > > !@$!@#%^^#$ > > OK, this doesn't happen 100% of the time. On VERY RARE occasion it actually > works the way it should. I can't believe this happens to all you other > people on a daily basis, or there'd be an angry mob outside of Xilinx HQ > threatening to burn the place down. So what am I doing wrong? The concept > seems really simple -- add a probe in schematic, and the simulator picks it > up, add a signal in simulator, and schematic should pick it up... right? > > ---Joel Kolstad > > Oh God! I am sitting here on a dreary Sunday afternoon, desparately looking for information describing a fix for EXACTLY THIS PROBLEM! However, I believe that I can add a little twist to the puzzle. In my case, however, the simulator works in the functional mode and does NOT WORK in the timing mode. What is more remarkable is the fact that the simulator does not even see the instance(s) that I am trying to probe in the timing mode. What is MOST remarkable is the fact that no schematic implementation, no vhdl macro implementation, no nothing is either visible or simulatable (in the timing mode) for this section of the design! Joel? did you ever get an answer? -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13503
John Harrop wrote: > Hello, > > I am looking for suggestions. I want to upgrade a replacement for a > design which previously used a Cypress CY7C341 CPLD. > > Unfortunately, we also want operating temperature from -55 to 105 > degrees C ...snip If you need 105 degrees AMBIENT, then you need a part that can handle significantly higher junction temperature, since power consumption in CPLDs is not insignificant. Make sure you read the definition of "temperature" carefully in the respective data sheets. Peter Alfke, speaking for himself. >Article: 13504
Sorry if I offended anyone with my post.
Thanks to "rk" for the time taken to post his results, and to Peter for his
comments.
I always identify who I am, and what my allegiance is. Which I think you
should do as well Guy. What's the best 7K timing you can get from the 7K
family?
But back to the question at hand:
The R398 software release includes support for the SX08 device, it is available
now from your local FAE.
I threw together the test circuit below (valid or not, just enough to generate
timing numbers for the SX08). I can make modifications on request and re-gen
the numbers. No hand placement, standard layout. Personally I don't like
simple test cases like this and would rather have our local FAE run the actual
customer design. No more commentary, just the data:
library IEEE;
use ieee.std_logic_1164.all;
entity threestate is
port (Reset_n : in std_logic;
Clock : in std_logic;
oe_nxt : in std_logic;
Ack_in : in std_logic;
Ack_out : out std_logic
);
end threestate;
architecture RTL of threestate is
signal oe_reg : std_logic;
signal Ack_reg : std_logic;
begin
UREG: process(Clock, Reset_n)
begin
if (Reset_n='0') then
Ack_reg <= '1';
oe_reg <= '0';
elsif (Clock'event and Clock='1') then
Ack_reg <= Ack_in;
oe_reg <= oe_nxt;
end if;
end process UREG;
Ack_out <= Ack_reg when (oe_reg='1') else 'Z';
end RTL;
Using HCLKBUF, WCCOM (3.0V 70 degrees C)
STD -1 -2
Z->0 or 1 6.5ns 5.5ns 4.8ns
0->1,1->0 6.0ns 5.1ns 4.4ns
0 or 1 ->Z 5.2ns 4.4ns 3.8ns
Using CLKBUF, WCCOM (3.0V 70 degrees C)
STD -1 -2
Z->0 or 1 7.5ns 6.4ns 5.6ns
0->1, 1->0 7.1ns 6.1ns 5.3ns
0 or 1 ->Z 6.3ns 5.4ns 4.7ns
Daniel K Elftmann
Actel Corporation
New England Field Applications Engineer
phone: 978-244-3827
email: dan.elftmann@actel.com
gs wrote:
> Dan,
> Professionally advertising to the group isn't proper net edicate. Being
> that you have been around these pages for so long, you should know better
> than to lower yourself to that level :-).
>
> GS
>
> Daniel K. Elftmann wrote in message <366358AF.81ECA389@actel.com>...
> >Take a look at the Actel A54SX08 and contact your local Actel FAE, sounds
> >like a good FAE Challenge.
> >
> >http://www.actel.com/products/devices/SX/chall.html
> >
> >Steve wrote:
> >
> >> I'm interfacing to a Motorola MPC 860 @50Mhz. I need to provide an
> >> acknowledge signal in <10ns after the Clock. To do this my PLD/FPGA
> >> needs to have a (Clk-Q + comb delay + tristate enable) < 10ns.
> >>
> >> So far I haven't found a CPLD to do it. What small FPGA's have the best
> >> crack at it??? ... or prove me wrong on the CPLD issue?
> >>
> >> So far my only practical solution is an XCS05XL-4.
> >>
> >> Comments?
> >>
> >> Steve
> >
Article: 13505Peter Alfke wrote: > John Harrop wrote: > > > Hello, > > > > I am looking for suggestions. I want to upgrade a replacement for a > > design which previously used a Cypress CY7C341 CPLD. > > > > Unfortunately, we also want operating temperature from -55 to 105 > > degrees C ...snip > > If you need 105 degrees AMBIENT, then you need a part that can handle > significantly higher junction temperature, since power consumption in > CPLDs is not insignificant. Make sure you read the definition of > "temperature" carefully in the respective data sheets. > > Peter Alfke, speaking for himself. > > > Very good advice indeed Peter, advice I think all designers of programmable logic need to be aware of. The customers design can strongly influence the power dissipation and self-heating effects and the designer needs to go through a power calculation as well as calculations with Tja and Tjc to determine the worst case device junction temperature. I believe this applies to all programmable logic and not just CPLDs. Next the designer needs the proper vender tools to determine the device performance characteristics for the calculated worst case junction temperature. Comments welcome. Daniel Elftmann Actel Corporation New England Field Applications EngineerArticle: 13506
Daniel K. Elftmann wrote: > Peter Alfke wrote: > > > John Harrop wrote: > > > > > Hello, > > > > > > I am looking for suggestions. I want to upgrade a replacement for a > > > design which previously used a Cypress CY7C341 CPLD. > > > > > > Unfortunately, we also want operating temperature from -55 to 105 > > > degrees C ...snip > > > > If you need 105 degrees AMBIENT, then you need a part that can handle > > significantly higher junction temperature, since power consumption in > > CPLDs is not insignificant. Make sure you read the definition of > > "temperature" carefully in the respective data sheets. > > > > Peter Alfke, speaking for himself. > > > > > > > Very good advice indeed Peter, advice I think all designers of > programmable logic need to be aware of. The customers design can strongly > influence the power dissipation and self-heating effects and the designer > needs to go through a power calculation as well as calculations with Tja > and Tjc to determine the worst case device junction temperature. I > believe this applies to all programmable logic and not just CPLDs. Next > the designer needs the proper vender tools to determine the device > performance characteristics for the calculated worst case junction > temperature. Comments welcome. > > Daniel Elftmann > Actel Corporation > New England Field Applications Engineer just to add a few comments ... .... if the requirements do not dictate high frequency, then most of the fpga's will have low power dissipation and there will not be a big temp rise to the junction, making the situation a no brainer - you'd have to screen your parts but i've tested a ton of commercial grade parts at 125C and have had good results - or you can procure your parts to military temperature range without the mil reliability screening and have the manufacturer do the temp screening for you. of course, one wants to operate the parts at a lower temperature, since most failure mechanisms result in about a 2x decrease in reliability for a 10C temp rise. for higher power operation package selection is also critical - certain packages will mount the die onto a metal "slug" that is brought right through the plastic or ceramic package for heat sinking on the bottom - other packages (ceramic) can be procured that are cavity down permitting easier cooling by convection, for example, or simply a ceramic package with a thermal resistance THETAj-c of say 10C/watt or so is available which is frequently used in vacuum or low air pressure situations. at least one manufacturer produces flat packs that can be lead bent "up" or "down", as conductively cooled systems typically heat sink on the bottom, convection cooled systems take the heat off of the top. also note that many fpga manufacturers are now producing mil-temp or mil-qual'd parts in plastic packages - recent stuff about this in the press has come from actel, quicklogic, and xilinx [in alphabetical order, trying to maintain the nice civility in the group :-)] - i don't know about the others [altera, atmel, dynachip, lucent, vantis again in alphabetical order], perhaps some one else can fill us in. rk rkArticle: 13507
We are looking to buy some of these Motorola FPGA's (160PQFP) . If you have surplus stock please contact Michal @ 212-2749191Article: 13508
> I agree with you. I wish many more manufacturers had usenet presence. Yes, but... I don't want to see a "Try our XX13-93" from each FPGA vendor every time somebody asks a question. Things like that should be emailed directly to the person who asked the question rather than posted to the whole group. I do want to see answers and comments that explain and compare. Why is that the right/best chip to use? Are there any tricks in that area that you wouldn't get from reading the data sheet? -- These are my opinions, not necessarily my employers.Article: 13509
Thanks for all the info and suggestions. I've decided to minimise risk and implement a near-clone of the Xilinx download pod, and to be generous with decoupling. Since the specific design will be made in only very small quantities, I am keen to avoid having to iterate round the PCB layout. -- Tim Forcer tmf@ecs.soton.ac.uk The University of Southampton, UK The University is not responsible for my opinionsArticle: 13510
It's really not that hard to do. Look at one of the xilinx counter macros as a starting point. To invoke the carry chain, you put the carry chain component (Cy4) on the schematic. That component needs to be RLOC'd. Attach to it the appropriate carry chain control macro (CY4***). Then add the CLB logic to the carry chain. to include the CLB logic, it needs to be RLOC'd too. To RLOC the logic, put an FMAP component on the schematic with appropriate signals attached and RLOC the FMAP. Make sure you observe the rules about getting on and off the carry chain and be careful about overlapping RLOCs. There is some information in the Xilinx libraries guide about working with the carry chain, RLOCs and FMAPs. Rickman wrote: > Austin Franklin wrote: > > > > > My question to you is; how would you do this using your library? Would > > > you need to add a "special" counter, or do you have some sort of > > > "universal" counter which allows you to add some custom logic in the CLB > > > which brings out the carry chain? > > > > Ray's method is pretty much the same as what I do. You do have to realize > > that taking the carry out of a 1 bit in the CLB vs a 2 bit in the CLB > > requires a different 'function' block be hooked to the 2 bit slice counter > > symbol.... Obviously, the starting bit can be different too...you might > > use only one of the bits of the start CLB too......and also, what type of a > > counter, loadable, up/down, up or down etc....makes the building blocks > > different... > > > > If you use Viewlogic, and tell me how many bits you need, what the starting > > bit is, whether you want it to count up/down etc. I can send you one in a > > few minutes..... > > > > Austin > > Thanks for offering Austin, but I am using Foundation. > > Just for the record, it is a loadable, enabled, 8 bit up counter with a > terminal count output (the carry of course). One thought that has > occured to me is the fact that for an 8 bit counter, I could just do the > TC in a CLB without using the carry chain. In fact, that might be even > faster than using the carry since the carry has a significant overhead > getting into and out of the chain. > > After I read Ray's post, it would appear that it might be possible to > use FMAPs to combine the logic with the carry. I have been searching the > Xilinx web site all morning looking for info on how to use RPMs to make > counters without sucess. Where can I get info on this? Even if the > circuit would be faster by putting my carry detect in a separate CLB, I > would like to know how to make RPMs in the future. > > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13511
> Just remember nothing is bug free, I completely disagree with this. Do you work for Microsoft ;-) That certainly is what they would like us to believe... They couldn't even get a simple set of utilities, like DOS bug free....even after 6 tries! Why would we ever expect them to get Windows correct? There was a time when products didn't ship with known bugs....it was a mater of reputation, quality and standards. I also understand projects are much vaster today, but we also have a lot more extensive tools today. Today, unfortunately, at least for software, bugs are severely rampant, and have sadly been widely accepted as 'the norm'. Personally, I believe it's just bad design, poor programming, and bad decisions made to rush things to get to market for, yet, another buggy release.... 'Well Alteblab released version 32,486.301 last week of their Flexoroute(tm) tools, so we have to release out latest tools too'. There is this funny 'keeping up with release numbers' in the software industry...like version 82.3 of something is somehow better than version 2 of something else.....all marketing perception.... This was always a good question...'Is software engineering?'. Well, it can be, but for the most part, I would say a resounding no. Sorry to get off on this little 'software' tangent.... Austin P.S. CPLD, eh? Watch that Tequila, it makes you see things....er, like bugs ;-)Article: 13512
> But then Xilinx stock hit $60 today, so I will not lose too much sleep. > :-) Hit. Hum. Interesting choice of words ;-)Article: 13513
> > Thanks for offering Austin, but I am using Foundation. > You're welcome. I think that is a funny name for the tools. It just doesn't fit ;-) Seriously, what do you think of the 'Foundation' tool set? Have you used Viewlogic before? AustinArticle: 13514
FYI,
We just recently released a credit-card sized single
board computer with an FPGA based "virtual interface".
It has the following features:
16,000 Gate FPGA (Altera EPF6016)
PowerPC CPU
16 MB DRAM
2 MB Flash
Ethernet
USB and Serial Ports
LCD/TV Video
On-Board Power Supply
Credit Card Sized
Integrated POSIX RTOS, TCP/IP and Web Server
-- Stuart
--------------------------------------------------
Stuart Adams
Bright Star Engineering Inc.
19 Enfield Drive
Andover MA 01810 USA
Tel: +1-978-470-8738
Fax: +1-978-470-8878
Email: sja@brightstareng.com
Web: http://www.brightstareng.com/
Article: 13515
hi guys,
not an fpga topic but ...
... the readers here probably can help.
i remember seeing an advertising splash a bit ago about 4 megabit static
ram with 6T cells and can't find it [i ripped out the ad and it's
probably in a pile of important stuff to be filed].
anyways, what i'm looking for is:
static sram
4 megabit density
low power
speed not terribly important
6T memory element
3.3V operation preferred
thanks in advance,
rk
Article: 13516
--------------E13A71606B830FB2F5778518
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
hi guys,
we're looking to get a new computer and would like some opinions. of
course, what we bought 2 years ago is already a bit overloaded so let's
make believe this one will last for 2 years. our designs are a mixture
of schematics, macros and vhdl, with more use of vhdl and larger parts.
now, we decided to use windoze NT and don't want to start a
unix<->linux<->windoze war. linux is out since we don't have software
that runs on it. we don't want unix since all of the software we want
to run is available on NT and we use pc's for a lot of programs that
aren't on UNIX, along with our add-in cards (store-bought and home
built) being ISA, a large investment.
cae s/w we can expect to run is:
viewlogic
actel tools
atmel tools
xilinx tools
synopsys w/ libraries for fpgas, asics
synplicity
possibly exemplar
anyways,
here's the topics for discussion:
1. how much dram should be on the machine?
2. how much dram should the machine be capable of? a lot of pc's are
limited to 384 megabytes.
3. does any of the s/w make use of a second processor?
4. will it be expected that in the next few years s/w
will make use of a second processor?
thanks,
rk
--------------E13A71606B830FB2F5778518
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<HTML>
<TT>hi guys,</TT><TT></TT>
<P><TT>we're looking to get a new computer and would like some opinions.
of course, what we bought 2 years ago is already a bit overloaded so let's
make believe this one will last for 2 years. our designs are a mixture
of schematics, macros and vhdl, with more use of vhdl and larger parts.</TT><TT></TT>
<P><TT>now, we decided to use windoze NT and don't want to start a unix<->linux<->windoze
war. linux is out since we don't have software that runs on it.
we don't want unix since all of the software we want to run is available
on NT and we use pc's for a lot of programs that aren't on UNIX, along
with our add-in cards (store-bought and home built) being ISA, a large
investment.</TT><TT></TT>
<P><TT>cae s/w we can expect to run is:</TT><TT></TT>
<P><TT> viewlogic</TT>
<BR><TT> actel tools</TT>
<BR><TT> atmel tools</TT>
<BR><TT> xilinx tools</TT>
<BR><TT> synopsys w/ libraries for fpgas, asics</TT>
<BR><TT> synplicity</TT>
<BR><TT> possibly exemplar</TT><TT></TT>
<P><TT>anyways,</TT><TT></TT>
<P><TT>here's the topics for discussion:</TT><TT></TT>
<P><TT> 1. how much dram should be on the machine?</TT><TT></TT>
<P><TT> 2. how much dram should the machine be capable
of? a lot of pc's are</TT>
<BR><TT> limited to 384 megabytes.</TT><TT></TT>
<P><TT> 3. does any of the s/w make use of a second processor?</TT><TT></TT>
<P><TT> 4. will it be expected that in the next few years
s/w</TT>
<BR><TT> will make use of a second
processor?</TT><TT></TT>
<P><TT>thanks,</TT><TT></TT>
<P><TT>rk</TT></HTML>
--------------E13A71606B830FB2F5778518--
Article: 13517And your point is...? Stuart Adams wrote: > FYI, > > We just recently released a credit-card sized single > board computer with an FPGA based "virtual interface". > It has the following features: > > 16,000 Gate FPGA (Altera EPF6016) > PowerPC CPU > 16 MB DRAM > 2 MB Flash > Ethernet > USB and Serial Ports > LCD/TV Video > On-Board Power Supply > Credit Card Sized > Integrated POSIX RTOS, TCP/IP and Web Server > > -- Stuart > > -------------------------------------------------- > > Stuart Adams > Bright Star Engineering Inc. > 19 Enfield Drive > Andover MA 01810 USA > Tel: +1-978-470-8738 > Fax: +1-978-470-8878 > Email: sja@brightstareng.com > Web: http://www.brightstareng.com/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13518
--------------FEA87EB1CAAE8CA893349949 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit For xilinx/viewlogic, I find that 256MB works fine. I've got a dual Pentium Pro. None of the software uses the second processor as far as I can tell. However, the second processor is nice to keep from taking a productivity hit while running synthesis or a place and route...you can continue working on something else while running a compute intensive application like PAR. The only thing that seems to crash my system (running under NT) is microsoft applications (office mostly). Viewlogic and xilinx software has never bluescreened the machine. Hmm, what does that tell me? rich katz wrote: > hi guys, > > we're looking to get a new computer and would like some opinions. of > course, what we bought 2 years ago is already a bit overloaded so > let's make believe this one will last for 2 years. our designs are a > mixture of schematics, macros and vhdl, with more use of vhdl and > larger parts. > > now, we decided to use windoze NT and don't want to start a > unix<->linux<->windoze war. linux is out since we don't have software > that runs on it. we don't want unix since all of the software we want > to run is available on NT and we use pc's for a lot of programs that > aren't on UNIX, along with our add-in cards (store-bought and home > built) being ISA, a large investment. > > cae s/w we can expect to run is: > > viewlogic > actel tools > atmel tools > xilinx tools > synopsys w/ libraries for fpgas, asics > synplicity > possibly exemplar > > anyways, > > here's the topics for discussion: > > 1. how much dram should be on the machine? > > 2. how much dram should the machine be capable of? a lot of pc's > are > limited to 384 megabytes. > > 3. does any of the s/w make use of a second processor? > > 4. will it be expected that in the next few years s/w > will make use of a second processor? > > thanks, > > rk -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka --------------FEA87EB1CAAE8CA893349949 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> For xilinx/viewlogic, I find that 256MB works fine. I've got a dual Pentium Pro. None of the software uses the second processor as far as I can tell. However, the second processor is nice to keep from taking a productivity hit while running synthesis or a place and route...you can continue working on something else while running a compute intensive application like PAR. The only thing that seems to crash my system (running under NT) is microsoft applications (office mostly). Viewlogic and xilinx software has never bluescreened the machine. Hmm, what does that tell me? <P>rich katz wrote: <BLOCKQUOTE TYPE=CITE> <TT>hi guys,</TT> <P><TT>we're looking to get a new computer and would like some opinions. of course, what we bought 2 years ago is already a bit overloaded so let's make believe this one will last for 2 years. our designs are a mixture of schematics, macros and vhdl, with more use of vhdl and larger parts.</TT> <P><TT>now, we decided to use windoze NT and don't want to start a unix<->linux<->windoze war. linux is out since we don't have software that runs on it. we don't want unix since all of the software we want to run is available on NT and we use pc's for a lot of programs that aren't on UNIX, along with our add-in cards (store-bought and home built) being ISA, a large investment.</TT> <P><TT>cae s/w we can expect to run is:</TT> <P><TT> viewlogic</TT> <BR><TT> actel tools</TT> <BR><TT> atmel tools</TT> <BR><TT> xilinx tools</TT> <BR><TT> synopsys w/ libraries for fpgas, asics</TT> <BR><TT> synplicity</TT> <BR><TT> possibly exemplar</TT> <P><TT>anyways,</TT> <P><TT>here's the topics for discussion:</TT> <P><TT> 1. how much dram should be on the machine?</TT> <P><TT> 2. how much dram should the machine be capable of? a lot of pc's are</TT> <BR><TT> limited to 384 megabytes.</TT> <P><TT> 3. does any of the s/w make use of a second processor?</TT> <P><TT> 4. will it be expected that in the next few years s/w</TT> <BR><TT> will make use of a second processor?</TT> <P><TT>thanks,</TT> <P><TT>rk</TT></BLOCKQUOTE> <P>-- <BR>-Ray Andraka, P.E. <BR>President, the Andraka Consulting Group, Inc. <BR>401/884-7930 Fax 401/884-7950 <BR>email randraka@ids.net <BR><A HREF="http://users.ids.net/~randraka">http://users.ids.net/~randraka</A> <BR> </HTML> --------------FEA87EB1CAAE8CA893349949--Article: 13519
Magnus Homann wrote: > <snipped> > > Isn't the new Altera Apex supposed to have LVDS options? Due out this spring? > Thanks for the tip! The Apex is described at http://www.altera.com/html/products/apex.html Don't know if I'll be able to use it, but it's nice to know that at least one FPGA heavyweight is promising this. Tom Burgess -- Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.ca Office: (250) 490-4360 Switch Board: (250) 493-2277 Fax: (250) 493-7767Article: 13520
On Fri, 4 Dec 1998 12:15:46 +0000, David Pashley <David@edasource.com> wrote: >If your requirements encompass productivity issues, then remember that >FPGA Express 3 is available fully integrated within the Viewlogic 7.5 >toolset. So you can freely combine HDL, schematics and state diagrams, >have a single flow (including integrated place and route) for all FPGAs, >and use a single environment for VHDL/Verilog, post-implementation and >board-level verification. Hi Dave! I'm kind of spoilt as I have a nice setup of Renoir, Turbo Writer, ModelSim, and Leonardo Spectrum L3. I don't like gate level schematics any more (no, really) because I can do everything I want to do in VHDL either graphically or textually. (And I have to deal with far too many architectures anyhow). I am biased as I have the pleasure of selling all four products. :-) You are right, that the real benefit is in the whole flow, not just a point solution. Cheers Stuart For Email remove "NOSPAM" from the addressArticle: 13521
Ray has a good point about the second processor, but I still decided to go with the single, fast processor (450MHz, 512MB) when I upgraded two months ago. I'm not always using my PC when I'm simulating/synthesizing/routing, so I wanted the fastest possible performance for single applications. If my user interface hesitates when I'm running a "big" app, I can live with that. What I am not happy with in my new PC is disk I/O performance. I wanted an ultra-wide/ultra-fast SCSI. What I ended up with was the same old enhanced IDE, not even ultra-IDE! I couldn't convince my boss that disk I/O performance was important. I would be interested in hearing what people recommend for disk I/O. Ray Andraka wrote: > For xilinx/viewlogic, I find that 256MB works fine. I've got a dual > Pentium Pro. None of the software uses the second processor as far as > I can tell. However, the second processor is nice to keep from taking > a productivity hit while running synthesis or a place and route...you > can continue working on something else while running a compute > intensive application like PAR. The only thing that seems to crash my > system (running under NT) is microsoft applications (office mostly). > Viewlogic and xilinx software has never bluescreened the machine. > Hmm, what does that tell me? > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka >Article: 13522
Stuart Clubb wrote: > I am biased as I have the pleasure of selling > all four products. :-) > Cheers > Stuart > For Email remove "NOSPAM" from the address As was mentioned in another recent thread: It is o.k. and even desirable for hardware and software suppliers to have a voice in this newsgroup, but they should ALWAYS identify themselves properly. We may be smart and even helpful, but we are obviously biased, and the readers should be alerted to that bias. Peter Alfke, as always: Xilinx Applications EngineeringArticle: 13523
Richard Cant <richard@timezznospamzzhigh.demon.co.uk> wrote:
[snip]
>Actually Plessey advertised a DSP device incorporating dedicated silicon
>in the form of multipliers together with some FPGA logic about 10 years
>ago - but I lost track of what happened to that development.
Probably showed signs of being succesful, so they axed it.
Richard
------------Richard Dungan-------------
Radix Electronic Designs, Orpington, UK
Spamtrapped: Remove the XY
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Article: 13524Hi! Wath's the best way to begin to work with PLD? I think to a 32 or 64 macrocells, ISP naturally. Some producers give free software, but I'm confused. Altera? Vantis? Lattice? Others? Please, advice me! Thanks... Luigi
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