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Kayvon, Thanks for the reply on the UART, but my mailtool ate your letter before I could reply. I would like the pointer you had. Thanks. Todd a0460010@shsun3.dseg.ti.comArticle: 1901
In article <43js68$o01@merlion.singnet.com.sg>, <jothi@singnet.com.sg> wrote: > >> >> Does anyone make an EEPROM version of the Xilinx XC17256D configuration PROM? >> >> TIA - Alan >> >Yes ATMEL makes these parts. > >they are 17C128 and 17C256 > We tried the 128 but it is still pre-production and has several bugs in it which prevent using it with the XC52xx and possibly all Xilinx chips. We also have used the AT&T reprogramable which did work but does not reliably load. I think it is power ramp up sensitive, on one chases it almost always loaded and in another it never would load. The Xilinx EPROM part always loaded. I don't think they have a 256 out yet either. David GessweinArticle: 1902
Hello, I have a question about XC4000 FPGA synthesis using synopsys. I want to instanciate manually some Xbloc component, how can i do it ? I currently instantiate some designware component so i have added to my VHDL code library IEEE, DWARE, DW03, GTECH; use IEEE.std_logic_1164.all; use DW03.DW03_components.all; use DWARE.DWpackages.all; use GTECH.GTECH_components.all; An i can instantiate some component manually cpt_i_I : DW03_lfsr_scnto GENERIC MAP( width => 3, count_to => 3) PORT MAP( data => n_data_i0, load => n_notld_i, cen => n_ce_i, clk => clk_4, reset => reset, count => n_count_i, tercnt => n_tc_i); How can i do that for Xbloc component ? I couldn't find any data in the designware data books such as name of the component and ports. Thank in advance for any help, (i am sorry if my name doesn't appears in the name column, it never does.) Jean Marc Daveau, Ph.D student, TIMA lab, Grenoble, FRANCE Email:daveau@verdon.imag.frArticle: 1903
>>In article <DEvyE5.64L@hpqmoea.sqf.hp.com>, mjm@hpqtdzk.sqf.hp.com (Murdo >>McKissock) writes: >>> Ola Torudbakken (otoe@si.sintef.no) wrote: >>> >>> : I need some recommendation of FPGA's which may achieve a system speed >>> : of 40MHz. I'm not interested in hearing about FPGA products which can Altera's FLEX family has comparable density anmuch faster speed than Xilinx 4000 devices. I looked through the PREP web page and found that the EPF81500A-2 has almost twice the speed ( in average ) than a 4013. I personally developed a PCI master card using EPF81188A-2 and got a 38MHz performance on first try. Maybe thats something that you might find helpfulArticle: 1904
I run into a problem when designing an Altera flex8452-3 with VHDL. After coding VHDL, I read it in Synopsys and sythesized it. I was pointing to flex8000.db and flex8000.sldb. I then do "report_timing" in synopsys. The problem is that some of the cells (namely, TBL_4, TBL_3, TBL_9) have extradinarily large delays - 11.22ns in my case. These cells are simply the equivalents of AO2, AO3, AN2, AN3 in ASIC libraries. I would image them to be runing at 1-2ns even with some extrinsic loadings. I called up Synopsys to ask them check flex8000.lib, which is what flex800.db compiled from. They told me that even an AND gate in flex8000.db has a 6ns intrinsic delay (without any loading). Altera told me to use maxplus2 to place & route it then report timing from maxplus2's static timing analyzer. With TBL_4, TBL_3, TBL_9 having 11.22ns, my design failed in Synopsys, but magically, it works after maxplus2 place&routed it. Altera said it will come back with an answer as why the timings in flex8k.db are so large after several days . The only thing that I will image is that when designing Altera, we cannot use Synopsys as an optimzer (or cannot rely on it), but simply use it as a translator to translate VHDL to netlists. I was wondering if anyone else run into the same problem. Your comments will be much appreciated. Regards, Louis cArticle: 1905
> > Does anyone make an EEPROM version of the Xilinx XC17256D configuration PROM? > > TIA - Alan > Yes ATMEL makes these parts. they are 17C128 and 17C256 Baskaran KArticle: 1906
Just wondering is there any FAQ in this newsgroup? Thanks! ChengArticle: 1907
There is a program called "xbloxgen" from Xilinx which is used to instantiate xblox modules in the vhdl/verilog code. You input which xblox module you want to instantiate in your code, and it generates the xnf file and the vhdl/verilog code (component definition, and instantiation lines) for that xblox module. You can use this tool to instantiate the xblox modules: clk_div, shift, inc_dec, accum, add_sub, compare, counter, decode, data_reg. If you don't have that tool, then you have to write the code and the xnf file for the xblox module yourself. Writing the code is easy, as all you have to do is, using the same input/output port names of the xblox module in the component decleration, and then instantiating the component. But, the second step ie. writing the xnf file for the xblox module is tricky, you need to be familiar with xnf file format, and xnf files generated for xblox modules. It is possible to write the xnf file for the xblox module yourself, however it is not part of a design flow that Xilinx suggests, and I am sure it won't be a recommended step by Xilinx. Good Luck, Yuce Beser "speaking for myself"Article: 1908
I'm thinking about buying the protel schematic capture package for windos at their "blow it out the door" price of $295. What I want to do is create a symbol library for AT&T ORCA parts so I can do some FPGA schematics and feed the resulting EDIF netlist to the ORCA Foundry place & route tool. Before I embark upon this venture, I've got to ask the obligatory question: HAS ANYONE DONE THIS BEFORE? I know it generates XNF files very nicely, but EDIF is my target netlist format. Anyone know if Protel supports EDIF attributes (properties) attached to nets and symbols? Thanks and all that stuff, John McCluskey J.McCluskey@ieee.org P.S. Soon as I get it ready, I'll post a VHDL design for an ORCA based DDS (Direct Digital Synthesis) circuit. 32 bit phase accumulator, 100 MHz system clock, supports DAC's of 1 to 16 bits. Theoretical spurs are -65 dBc. Anybody interested?Article: 1909
twtmail@twt.co.il wrote: >I'm using an EPM5016 in a small project. >I'm using 4 i/o pins for 2 NOT gates osc. >The component is getting very very hot (after about 5 min.) >Does anybody knows why? Sounds like latchup (due to floating input pins) to me. _____________________________________________________________ Ian Baines Eurotherm PID R&D work ianb@epid.eurotherm.co.uk Southdownview Way home ianb@mistral.co.uk Worthing, Tel +44(0)1903-205277 Fax +44(0)1903-524016 BN14 8NN, UKArticle: 1910
methot@ccrs.emr.ca (Simon Méthot) writes: > I am presently starting a project using emitter coupled logic (ECL). > Does anyone know of a manufacturer of ECL fpga. The data rate that must > be achieved is 150 mbits/sec, and the input voltage is ECL. One of the > task is to be built a P-N sequence decoder. Thanks. > I've never seen one. Cypress, National, and possibly Phillips have ECL PAL's with density on the order of a 20V8. Let us know if you find anything better.Article: 1911
In article <DF4vz7.4qz@alchemy.chem.utoronto.ca>,
Yuefang Xiang <xiang@hera.med.utoronto.ca> wrote:
>I run into a problem when designing an Altera flex8452-3 with VHDL. After
>coding VHDL, I read it in Synopsys and sythesized it. I was pointing to
>flex8000.db and flex8000.sldb. I then do "report_timing" in synopsys.
>The problem is that some of the cells (namely, TBL_4, TBL_3, TBL_9) have
>extradinarily large delays - 11.22ns in my case. These cells are simply
>the equivalents of AO2, AO3, AN2, AN3 in ASIC libraries. I would image
>them to be runing at 1-2ns even with some extrinsic loadings.
>
>I called up Synopsys to ask them check flex8000.lib, which is what flex800.db
>compiled from. They told me that even an AND gate in flex8000.db has a 6ns
>intrinsic delay (without any loading). Altera told me to use
>maxplus2 to place & route it then report timing from maxplus2's static
>timing analyzer. With TBL_4, TBL_3, TBL_9 having 11.22ns, my design failed
>in Synopsys, but magically, it works after maxplus2 place&routed it.
>Altera said it will come back with an answer as why the timings in
>flex8k.db are so large after several days .
>
>The only thing that I will image is that when designing Altera, we cannot
>use Synopsys as an optimzer (or cannot rely on it), but simply use it as
>a translator to translate VHDL to netlists.
>From two Flex8K design I did two months ago using VHDL and Synopsys,
I'd say you are right. Synopsys timing reports are useless for Altera8K.
The reason is that Synopsys synthesizes downto gates. It simply assigns
gates with 6ns delay, and sum them up along the path. Altera may group
gates together in the implementation and fit them into one LE,
thus significantly reduce the path delay reported by Synopsys.
I had slack time in the range of -30 ns, but the design worked after
fitting.
Synopsys can still be used as an optimizer to do some common sense
optimization.
I read that for Xilinx parts, Synopsys maps logic to CLBs, and the
timing reports are more accurate.
Cheers,
--------------------- My opinion only ------------------------------------------
Qian Zhang Bell-Northern Research, Ltd Ph.: (613) 765-2485
H/W System Modelling P.O. Box 3511, Station C Fax: (613) 763-4222
Ottawa, Ontario, Canada, K1Y 4H7 Email : qzhang@bnr.ca
--------------------------------------------------------------------------------
>
>I was wondering if anyone else run into the same problem. Your comments will
>be much appreciated.
>
>Regards,
>
>Louis
>c
Article: 1912leow@uclink.berkeley.edu (Ka-Chung Wong) wrote: > >>>In article <DEvyE5.64L@hpqmoea.sqf.hp.com>, mjm@hpqtdzk.sqf.hp.com (Murdo >>>McKissock) writes: >>>> Ola Torudbakken (otoe@si.sintef.no) wrote: >>>> >>>> : I need some recommendation of FPGA's which may achieve a system speed >>>> : of 40MHz. I'm not interested in hearing about FPGA products which can > > >Altera's FLEX family has comparable density anmuch faster speed than Xilinx >4000 devices. I looked through the PREP web page and found that the >EPF81500A-2 has almost twice the speed ( in average ) than a 4013. > >I personally developed a PCI master card using EPF81188A-2 and got a 38MHz >performance on first try. Maybe thats something that you might find >helpful Just a quick note: The PREP data base does not include any certified Xilinx data on FPGAs. Be careful on the data quoted by other companies. They are probably using XC4000-5 timing info. There have been two significant speed grades since that data was reported (a -4 speed grade and a -3). If you want the latest information, see the "XC4000E Data Sheet" available on the Web at http://www.xilinx.com/products/fpgaspec.htm#XC4000 . Also, if you are interested in maximum performance, you should also look at the XC3100A FPGA family. Again, the most up-to-date information is available at http://www.xilinx.com/products/fpgaspec.htm#XC3000 . -- Steve Knapp Corporate Applications Manager Xilinx, Inc.Article: 1913
Recent research has shown that multi-FPGA systems implemented using MCMs provide better logic density and speed performance compared to board level implementations. Altera has a commercially available product, EPF8050, that uses four EPF1188s and one Aptix FPIC housed in an MCM. On the other hand, most Logic emulators and custom computing machines built to date use multiple FPGAs with or without FPICs, implemented using printed circuit boards. My question is: are Field Programmable MCMs commercially viable yet? What are their limitations? Heat dissipation problem? Is the cost prohibitively high? Any insights on this issue will be greatly appreciated. I am especially keen on hearing from people involved in designing next generation Logic emulators and custom computing machines. If there's a good response I will summarize the comments I receive and post them. Thanks. KhalidArticle: 1914
methot@ccrs.emr.ca (Simon M=E9thot) wrote: >I am presently starting a project using emitter coupled logic (ECL). >Does anyone know of a manufacturer of ECL fpga. The data rate that must >be achieved is 150 mbits/sec, and the input voltage is ECL. One of the >task is to be built a P-N sequence decoder. Thanks. > Philips have a small (8 regs) ECL PAL device 10H20EV8/10020EV8. (~200MHz fmax) For anything larger, use external ECL/TTL translators & serial/parallel conversion to take down the speed to something agreeable with whatever fpga you want. /RolfArticle: 1915
In article <43mo2n$adj@mailman.xilinx>, Steven K. Knapp <stevek> wrote: >Just a quick note: The PREP data base does not include any certified Xilinx >data on FPGAs. Be careful on the data quoted by other companies. They are >probably using XC4000-5 timing info. There have been two significant speed >grades since that data was reported (a -4 speed grade and a -3). > Any plans for prep results so we have a chance of comparing parts? Thanks, David GessweinArticle: 1916
In Article <43d28f$ij8@paperboy.ids.net>, randraka@ids.net wrote:
lines deleted
>The trick is to pay attention to the device architecture when you do the
>design. Keep the combinatorial logic to one level whenever at all possible
>(yes this is possible more than is obvious...pipeline your decodes and state
>machines). Use OHE statemachines, and LFSR counters for timers. Without doing
^^^^^^^^^^^^^^^^^^^^^^^^
Could someone refer me to some references or sites where I can get info
on what LFSR counters are? I'm building a system using the Xilinx 4000
series that requires fast FSM's and this would help a lot. Also, would
there be any sites that contain VHDL code for these counters? Thanks
in advance.
Michael
Article: 1917In article <43n21b$cuf@moe.tas.drs.com>, djg@tas.com (David Gesswein) wrote: > In article <43mo2n$adj@mailman.xilinx>, Steven K. Knapp <stevek> wrote: > >Just a quick note: The PREP data base does not include any certified Xilinx > >data on FPGAs. Be careful on the data quoted by other companies.... > > > Any plans for prep results so we have a chance of comparing parts? > > Thanks, > David Gesswein Beware of PREP results, they hav a tenuous relationship with reality. PREP started as a laudable effort by several manufacturers of programmable logic ( originally Actel, Altera, AMD, and Xilinx, soon joined by many others ) to define standardized benchmarks for programmable logic. The benchmarks are implemented by the manufacturer ( who understands the parts best ) and checked by a competitor, to assure accuracy. Performance is measured in clock rate, density in the number of times the standard circuit can be implemented in a given chip. Since small EPLDs had to be included, nine circuits were defined as small ( very small by today's standards ) subsystems. Each circuit has combinatorial logic driving output flip-flops, and the number of inputs is generally identical with the number of outputs ( #1 is an exception ). These circuits are then concatenated, each "instance" driving the inputs of the next instance. ( I have used Lego blocks to describe the structure ) As a result, the big FPGAs contain 100 and more identical circuits, each of them communicating with nothing else but its neighboring circuit. The achievable density is a measure of how well the circuits are partitioned and placed next to each other, (they usually pack very well ) and the reported speed is dominated by the logic speed, since the interconnects are usually very short. Obviously, PREP ignores architecture-specific features ( Longlines, decoders, clock distribution networks, global resets, RAMs, output flip-flops, slew-rate control, xtal oscillators, output drive, power consumption ) and does not report prices. This is not a criticism, but the reader must keep the limtatio in mind. There is only a weak correlation with real density and speed in real systems. The committe put enormous emphasis on push-button automatic implementation, without any user intervention. How meaningful or meaningless that is in the actual implementation of a 10,000 to 20,000-gate circuit is debatable ( and was debated at length ). To add insult to injury, one of the committee members found out that an oversight in the original definition of two of the nine circuits made it possible to extract common logic, implement it only once, and thus concatenate only the remaining logic, obviously more often. It was touted as a triumph of logic synthesis ( apparently over the stupidity of the "Founding Fathers", I was one of them ), and the PREP committe was unable to stop this distortion of the original intent. Conclusion: PREP gives somewhat meaningful numbers for the absolutely best packing density of a few simple circuits with very limited interconnectivity ( provided the distortion mentioned above is taken into account). PREP speed is even more affected by the small size of the circuits and the short interconnects. The cumbersome verification process has resulted in obsolete data being published, and not updated often enough for a relevant comparison. PREP numbers must be taken with a few grains of salt. Peter Alfke, Xilinx. Disclaimer: The opinions expressed above are my own, not necessarily those of my employer.Article: 1918
otoe@si.sintef.no (Ola Torudbakken) writes: >In article <DEvyE5.64L@hpqmoea.sqf.hp.com>, mjm@hpqtdzk.sqf.hp.com (Murdo McKissock) writes: >> Ola Torudbakken (otoe@si.sintef.no) wrote: >> >> : I need some recommendation of FPGA's which may achieve a system speed >> : of 40MHz. I'm not interested in hearing about FPGA products which can >> >> XC3100-3 family. Use timing-driven place and route, limit full speed logic to >> 3 levels of CLB combinatorial logic between registers, 1 level from chip >> inputs, and use IOB FFs for all chip outputs. >I've already used them in a previous design. The problem is the >routing resources available. I've had really trouble getting these up >to 20MHz (xc3195a) (large design). I think its possible to go as high >as 30MHz, if you are using a lot of effort with the placing and >routing, but not any further. >You should also remember that the Xilinx people haven't managed to >run a state machine (25 states, 40 transitions) faster than 30MHz, and >still then the design contained only the fsm. So, always look at >fsm designes from the vendor, when you're lookin for speed. > >Ola I must disagree. I have done a moderately complex 40 MHz design using Xilinx XC31xx-5 parts (specificaly a 3190-5 and a 3142-5). After that I did a totally unrelated project and got 40 MHz performance using several XC40xx-4 parts. My most recent project runs at 39 MHz using an XC4010D-4. Each of these projects runs at the spec speed under worst-case timing conditions. Each FPGA contains one or more state machines, some with 30 or more states, and CLB usage is around 70% to 85%. This is not just theory -- these systems are running right now. So it is my experience that 40 MHz operation CAN be achieved with Xilinx XC3100 and 4000 series, using FPGAs of the -4 and -5 speed grade parts. Speeds of well over 50 MHz ought to be possible with the -3 parts. You do have to pay attention to what you are doing (and what the place-and-route tools are doing) but it is certainly possible. Depending on the design, some amount of floorplanning and/or timing-driven routing will be needed. Jonathan Griffitts AnyWare Engineering Boulder, CO -- --JCG AnyWare Engineering, Boulder CO 303 442-0556 (voice or FAX)Article: 1919
>Could someone refer me to some references or sites where I can get info
>on what LFSR counters are? I'm building a system using the Xilinx 4000
Linear Feedback Shift Registers
>series that requires fast FSM's and this would help a lot. Also, would
>there be any sites that contain VHDL code for these counters? Thanks
>in advance.
Not VHDL code, but interesting reading:
Read the "ASIC and EDA", Oct 1994,
"Design tips for high-performance FPGA Design"
by Stephen L. Wasson.
He has some info about the LFSR. Also, get the file
LFSR.ZIP from the HighGate BBS at 408-255-9742.
/======================================================================\
| Bill Banzhof | Webb : http://www.xlnt.com|
| Electronic Engineer | |
| XLNT Designs, Inc. | Voice : 619-487-9320 x236 |
| 15050 Avenue of Science, Suite 200 | Fax : 619-487-9768 |
| San Diego, CA 92128 USA | Internet: bill@xlnt.com |
\======================================================================/
Article: 1920>Does anyone get QuickLogic SpDE 5.0 ? We paid for the maintence >charge to upgrade from 4.0 for a long time but still don't get 5.0 >yet. >Frankie Chung >R & D Manager >Onmate Technology Ltd SpDE 5.0 has been out for a few months. If you did not get your copy, give them a call. John McCaskill.Article: 1921
Try taking a look at the QuickLogic pASIC parts. I have run them in 50 Mhz data path aplications with ease, and they are very good at state machines. The development system is very good. I have used all the pins on a part, fixed them where I wanted them, used 100% of the logic cells and had no problems placing and routing them. I like them, and I recomend them. They have a $100 eval system that they tell me is not striped down from the real version. Call them at 1-800-842-FPGA. John McCaskill mccask@mccaskill.comArticle: 1922
About data typing. My preference is to describe the data types in the terminology of the problem domain at the top level; enumeration types, records, integer ranges, etc. As the design progresses to lower levels, the data types also progress to lower levels. (I may decide to "+" to records (or matrices) together and define the "+" operation in terms of the std_logic_vectors that comprise the matrix elements.) Of course, once this has been completed you discover that your synthesis tool cannot accept record data types as ports. Synthesis vendors are too busy trying to 'beat the other guy's benchmark' by 5 gates or 13 femtoseconds to extend their VHDL source support. I am constantly fighting a battle of how I wish to write VHDL to express my design versus how my synthesis tool will accept the VHDL. VHDL designers are letting the synthesis vendors (especially S.....) dictate how VHDL will be written for synthesis rather than having the synthesis adapt to how the designers develop their designs. [Please do not flame me about the differences between synthesizable VHDL and non-synthesizable VHDL. I am not advocating the synthesis of access types! only more freedom in style and methodology issues.] I am hoping the new 'synthesis standard' will be a good first step. Although I greatly prefer strongly typed languages, one desire that I have had on multiple occasions was a synthesis function that was the equivalent of the Ada 'unchecked_conversion' function. Thus a record that included some constrained integers and some booleans could be immediately converted (without introducing any actual hardware) to a std_logic_vector of the appropriate width and back again. Charles F. Shelor cfshelor@acm.org SHELOR ENGINEERING (817) 467-9367 3308 Hollow Creek Rd VHDL Training and Consulting Arlington, TX 76017-5346Article: 1923
Hello ,
Does anyone know if I can simulate a sheet which
consists of both symbols taken from Xilinx XC3000 library
and symbols based on VHDL description.If you think I can ,
do you know which sequence of steps I sould follow to
simulate the sheet in Mentor Graphics QuickSimII ?
Please e-mail me any replies .
Thanks ,
Evagelia Diamantakou .
Article: 1924
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$1,800. All videotape purchases are restricted for internal use by your
organization. Send check, money order, or purchase order
(made out to the University of Maryland) along with the attached
form to:
Professional Development Assistant (UIS '96),
University of Maryland, Instructional Television System (ITV),
2104 Engineering Classroom Building,
College Park, MD 20742.
On the check or purchase order please write UIS '96.
To process your live satellite downlink registration, we ask that
you register by December 6, 1994. When we receive payment,
we will send the technical information and one set of notes that
can be reproduced to accommodate the number of viewers
at your location. For more information, please call
(301) 405-4905 or FAX (301) 314-9639. e-mail itv@eng.umd.edu
Name: _____________________________________
Title: ______________________________________
Organization: ________________________________
Street Address: _______________________________
City: _______________________________________
State: _______ Zip: ___________________________
Phone: _____________________________________
FAX: _______________________________________
Check one
__ Live downlink $1,600
__ video tape $1,800
The list of ITV sites in the Washington DC/Baltimore area are;
University of Maryland College Park (studio audience)
Bureau of the Census
Department of Defense, Ft. Meade/FANX
NASA Goddard
Defense Mapping (DMA)
Naval Research Lab
Social Security Admn.
CTA
General Accounting Office
SAIC
World Bank
Ft. Ritchie
For more details on attending this broadcast in the
Maryland/DC Virginia area
Call ITV Marketing at 301-405-4905.
FAX: (301) 314-9639
Or e-mail itv@eng.umd.edu
Your organization can join the ITV Network. Send e-mail for details
itv@eng.umd.edu
*If you are an employee or member of the following
organizations/universities, you are member of the
NTU Network and your organization has the capability to
receive this broadcast. Contact your NTU Site Coordinator
for more information. If you need their name and phone
number, call ITV Marketing at 301-405-4905.
Or e-mail itv@eng.umd.edu
When you send e-mail please tell us the name and location of
your organization.
Participating Organizations:
Advanced Micro Devices, Inc
Aeroquip Corporation
Air Products and Chemicals, Inc.
ALCOA
Alliance for Higher Education
Allied Signal Aerospace Company
American Association of Retired Persons (AARP)
AMP Incorporated
Analog Devices, Inc.
Applied Research Laboratory
Argonne National Laboratory
ARINC
Armco Steel Co., L.P.
Army Research Laboratory
AT & T
AT & T Global Information Solutions
AXIOHM IPB
Bellcore
BNR Inc.
Boeing Defense and Space Group
Bull Electronics
Burle Industries Inc.
Burr-Brown Corporation
Colorado Memory Systems
Computing Devices International
datotek, An AT & T Company
David Sarnoff Research Center
Deere & Company
Detroit Diesel Corporation
Digital Communications Associates, Inc.
Digital Equipment Corporation
Eastman Chemical Company
Eastman Kodak Company
Eaton Corporation
Eaton Cutler-Hammer
EG & G Rocky Flats
E.I. du Pont de Nemours & Company
Electronic Data Systems Corporation
E-Systems, Inc.
Ericsson GE Mobile Communications
Evans & Sutherland
Extended Systems, Inc.
Exxon Corporation
GBCS Education & Training
General Electric Company
General Instrument Corporation
Glenayre Electronics Corporation
GM Saginaw Steering
Grass Valley Group
GTE Corporation
Hamilton Standard
Harris Corporation
Hewlett-Packard Company
Honeywell, Inc.
HRB Systems
Hughes Missile Systems Company
IBM
Integrated Device Technology, Inc.
Intel Corporation
Internal Revenue Service
IOMEGA Corporation
John Deere Dubuque Works
K & L Microwave
Knolls Atomic Power Laboratory
Lake Shore, Inc.
Lawrence Berkeley Laboratory
Lawrence Livermore National Laboratory
LEXIS-NEXIS
Lexmark International, Inc.
Lockheed Martin Corporation
Loral Federal Systems Company
Loral Space Information Systems Company
Los Alamos National Laboratory
Magnavox Electro-Optical Systems Company
Magnavox Electronic Systems Company
Mason & Hanger
McDonnell Douglas Aerospace-East
Metrum Information Storage
Michigan Information Technology Network, Inc.
Micron Technology, Inc.
Middle Georgia Technology Development Center
Milliken & Company
The MITRE Corporation
Motorola, Inc.
Naval Air Development Center
Naval Air Engineering Center
Naval Air Systems Command
Naval Air Warfare Center
Naval Research Laboratory
Naval Surface Warfare Center
NASA
National Semiconductor Corporation
Noise Cancellation Technologies
Occidental Chemical Corporation
Pacific Bell
Pacific Tustin
Polaroid Corporation
Prince Corporation
PSE & G Nuclear Training Center
Quantum Corporation
RDL Inc.
Rockwell International Corporation
ROLM Company
Sandia National Laboratories
Santa Barbara Research Center
Schuller International, Inc.
Siemens Medical Systems, Inc.
Symbios Logic, Inc.
Tektronics Consolidated
Texas Instruments, Inc.
3M Company
The Travelers Insurance Company
U.S. West Advanced Technologies, Inc.
U.S. Air Force
U.S. Air Force Academy
U.S. Army
U.S. Bureau of Mines
U.S. Department of Energy
U.S. Mine Safety & Health Admistration
U.S. Navy
US Signal Corporation
Westinghouse Electronic Corporation
Whirlpool Corporation
Xerox Corporation
Zenith Data Systems
Arizona State University
Colorado State University
Columbia University
Cornell University
The George Washington University
Georgia Institute of Technology
GMI Engineering & Management Institute
Illinois Institute of Technology
Iowa State University
Kansas State University
Lehigh University
Michigan State University
Michigan Technological University
New Jersey Institute of Technology
New Mexico State University
North Carolina State University
Northeastern University
Oklahoma State University
Old Dominion University
Purdue University
Rensselaer Polytechnic Institute
Southern Methodist University
The University of Alabama
University of Alaska at Fairbanks
The University of Arizona
University of California at Berkeley
University of California, Davis
University of Colorado at Boulder
University of Delaware
University of Florida
University of Idaho
University of Illinois at Urbana-Champaign
University of Kentucky
The University of Maryland College Park
University of Massachusets at Amherst
The University of Michigan
University of Minnesota
University of Missouri-Rolla
The University of New Mexico
University of South Carolina
University of Southern California
The University of Tennessee, Knoxville
University of Washington
University of Wisconsin-Madison
If you need help contacting the Satellite Coordinator at these
universities, call ITV Marketing at 301-405-4905.
Or e-mail itv@eng.umd.edu
*Unfortunately, this course is only available by satellite throughout
the North American Continent. For other areas of the world, a
videotape will be available.
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