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In article <1994Nov18.031530.22623@afterlife.ncsc.mil>, Chris Tscharner <cgtscha@afterlife.ncsc.mil> wrote: >> >> 2) Which HDL to use: Verilog HDL or VHDL? >> > I would go with Verilog. You can then stay with one language from RTL > all the way to post-route structural code containing delay information. > I believe with VHDL you are probably stuck with going to a proprietary > simulator for the latter at the present time (ex: Viewsim in the case of > Viewlogic). In addition, a unified language enables true mixed level > simulation (some parts of the design hierarchy described as RTL code, > some as schematics, possibly some as post-routed structural code). > Both the Xilinx toolset and the Altera toolset have the capability of > generating post-route Verilog. Neocad now has the same capability for > the FPGAs they support with their toolset. As I understand it VHDL _is_ capable of mixed-level description (e.g., some behavioural, some RTL, some purely structural). In other posts to this newsgroup I have seen several claims that Verilog-to-VHDL translators exist -- which would seem to imply that VHDL is at least as powerful as Verilog. Translating in the other direction is said to be difficult owing to VHDL constructs which have no analog in Verilog. I will readily grant that I've seen no tool set which generates post-route VHDL for Xilinx or any other FPGA. What I'd really like is a synthesis tool which could show what kind of hardware the high-level constructs were actually mapping to -- similar to a compiler giving a mixed source/assembly output. Chris, is this what you are referring to by post-route Verilog? Or is it something more limited -- such as translation of an LCA file into a netlist description without correlating it with your original source code? Mike -- C. M. Heard VVNET, Inc. phone: +1 408 247 9376 4040 Moorpark Ave. Suite 206 fax: +1 408 244 3651 San Jose, CA 95117 USA e-mail: heard@btr.comArticle: 451
In article <3aimv2$845@mailman.etecnw.com>, Richard George <rkg@etecnw.com> wrote: >I'm evaluating some FPGAs for use in a project, and I'm looking for >"horror stories" having to do with the xilinx XC4000 series parts. Actually this is not really a horror story so much as a success story. The project in question (at a place where I'm no longer employed) used XC4005-6 devices as full-speed peripherals on a 25 Mhz 80386-DX local bus. The one XC4005 problem we had on this project was owing to a bad lot of parts: devices with one specific date code (but no others) would 'glitch' the 80386 data bus just as they transitioned from configuration download mode to user mode. This generally caused the 80386 processor to GP fault. Once we swapped out the offending lot of parts we had no further problems. In all other respects we were VERY happy with the 4005s. Probably the conservative design practices of the lead engineer had something to do with this. > I've heard some nasty rumors of difficulties with ground bounce, timing, > etc., [...] I've not heard of this ... do you know where these rumours originated? G'Day, Mike -- C. M. Heard VVNET, Inc. phone: +1 408 247 9376 4040 Moorpark Ave. Suite 206 fax: +1 408 244 3651 San Jose, CA 95117 USA e-mail: heard@btr.comArticle: 452
In Article <3afvn5$969@steel.interlog.com> "David I.Roach" <daver@interlog.com> writes: >Looking for experts/consultants for VHDL & VIEWLOGIC FPGA > The Andraka Consulting Group is a digital hardware design firm specializing in getting maximum performance from FPGAs. Our services include complete design, development, simulation and integration of these devices. We also evaluate, troubleshoot and improve existing designs. Please call or send E-mail for a free brochure. -Ray Andraka, Group Chairman Andraka Consulting Group Tel 401/884-7930, Fax 401/884-7950 Email randraka@ids.net >Article: 453
rkg@etecnw.com writes: > Hi, > I'm evaluating some FPGAs for use in a project, and I'm looking for > "horror stories" having to do with the xilinx XC4000 series parts. > I've heard some nasty rumors of difficulties with ground bounce, > timing, etc., and I was looking for some firsthand accounts of > problems with these beasties. I had heard that the new Xilinx chips were more powerful than ever and I decided to put that rumor to the test. It was a cold and rainy night and I was working late down in the pits of the colliding detector. I could almost feel the anti-proton flux in the air (but of course I knew I was safe since the place is always swarming with safety geeks.) I set my new X4010 chips into the circuit board, attached the X-Cehcker a started a download. About 10 seconds into the download there was a searing lightning strike. There was a crash of thunder followed by the whoosh of helium as the superconducting magnets lost ther containment. I had been lucky: the anti proton beam just missed me. "Whew, I could have been killed", I thought. "Better luck next time" said high squeaky voice that seemed to come from my test equipment. I looked for the source of the voice but couldn't find it. I moved stuff around and when I reached to unplug the smoking mess that was my Xilinx test board, I was knocked on my ass by a bolt of electricity. "Strike two", the little voice said... -- Ground bounce?Article: 454
John, I changed addresses recently and missed that issue (alas!). I'll try and find it somewhere around here. I think benchmarks are good things, and why wouldn't I? Cadence does very well in benchmarks (like Cadence's Leapfrog being the fastest VHDL simulator on the market). As a recently former user and now a tool vendor employee, however, I tend to take a wary approach. It's too easy to focus on specific tasks in a design cycle and lose sight of the overall design process. As a user, I want to know what it's going to take to get my design done, not just how a tool functions on one specific task. The use of more complex tools, such as synthesis tools, means that there is a very real learning curve for the tool, and many user-interface issues that can have a dramatic impact on total usability. Cadence's Synergy synthesis tool, for example, meets or beats the competition in many raw benchmarks. It's real appeal to many of it's users, however, is it's ease of use, integration and pricing. A Learjet is a great way to get to work, but how long does it take to learn how to drive it? How much does it cost? Not to mention the problem of parking! So- I think benchmarks are good, in general, but authors need to make sure not to obscure the impact on the total design methodology by too narrow a focus on individual tasks. standrd disclaimer: my opinions are my own,etc., etc., etc. John WilloughbyArticle: 455
> Hi, > > I'm evaluating some FPGAs for use in a project, and I'm looking for "horror stories" > having to do with the xilinx XC4000 series parts. I've heard some nasty rumors of > difficulties with ground bounce, timing, etc., and I was looking for some firsthand > accounts of problems with these beasties. > > Thanks in advance, > > rkg > > (Richard George) > > One of my senior design student groups managed to blow a 1 cm diameter chunk out of the ceramic package above the die in an XC4003 - does that qualify as a "horror story"? Other than that, the XC4003 and 4005 devices have done quite well in student projects. Vic Nelson Auburn UniversityArticle: 456
Does anybody know any software package that converts Fortran (or C) to VHDL? If this is not the right user group to post this question, can you sugguest me which user group I should post this? ChuArticle: 457
>Hi,
>
>I'm evaluating some FPGAs for use in a project, and I'm looking for "horror stories"
>having to do with the xilinx XC4000 series parts. I've heard some nasty rumors of
>difficulties with ground bounce, timing, etc., and I was looking for some firsthand
>accounts of problems with these beasties.
>
>Thanks in advance,
>
>rkg
>
>(Richard George)
>
>
HORROR 1: _THE_TOOLS_
My project started with 4008 using PC tools. Went to 4010, had to
upgrade to 16 MBytes. Went to 4013, had to upgrade to 32 MBytes. PPR
ran all weekend without a solution. Eventually got NeoCad on the SUN
which generated 65% utilization of the 4013 in a couple of hours.
HORROR 2: _XILINX_NON_SUPPORT_
Xilinx won't tell you about known problems until you rediscover them
yourself. Example 1: The transparent/latch sense for the gates of the
I/O latches are reversed from the XC3000s and incorrect in the 1st AND
2nd editions of their data books. Example 2: First release of PPR for
4013 would not 'honor' pin locations and moved pins freely trying to
improve routing. (Only a problem if you are updating a design that is
already in a PCB!)
Corner your local Xilinx AE and threaten severe mental and physical
anguish if he doesn't tell everything he knows about the part!
HORROR 3: Pullup resistors sometimes 'wear out'. We had several parts
where the pullup resistors got weaker and weaker until we had to add
external pullups.
HORROR 4: Optimistic timing: Preliminary reviews by Xilinx and company
personnel using Xilinx databooks indicated typical operation at 30 MHz
with full temp operation at 24 MHz. We were able to get as high as
20 MHz in the lab with 16 MHz being normal. We never achieved greater
than 12 MHz through the temperature range.
We did not experience ground bounce problems in a 32-bit bidirectional
microprocessor bus interface.
Good Luck,
Charles F. Shelor
SHELOR ENGINEERING VHDL Training, Consulting, and models
3308 Hollow Creek Rd (817) 467-9367
Arlington, TX 76017-5346 cfshelor@acm.org
Rule 1: Never sacrifice global efficiency during local optimization.
Rule 2: Every interaction between two organizations is a
marketing opportunity; make it a positive one!
Article: 458> Hi, > > I'm evaluating some FPGAs for use in a project, and I'm looking for "horror stories" > having to do with the xilinx XC4000 series parts. I've heard some nasty rumors of > difficulties with ground bounce, timing, etc., and I was looking for some firsthand > accounts of problems with these beasties. > > Thanks in advance, > > rkg > > (Richard George) > All products horror stories let me know when you find the *perfect* product. One problem I had with the XC4010 was with the prototype of our EVC. I had hooked a pin to a open-collector buffer that drives a *level* sensitive interupt on the SUN. Every time I loaded the device I would get an interupt. I fixed this by routing a pin the the o-c bufs enable now everything works fine. The interupt line is the only asyncronous line on the SBus and very touchy. So the bottom line is I should have been more careful. Steve CasselmanArticle: 459
In article <3avs3oINNoi0@sun004.cpdsc.COM>, cshelor@cpdsc.com (Charles Shelor) writes: # 2nd editions of their data books. Example 2: First release of PPR for # 4013 would not 'honor' pin locations and moved pins freely trying to # improve routing. (Only a problem if you are updating a design that is # already in a PCB!) The current version (5.0) of the XACT/Mentor tools have this error unless the LOC property is assigned on the top level schematic. They had it fixed, then broke it again in this version. Makes your top-level schematic design really ugly. Aargh! I've also had problems with the tools removing dead circuitry that...wasn't. I think this is due to the same problem as the above comment, though (certain properties don't propagate from level to level, LOC and INIT=gnd being two examples.) # HORROR 4: Optimistic timing: Preliminary reviews by Xilinx and company # personnel using Xilinx databooks indicated typical operation at 30 MHz # with full temp operation at 24 MHz. We were able to get as high as # 20 MHz in the lab with 16 MHz being normal. We never achieved greater # than 12 MHz through the temperature range. Hmmm. I run state machines off a 32MHz clock in a 4005 at room temperature. I'd have to look to see what the data book claims for this chip, though. I also have intermittent problems with the xchecker software not recognizing the xchecker cable unless I remove the cable header from the board and replace it WITH THE BOARD POWERED UP. It just tells me that the xchecker cable is not correctly connected to the system. I break/replace the connection between the xchecker header and the board and it works fine. This happens both on the xilinx demo boards and a wire-wrapped microprocessor interface board we built. --kevin nickels -- | Kevin Nickels - knickels@uiuc.edu | | Home: 210 Kenwood #337 Champaign, IL 61821 | | Office: 217-244-1372 2414 Beckman Institute Urbana, IL 61801 | | Lab: 217-333-9591 268 Everitt Lab Urbana, IL 61801 | The scientist is elated by being confused. -Dudley Hershbach, Harvard University (Nobel Prize, Chemistry, 1986)Article: 460
In article <Czn0oB.E5t@Cadence.COM>, jww@cadence.com (John Willoughby) says: > >So- I think benchmarks are good, in general, but authors need to make sure >not to obscure the impact on the total design methodology by too narrow >a focus on individual tasks. > I can't agree more. The point is quite simple, the raw performance can be boost in some way (Better Hardware, More RAM, etc) However, time cost by bad/stupid user interface can never be reduced. Best Regards. Frankie ChungArticle: 461
Have anyone used the new QuickLogic Design Tools ? It claim to have very good features: VHDL/Verilog Simulation & Synthesis. Does it really work ? Best Regards Frankie Chung Onmate TechnologyArticle: 462
We've been working with a project on Altera-PC for a long
time. When compiling, it comes out that only with soft-buffering option On
it will finish the job, and it uses up too much logic. We've been thinking
about translating the .tdf to .vhd for use with Synonsys in a Sun, to see
wether the logic optimization is better, and not have to use soft
buffering.
Is it worth the trouble or should we just jump directly to Actel?
-------------------------------------------------------------------------
Juan Toledo Cota ESCUELA SUPERIOR DE INGENIEROS
c/ Santa Maria de los Reyes, 8. DE SEVILLA.
41008 Sevilla, SPAIN. toledo@gtex02.us.es
--
-------------------------------------------------------------------------
Juan Toledo Cota ESCUELA SUPERIOR DE INGENIEROS
c/ Santa Maria de los Reyes, 8. DE SEVILLA.
41008 Sevilla, SPAIN. toledo@gtex02.us.es
Article: 463As part of my thesis research, I have been constructing a WWW page on Asynchronous/Self-timed FPGA systems research. The page contains links to most of the Web sources on the topic, a self-timed FPGA bibliography, and some background to my own research on a dedicated self-timed bundled-data FPGA architecture. The page's URL is: http://www.dcs.ed.ac.uk/students/pg/rep/selfTimedFPGA/selfTimedFPGA.html Any suggestions for improvements or additions to the page are welcome. Rob Payne. ------------------------------------------------------- |Rob Payne rep@dcs.ed.ac.uk| |Dept. of Computer Science, University of Edinburgh, UK.| |tel: (+44) 131 650 5169 | -------------------------------------------------------Article: 464
In article <3b2e9r$rri@obelix.cica.es> toledo@gtex02 (Juan Toledo Cota) writes: >From: toledo@gtex02 (Juan Toledo Cota) >Subject: Should I jump to Actel when using Synopsys/Altera? >Date: 24 Nov 1994 16:16:59 GMT > We've been working with a project on Altera-PC for a long >time. When compiling, it comes out that only with soft-buffering option On >it will finish the job, and it uses up too much logic. We've been thinking >about translating the .tdf to .vhd for use with Synonsys in a Sun, to see >wether the logic optimization is better, and not have to use soft >buffering. > Is it worth the trouble or should we just jump directly to Actel? >------------------------------------------------------------------------- >Juan Toledo Cota ESCUELA SUPERIOR DE INGENIEROS >c/ Santa Maria de los Reyes, 8. DE SEVILLA. >41008 Sevilla, SPAIN. toledo@gtex02.us.es Not having used anything but Actel, I can't tell you what would be best. I can say that I have used Actel for years on several designs with very good results. Design turn-around time has been very good and I have always achieved full routing with only minor tweaking. regards, BJB =================================================================== Billy J. Beckworth bjb@bei.pic.netArticle: 465
References: <3aimv2$845@mailman.etecnw.com> <3avs3oINNoi0@sun004.cpdsc.COM> Sender: Followup-To: Distribution: world Organization: US Dept of Defense Keywords: In article <3avs3oINNoi0@sun004.cpdsc.COM> cshelor@cpdsc.com writes: SNIP > >HORROR 4: Optimistic timing: Preliminary reviews by Xilinx and company >personnel using Xilinx databooks indicated typical operation at 30 MHz >with full temp operation at 24 MHz. We were able to get as high as >20 MHz in the lab with 16 MHz being normal. We never achieved greater >than 12 MHz through the temperature range. > Trying to predict timing strictly through use of databooks is dangerous for any FPGAs IMHO. The routing determines timing to a great extent, and it is nondeterministic. A great contributor is device utilization percentage. In addition, efficiency of the designer or designer/follow-on-optimizer (schematics) or synthesizer/optimizer (HDLs) can effect both levels of "atomic logic blocks" (ex CLBs in Xilinx) as well as routability (ex: use of hard macros for floorplanning of complex often used functions like adders). Chris TscharnerArticle: 466
Does anybody know how to preserve active low labels in Viewdraw-XACT5.0? As far as I understand the Change Label Sense command places a tilde in front of an active low label name. This tilde is then changed by WIR2XNF into a hyphen which has a special meaning in Viewsim. I have tried several ways of preserving the label sense by creating a CRS file during WIR2XNF execution. I tehn tried to restore the label sense during XNF2WIR ( -s -c file.crs). However, this was unsuccessful. I find it hard to believe that you can not use active low label in your design. I have now changed all my active low label to "LABEL_L", this does however not improve readabily. Regards, Hans Tiggeler University of SurreyArticle: 467
Juan, > > We've been working with a project on Altera-PC for a long > >time. When compiling, it comes out that only with soft-buffering option On > >it will finish the job, and it uses up too much logic. We've been thinking > >about translating the .tdf to .vhd for use with Synonsys in a Sun, to see > >wether the logic optimization is better, and not have to use soft > >buffering. > I've forwarded your post to an Altera Applications Engineer. She should be able to help you. You probably will be asked to e-mail a copy of your TDF to sos@altera.com once we are back in the office on Monday. Kerry Veenstra kerry@altera.comArticle: 468
In article <H.A.B.Tiggeler.1.000B856B@ee.surrey.ac.uk> H.A.B.Tiggeler@ee.surrey.ac.uk (Hans Tiggeler) writes: > >Does anybody know how to preserve active low labels in Viewdraw-XACT5.0? >As far as I understand the Change Label Sense command places a tilde in front >of an active low label name. This tilde is then changed by WIR2XNF into a >hyphen which has a special meaning in Viewsim. I have tried several ways of >preserving the label sense by creating a CRS file during WIR2XNF execution. I >tehn tried to restore the label sense during XNF2WIR ( -s -c file.crs). >However, this was unsuccessful. > >I find it hard to believe that you can not use active low label in your >design. I have now changed all my active low label to "LABEL_L", this does >however not improve readabily. > >Regards, > >Hans Tiggeler >University of Surrey > Unfortunately, I believe that the solution you are using (using label names that include sense) is the only thing that works reliably. Both the change_label_sense, and the symbol editor's change_pin_sense seem to cause problems either with wir2xnf or later on when backanotating timing. The problem seems to be related to resrictions in the xnf language. The tilde, minus, slash, and backslash all have special meaning somewhere in the whole tool chain, and the conversions that wir2xnf makes seem to just push the problems from one place to another. I went through trying to make sense of the mess about 2 years ago, and was unable to find a reliable way of using the change sense commands. I now either remember which signals are active low, or call them things like write_enable_bar. Wordy, but it does work. I dont believe this has changed in any version of wir2xnf since I last wasted time trying this. There are also problems with the vielogic parameter substitution logic in wir2xnf. Fortunately the only fancy use I had for this has since been solved much more nicely with the new RLOC system. Simple parameter substitutions in viewlogic/wir2xnf still work fine. Basically, substitution works if the first character of the assignment is an '@' character. I tend to create macros with multiple FFs in them, and on each one I will have an attribute like 'LOC=@Q0LOC' and 'LOC=@Q1LOC'. On the instatiated symbol, I will have attributes like '@Q0LOC=CLB_R2C3', and '@Q1LOC=CLB_R4C5'. This works fine. Attributes like 'LOC=CLB_@Q0LOC', with the instantiated symbol having '@Q0LOC=R2C3' does not work because of the position of the '@'. The new RLOC is easier to use and is more sophisticated than the simple substitutions I used to use. All The Best, Philip FreidinArticle: 469
Hi,
we're developping a students course which provides
an insight in VHDL synthesis and FPGA programming.
We're using the Synopsys FPGA compiler and have
ordered the xilinx tools. Since the delivery of these
tools takes a long time (no, this is not Xilinx's fault)
and we like to start synthesizing now, I like to know,
if there is any possibility to get the Synopsys
libaries:
xfpga_xxx.db
xprim_xxx.db
fast (ftp, ... ?) and free of charge?
Thanks
Gunther Lehmann
e-mail: leh@itiv.etec.uni-karlsruhe.de
Article: 470We are evaluating the i-Logix Statemate and ExpressV-HDL packages for use in a large scale simulation project. Are there any current users of either of these tools who would be willing to share their experiences before we make a purchasing decision. You may E-mail me directly or phone (512) 331-3118 8:30-5:30 CST if you wish. Thanks.Article: 471
I have been using MAX7000 parts in my design. Although there have been many problems with the tools, the situation has been improving. All my design is in VHDL. We are running Mentor 8.2 and use AutoLogic for synthesis. Most problems on MAX parts seem to come down to the fact that muxes on the interconnect are partially populated, so if your pins are locked (which is normally the real world scenario anyway) then small design changes can mean your project doesn't fit. This situation has improved in version 5 of MaxPlus2. If your project no longer fits due to pin allocations, it now can find the minimal set of changes to fix the problem. I DONT THINK going to Actel will help your problem, unless the synthesis tool is absolutely top-notch. We have another design here which is presently using 4 x 1460s. Autologic synthesis result was pretty depressing in terms of both utilisation and speed. The designer ended up doing hand synthesis to get what he wanted. Again, the initial design was in VHDL. My impression from running through my own VHDL is that the Altera VHDL option is reasonably good (better utilisation and much faster than AutoLogic) and that place and route for FLEX devices leaves Xilinx and Actel in the dust. Regards Tim LindquistArticle: 472
We are having a little trouble here. Is it right that a digital
comparator (74684 macro-function) uses up 9 macro-cells in
a 5000 series device? We've tried every possible compiler option.
Is it because of the optimiser or the device will just not get anymore?
Thanks.
Article: 473Hi, We are currently using the XC3090PG175 to implement a circit which demands a speed of 25MHz (40ns). However any attempt to reach a speed higher than 12ns has proved futile with the XC3090. (We are only using 38 CLBs and abot 70 I/O pads, 150 speed grade). Are there existing designs which run at higher speeds on the XC3090 and if so any pointers to increase the performance will be greatly appreciated. Please e-mail us at: s1b@eclu.psu.edu Center for Electronic Design, Communication and Computing University Park. Thanks in advance, Sanjay B.Article: 474
From: "Lenihan, William E III" <wlenihan@msmail4.hac.com>
To: John Cooley (ESNUG)
I have heard a little about "VITAL", the VHDL Initiative Toward ASIC
Libraries. My limited understanding of it is that it allows a designs'
gate-level implementation, with real timing, to be 'linked-back' to the
source VHDL code and its' simulator, to enhance verification integrity by
using one common stim/response methodology (i.e. - test bench). Do I have
that right?
(1) Do you know if VITAL's reference to "ASIC Libraries" covers PLD's as well
as the obvious Gate Array/Standard Cell technology?
(2) If not, do you know of any work toward a PLD-targeted effort comparable
to VITAL?
Bill Lenihan
Hughes Aircraft
----
I'm posting this for Bill because he doesn't have access to the vhdl & fpga
newsgroups. Please, feel free to post replies publicly (to benefit the user
community) and to "cc" him via e-mail (to benefit him personally.)
- John Cooley
the ESNUG guy
(and EDA & ASIC Design Consultant, too!)
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3114 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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