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I do not have any manuals !!!! I need the internal names for the signals out of the Macro Cells, I need to use these for internal combinatory logic, and am having problems !!! I can explain further if anyone wan't -- God Bless Chris Abbott ============================================================================Article: 551
Joel Glickman <joel@hibp2.ecse.rpi.edu> writes: >Has anyone successfully implemented PCI on a Xilinx FPGA? Any tips? Yes, even a -4 can be used with some restrictions. If you are referring to the Xilinx VHDL model be aware that they have not ( as of a seminar in late november) built the thing just simulated it. Be sure you have a copy of the formal PCI speck, it is actually readable!. PCI tip: The card is reverse of standard PC (isa) card, be carefull reviwingPCB layout, our first board cam back with the fingers on the wrong side ( A X B ). Did notice before we plugged in, would hav corssed + and- 12V. ( make that crossed in last line) Dont assume that the parity generator is trivial :-( Good Luck, feel free to Email. mmoeller@delphi.com Martin Moeller Moeller, Inc. We do video in Xilinx.Article: 552
I'm looking for documentation on the Library of Parameterized Models (LPM) standard. Network resources and examples would be even better. Has anybody built a VHDL version of LPM? Would a VITAL compliant library be useful to the FPGA community? Thanks for your input. Jose De Castro.Article: 553
Jose De Castro (jose_decastro@mentorg.com) wrote: : I'm looking for documentation on the Library of Parameterized : Models (LPM) standard. Network resources and examples would : be even better. Has anybody built a VHDL version of LPM? : Would a VITAL compliant library be useful to the FPGA community? Contact EIA, The Electronic Industries Association, for a copy of the standard. They've just recently moved and I don't have the new address. LPM is a standard within the EDIF realm. Another source of the LPM standard is NeoCAD. Contact Carle Churgin for information at: Carle Churgin NeoCAD, Inc. 2585 Central Ave. Boulder, CO 80301 (303)442-9121 carle@neocad.com Sorry, can't answer the other questions. -- Jim Kruse NeoCAD, Inc. PGP Public Key available upon requestArticle: 554
Does anyone know the maximim number of configuration bits the XCHECKER cable for XILINX can take? More specifically, has anyone SUCCESSFULLY programmed 5 or more XC4010 in the Serial Slave mode? I'm am presently making a board and need to know if programming 5 XC4010 in a daisy chain is possible. Thanks in advance DaveArticle: 555
I would like to know if you can use the Orcad output from Protel for Windows to feed the Xilinx software. A friend who called Xilinx was told that only Orcad STB-386+ (or something like that) would work properly and that other versions of the Orcad software don't work. This led me to question whether or not the Protel for Windows Orcad output would work. Since I already own Protel, I didn't want to have to buy Orcad and learn yet another user interface. Thanks, PeterMArticle: 556
Peter Montgomery <peterm@fa.disney.com> writes: >I would like to know if you can use the Orcad output from Protel for Windows >to feed the Xilinx software. A friend who called Xilinx was told that only It probably will not work. The Xililinx tools use the raw ( .inf?) net info from Orcad. This is an intermediate netlits that Orcad then reformats into variouse forms. Unles Protel has the same intermediate format it will not work. If protel has a ".xnf" output it may work, but that wold be a Protel tool and would use the Xilinx Orcad tools only for the parts library. Martin Moeller mmoeller@delphi.comArticle: 557
David Yeh <aa179@torfree.net> writes: >Does anyone know the maximim number of configuration bits the >XCHECKER cable for XILINX can take? More specifically, >has anyone SUCCESSFULLY programmed 5 or more XC4010 in the >Serial Slave mode? I'm am presently making a board and >need to know if programming 5 XC4010 in a daisy chain is >possible. Thanks in advance No reason it wont work, the file is read from the disk, no storage in the cable. A quick testif you have a board with one 4010 on it woul be to gen up a ROM image with 5 copies of the config file for the 4010 an try loading that. If that loads almost for sure the string of 5 will work. ( May complain about done bit early, point is to see if it can read the file ) Martin Moelle mmoeller@delphi.comArticle: 558
In article <3dsp7q$2uq@mark.ucdavis.edu> jwcollin@chorizo.engr.ucdavis.edu (Jeff Collins) writes: >Hello. I am designing a system with 2 Xilinx chips, one a 4000 series >and one a 3000 series. The 4008 is the lead device and will be >programmed by a 68k in synchronous peripheral mode. I'm hoping that the >3000 part can be daisy chained and programmed simultaneously. I do >realize that the other control pins are a bit different. > >Can this really work?? The 3000 & 4000 series parts have different frame >styles and a different postamble. > >Thanks, >Jeff >-- >-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- >Jeff Collins jwcollin@engr.ucdavis.edu >Intelligent Manufacturing Systems/ collinsj@ece.ucdavis.edu > Mechatronics Lab, 1065 Bainer Hall collinsj@cs.ucdavis.edu >University of California, Davis jwcollins@ucdavis.edu >-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- > Yes this works. The XC4000 must be the lead device, and the XC3000 part should be in serial daisy chain mode. The differences in framing codes does not effect the lead device (the XC4000), as it only looks at the bits at the beginning that are for it. When it is full, it starts passing the following bits (for the XC3000) from din to dout, and does not look at the bits. After the XC4000 is is full, and passing data to down-stream chips, the only thing it is still doing is counting bits waiting to go done. There should be only 1 header in the file, with the lengthcount field set to the sum of the two bitstream lengths. The makeprom program can do this for you. All the best Philip FreidinArticle: 559
mmoeller@delphi.com wrote: : >I would like to know if you can use the Orcad output from Protel for Windows : >to feed the Xilinx software. A friend who called Xilinx was told that only : : It probably will not work. The Xililinx tools use the raw ( .inf?) : net info from Orcad. This is an intermediate netlits that Orcad then : reformats into variouse forms. Unles Protel has the same intermediate : format it will not work. If protel has a ".xnf" output it may work, but : that wold be a Protel tool and would use the Xilinx Orcad tools only for : the parts library. Martin, I'm not sure I understand your last statement about "that would be a Protel tool". I just heard from Tech support at Protel that the new version of the schematic package has a .XNF output. How would the process work then? I'm assuming that I would create a schematic in Protel, output a netlist in .XNF format, and then feed that to the Xilinx software for routing, etc to create the image file for the EPROM. Is this correct? Would I be able to use the stand parts library in Protel as long as there were matching parts in the Xilinx library? Thanks, PeterMArticle: 560
Last night when I was channel surfing on the TV, I caught a quick snippet of
the PBS Nightly Business Report that was talking about big stock gainers &
losers for the day. The top NASDAQ loser was ViewLogic; it went from
$18.50 down to $9.75 (a 47% drop) in *one* day. That's pretty dramatic for
one day's trading. What's up? They've been picking up some pretty good
EDA companies as subsidiaries for the past few years -- why would investors
suddenly frown on this?
- John Cooley
Part Time Sheep & Goat Farmer
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3114 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 561David: I didn't get your e-mail address. Please re-post your question or send me an e-mail. MihaiArticle: 562
Investor's Business Daily has a front page item about it today (04 Jan), including an "explanation" of the stock price tumble. Have a look.Article: 563
According to the news wires, fourth quarter earnings will be less than expected, but not by much. Also a lawsuit by stockholders has been filed with a complaint that insiders have been selling large amounts of stock recently before the drop. In my opinion, Viewlogic was over bought, and selling at a big premium, but now at 9 1/2, it may be a good buy. Fourth quarter earnings will be released the third week of January.Article: 564
Peter Montgomery (peterm@fa.disney.com) wrote: : mmoeller@delphi.com wrote: : : >I would like to know if you can use the Orcad output from Protel for Windows : : >to feed the Xilinx software. A friend who called Xilinx was told that only : : : : It probably will not work. The Xililinx tools use the raw ( .inf?) : : net info from Orcad. This is an intermediate netlits that Orcad then : : reformats into variouse forms. Unles Protel has the same intermediate : : format it will not work. If protel has a ".xnf" output it may work, but : : that wold be a Protel tool and would use the Xilinx Orcad tools only for : : the parts library. : Martin, : I'm not sure I understand your last statement about "that would : be a Protel tool". I just heard from Tech support at Protel that the new : version of the schematic package has a .XNF output. How would the process : work then? I'm assuming that I would create a schematic in Protel, output : a netlist in .XNF format, and then feed that to the Xilinx software for : routing, etc to create the image file for the EPROM. Is this correct? Would : I be able to use the stand parts library in Protel as long as there were : matching parts in the Xilinx library? : Thanks, : PeterM No, you'd want to convert the old Xilinx OrCad libraries into Protel libraries, and then use *them*. Also, some of the macrocell functions, in fact anything other than the basic elements reference the converted schematics (*.PIN, usually, *.SCH and/or *.SP3 for the source), and may not link in properly to the Protel .XNF file; you're in for a fun time!Article: 565
The plunge in Viewlogic was due to the usual, earnings were less than projected. Wall Street doesn't like surprises. Viewlogic attributed the change due to the fact that sales of HDL products are doing better than expected, at the expense of their schematic-based products. This product change over is effecting their cash flow more than they thought. Also they could not sustain their rapid growth forever. WSJ also has an article in the January 4 edition. -- Fred Rose Honeywell Technology Center e-mail: rose@src.honeywell.com MS-2200 Phone : (612) 951-7106 3660 Technology Dr. Fax : (612) 951-7438 Minneapolis, MN 55418Article: 566
If you need to convert your OrCad schematics to Cadence Concept schematics, I know of a program called ORTRAN from Koalaware. Just give them a fax asking for a PC demo disk at 206-770-2327Article: 567
Stan Eker <seeker@indirect.com> writes: >No, you'd want to convert the old Xilinx OrCad libraries into Protel >libraries, and then use *them*. Also, some of the macrocell functions, in >fact anything other than the basic elements reference the converted >schematics (*.PIN, usually, *.SCH and/or *.SP3 for the source), and may not >link in properly to the Protel .XNF file; you're in for a fun time! If Protel has .xnf output there is a good chance that they also have the libraire converted. Xnf without the libraries and macros would not meanmuch and if they are Orcad comaptible it would not eb hard for them to do. If they do have the libaries and .xnf you would simply feed the .xnf into the Xilixn tool chain as usual. The .pin is now the .inf format, .pin was the earlier Xilinx version that used Dataio net list format. The point is still valid though unless Protel has (or can directly use) the Xilinx library the effort would not be trivial. Martin Moeller mmoeller@delphi.comArticle: 568
In Article <D1zu5s.4FA@eunet.ch> roman@pax.eunet.ch (rroman pollak) writes: >Is there a Software on an Anonymous ftp ,to can programm resp. desing a >fpga with my circuits . >I am a normal mortal person, for my is it vary expensive to buy >the original Software mybe for one or two chips programm. >And for the local distributer have the hole installation , >it is also very expensive . >I would like to build my dream Graphic Processor it is >possible with ttl but with 30-40 ic's. >regards, >roman I am not aware of any low cost software for FPGAs, Xilinx offers a basic package for under $1000, but it is only good for the smaller devices, and is not full featured. I think you have to provide the schematic capture software for that as well. I wholeheartedly agree that it is not cost effective to buy the software to do one or two chips. There is another alternative you may not have considered. I run a consulting firm specializing in high performance FPGA design. One of the things we do is to convert existing designs into FPGA designs. The advantage of using a firm such as mine for someone like you is that we've already invested in the tools and have gained substantial experience using the tools and designing in the parts. My firm uses Viewlogic's Workview Plus along with the specific tools from each of the FPGA vendors. We provide complete design, simulation and integration services for a very reasonable fee. -Ray Andraka Chairman, the Andraka Consulting Group tel 401/884-7930 FAX 401/884-7950 Email randraka@ids.net The Andraka Consulting Group is a digital design firm specializing in getting the maximum performance from FPGAs. Our services include complete design, development, simulation and integration of these devices. We also evaluate, troubleshoot, and improve existing designs. Our background includes high speed pipelined digital signal processors incorporating FPGAs at 40Mhz and beyond. ****We are now supporting Xilinx 5000 series parts***** ****We do Atmel AT6000 (Cache Logic tm) designs*****Article: 569
Is there a Software on an Anonymous ftp ,to can programm resp. desing a fpga with my circuits . I am a normal mortal person, for my is it vary expensive to buy the original Software mybe for one or two chips programm. And for the local distributer have the hole installation , it is also very expensive . I would like to build my dream Graphic Processor it is possible with ttl but with 30-40 ic's. regards, romanArticle: 570
FPD `95: Check out the WEB at
http://www.ee.umanitoba.ca/Conferences/FPD/fpd.html
------------------------------------------------------------------------
The Third Canadian Workshop on Field-ProgrammableDevices: Technology, Tools and
Applications May 29-June 1, 1995, Montreal, Quebec
ADVANCE NOTICE AND CALL FOR PARTICIPATION
------------------------------------------------------------------------
The Ecole Polytechnique de Montreal and the Universite du Quebec a Montreal
will host the Third Canadian Workshop on Field-Programmable Devices (FPD'95).
The goal of this Workshop is to bring together workers from throughout Canada
for a wide-ranging discussion on all forms of field-programmable devices and
their applications. Discussion will focus on industrial applications, advanced
CAD tools and systems, novel system architectures and educational experience.
English will be used for discussions and the principal printed materials, but
contributions can be submitted and presented in either English or French.
SPECIFIC OBJECTIVES AND SCOPE OF THE WORKSHOP
------------------------------------------------------------------------
To continue to provide a forum for discussion on the design and
application of FPGAs
To provide an appropriate forum, both for those in industry and those in
post-secondary education
To allow manufacturers of field-programmable device software and hardware
an opportunity to present their products to a specialized group
To include a wide range of field-programmable devices such as interconnect
components, analog arrays, etc.
To increase the emphasis on designing at the system level, using synthesis
to generate the circuit details
These objectives will be implemented through: -
------------------------------------------------------------------------
Hands-on training -
Tutorials and demonstrations -
Industrial and academic case studies -
Industry, university and educational paper sessions (lecture and/or
poster formats) -
A session on commercial opportunities and business implications
SUBMISSION OF PAPERS
------------------------------------------------------------------------
Prospective participants are invited to submit one (1) copy of an extended
summary to the Organizing Committee Chairs for review. The summary should be no
more than four (4) pages in length, including title pages and figures.
Submissions must be marked "FPD'95 WORKSHOP" and may be in hard copy or
electronic format. Acceptable electronic formats are PostScript, FrameMaker and
WordPerfect. Authors should indicate whether their preferred presentation
format is lecture, poster or demonstration. If possible, authors should also
provide an e-mail address to facilitate rapid communication. Authors of
accepted papers (lecture, poster and demonstration) will be asked to prepare a
camera-ready version for publication in the Workshop proceedings. As this is a
Workshop emphasizing the exchange of ideas and research results, the material
does not have to consist of unpublished results, but novelty is desirable. The
referees will favour material that is of interest to industrial and/or
university users of field-programmable devices.
AUTHORS' SCHEDULE
------------------------------------------------------------------------
Submissions of extended summaries: Friday, January 27
(to Organizing Committee Chairs)
Notification of acceptance: Friday, March 10
Final version of paper: Friday, April 21
Submissions should be addressed to:
------------------------------------------------------------------------
Prof. Mohamad Sawan (Co-Chair)
Ecole Polytechnique de Montreal
Department of Electrical and Computer Engineering
P.O. Box 6079, Station centre-ville Montreal, (Quebec)
H3C 3A7 CANADA
Fax: (514) 340-4147 E-mail: sawan@vlsi.polymtl.ca.
AREAS OF INTEREST
------------------------------------------------------------------------
It is expected that there will be a wide range of discussion topics because of
the versatility of field-programmable device technology. Some suggested topic
areas are: -
Architecture and technology -
Design and development tools -
Industry case studies -
Educators' experiences -
Novel approaches to and utilizations of the technology -
Design approaches -
Business/commercial aspects of the technology -
Entrepreneurial opportunities and support -
System design issues -
Synthesis opportunities for programmable devices -
Partitioning across multiple FPGAs and/or interconnects.
PAPER SESSIONS
------------------------------------------------------------------------
Researchers and industrial users are encouraged to show the results of their
field-programmable device activities - the projects presented can be of an
ongoing nature. Educators are welcome to present experiences with incorporating
field-programmable devices into their curriculum. This is expected to be an
active forum for the exchange of ideas for course and laboratory development.
Industrial users are also encouraged to present case studies utilizing
field-programmable devices in their particular environment. Papers describing
how practical problems have been overcome are welcome. Manufacturers of
field-programmable device software and hardware may also make presentations on
the engineering characteristics of their software and/or devices. We are also
soliciting presentations on the commercial and business aspects of this
technology, including entrepreneurial issues. Examples of topics are: financial
considerations of introducing field-programmable devices into the product life
cycle; when to switch from field-programmable to mask-programmable gate arrays;
etc. A combination of both lecture-style presentations and poster/demonstration
sessions are planned for the workshop. The poster/demonstration sessions are
provided for those applications where it makes more sense to present results
using this format. Ecole Polytechnique may be able (reservation required) to
lend workstations, PCs and other large equipment for use in demonstrations.
Vendors of field-programmable-related products will also have a forum for
demonstrating and promoting their products among workshop attendees.
HANDS-ON SESSIONS
------------------------------------------------------------------------
During this Workshop, we anticipate hosting several hands-on sessions for a
wide variety of users from novice to expert. Plans are being made to include
tutorial sessions given by the major tool and device vendors.
WORKSHOP COMMITTEES ORGANIZING COMMITTEE:
------------------------------------------------------------------------
Mohamad Sawan (Co-Chair), Ecole Polytechnique de Montreal
Telephone: (514) 340-5943,
Fax: (514) 340-4147 -
Jacob Davidson (Co-Chair),
Universite du Quebec a Montreal (UQAM)
Telephone: (514) 987-3323,
Fax: (514) 987-8477 -
Raymond Levesque (Administration),
Ecole Polytechnique de Montreal -
Lynda Moore (Network Communications),
Canadian Microelectronics Corporation
PROGRAM COMMITTEE:
------------------------------------------------------------------------
Paul Chow University of Toronto pc@eecg.utoronto.ca
Jacob Davidson (Co-Chair) Universite du Quebec a Montreal
davidson.jacob@uqam.ca
Baher Haroun Concordia University haroun@ece.concordia.ca
John Knight Carleton University jknight@doe.carleton.ca
Bob McLeod University of Manitoba mcleod@ee.umanitoba.ca
Michael Miller University of Victoria dmill@csr.uvic.ca
Mohamad Sawan (Co-Chair) Ecole Polytechnique de Montreal sawan@vlsi.polymtl.ca
Ted Szymanski McGill University teds@macs.ee.mcgill.ca
Claude Thibeault Ecole de Technologie Superieure thibault@ele.etsmtl.ca
Laurence Turner University of Calgary turner@enel.ucalgary.ca
LOCATION, REGISTRATION AND ACCOMMODATION
------------------------------------------------------------------------
The Workshop will be held at the Ecole Polytechnique de Montreal, 2900 Chemin
de la Polytechnique, May 29-June 1, 1995. Accommodation at the Radisson Hotel
will be available at a special rate from the evening of May 28 (Sunday) until
breakfast on June 2 (Friday), i.e. five nights. Additional nights and
accommodation for non-participants can be arranged (see Registration Form).
Montreal has numerous cultural and tourist attractions. Social programs will be
organized for non-participants.
OTHER USEFUL INFORMATION GENERAL:
------------------------------------------------------------------------
Montreal, a fusion of European style and the American way of life, is one of
the loveliest cities in North America and is situated between the St-Lawrence
River and Mount Royal. After Paris, Montreal is the second-largest
French-speaking city in the world, with the advantage of offering services in
English as well. TRANSPORTATION: Both airports offer convenient public
transportation into downtown Montreal. The one-way shuttle bus fare is $8.50
Cdn. from Dorval and $13.50 from Mirabel. By taxi, the trip into town is about
$25 from Dorval and $60 from Mirabel. In Montreal, there is an extensive bus
and subway network (Montrealers call the subway the "Metro"), and a ticket for
either costs $1.75. WEATHER: During the month of May, temperatures can vary
quite a bit. During the day, they may reach 22 C, or drop to as low as 8 C.
Evenings are generally cool (4 to 10 C).
Article: 571On Tue, 3 Jan 1995 22:37:28 GMT, "David Yeh" <aa179@torfree.net> wrote: > Does anyone know the maximim number of configuration bits the > XCHECKER cable for XILINX can take? More specifically, > has anyone SUCCESSFULLY programmed 5 or more XC4010 in the > Serial Slave mode? I'm am presently making a board and > need to know if programming 5 XC4010 in a daisy chain is > possible. Thanks in advance > > Dave > Hi Dave, If you have one of the old parallel port download cables, then that definitly has no limit. The file simply seams to get read from disk as the bits are spat out the parallel port, one bit at a time. The only problem with that is that as the Xilinx devices have got faster, they have become more sensitive to glitches (and hence ringing) during download. The only big benifit with the XCHECKER is that the leads are short and ringing is not a problem. I like the old DOWNLOAD cable but after a lot of heartache & study, I have deciced that the only correct solution to the ringing problem is by adding an active buffer (74HC14) at the Xilinx end of the cable. Some old Xilinx manuals gave the schematic of the parallel download cable, so you could make one if you havn't got one handy (but watch out for ringing). I am asuming that you are not running long leads from the body of the xchecker head. Regards Michael.Article: 572
Request for Discussion (RFD)
Newsgroup : comp.cad.viewlogic
Status : unmoderated
Distribution : Worldwide
Summary : For discussion of Viewlogic's CAD software
Proponent : Scott Murphy (scott@gordian.com)
This is a formal Request For Discussion on the creation of an unmoderated
newsgroup, comp.cad.viewlogic.
This RFD has been posted in accordance with the Guidelines for Newsgroup
Creation. Its language is based on previously submitted RFDs. The RFD is
being cross-posted to the following relevant news groups:
news.announce.newgroups
comp.cad.synthesis
comp.arch
comp.arch.fpga
comp.lang.verilog
comp.lang.vhdl
sci.electronics.cad
CHARTER
The comp.cad.viewlogic newsgroup will be open to discussion of the use of
and any problems or conditions arising from the use of Viewlogic's Powerview
and Pro series CAD software. Specific topics may include but are not limited
to:
Installation Design methodology
Security Verification and Validation
Bugs Vhdl
Customization Product enhancement
This group is not affiliated with Viewlogic, but it is hoped, that employees
of Viewlogic will participate in the discussions.
RATIONALE
As Viewlogic has grown, it's software has evolved from a simple pc based
schematic capture system into a full electronic design package. This growth
has increased the difficulty in effectively using and maintaining that
software. This forum will provide users of Viewlogic's software a place to
solve problems and share ideas. It is hoped, that Viewlogic will use this
group to aid their customers, and to solicite information about those customers
needs.
MAILING LISTS
No know lists exist.
FUTURE CALL FOR VOTES
After a discussion period of 21-30 days, if there are no overwhelming
objections to the proposed group, there will be a Call For Votes (CFV)
posted to the same groups as this RFD. The voting period will be at least
21 days. If the group passes by receiving 100 more YES votes than NO
votes, and (at least) twice as many YES votes as NO votes, it will be
created.
--
__________________________________________________
| |
| homebrew is the elixir of the gods |
| |
Article: 573I want to find Bhat's work using library patterns for FPGAs based on 2-input LUT. Could anyone help me? Thanks. -- =============================== Hsien-Ho Chuang eea80593@yankees.ee.nctu.edu.tw ===============================Article: 574
I want to find some information about look-up table-based FPGA made be Motorola. Could anyone help me? Thanks. -- =============================== Hsien-Ho Chuang eea80593@yankees.ee.nctu.edu.tw ===============================
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