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Messages from 154100

Article: 154100
Subject: Re: Burn to an internal prom Spartan-3an
From: Gabor <gabor@szakacs.invalid>
Date: Tue, 07 Aug 2012 11:22:29 -0400
Links: << >>  << T >>  << A >>
userkan@gmail.com wrote:
> 7 Haziran 2010 Pazartesi 16:12:22 UTC+3 tarihinde izaak yazd─▒:
>> I use an internal memory Spartan 3an
>> When I try to burn only the FPGA I can!
>> Even when I try to burn the FPGA and the prom
>> I get in the middle of the recording process failed!
>> And the reason he failed is:
>> "'1': Configuration data download to FPGA was not successful. DONE did not
>> go high, please check your configuration setup and spi mode settings.
>> PROGRESS_END - End Operation."
>>
>> Would love to get any help
>> Thanks!
>>
>> 	   
>> 					
>> ---------------------------------------		
>> Posted through http://www.FPGARelated.com
> 
> Hi Izaak,
> I'm experiencing exactly the same problem with you. I could not find a solution yet. Did you find the source of the problem and any solution? 
> I would appreciate if you can help.
> Thanks.
> Serkan.
A common issue that can cause this is wrong Mode pin settings.  Check
that your Mode and VS pins are tied as in the configuration user's
guide.  Also if you use a resistor to pull Mode or VS pins low,
make sure the value is less than 1K to overcome the internal
pullups in the Spartan 3 AN.

-- Gabor

Article: 154101
Subject: Re: Burn to an internal prom Spartan-3an
From: Jon Elson <jmelson@wustl.edu>
Date: Tue, 07 Aug 2012 14:29:28 -0500
Links: << >>  << T >>  << A >>
userkan@gmail.com wrote:

> 7 Haziran 2010 Pazartesi 16:12:22 UTC+3 tarihinde izaak yazd─▒:
>> I use an internal memory Spartan 3an
>> When I try to burn only the FPGA I can!
>> Even when I try to burn the FPGA and the prom
>> I get in the middle of the recording process failed!
>> And the reason he failed is:
>> "'1': Configuration data download to FPGA was not successful. DONE did
>> not go high, please check your configuration setup and spi mode settings.
>> PROGRESS_END - End Operation."
>> 
I am using Spartan XC3S50AN parts with the Xilinx Parallel Cable III
and it works fine.  I am using ise 10.1  Not much else I can say,
it just works.

Jon

Article: 154102
Subject: spartan 6 ddr2 pinout
From: colin <colin_toogood@yahoo.com>
Date: Wed, 8 Aug 2012 01:09:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
I've just run a DDR2 based MIG through place and route and tried the simple=
st of pin swaps, which failed. The default pinout is terrible for PCB routi=
ng, does anyone know whether any swapping is possible if I drill down throu=
gh the code. I had hoped that the hard silicon ddr core just made clock dom=
ain control trivial, with the functional stuff still soft.

Has anyone tried this?

Cheers

Colin

Article: 154103
Subject: Re: Burn to an internal prom Spartan-3an
From: userkan@gmail.com
Date: Wed, 8 Aug 2012 01:47:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
Thanks a lot Gabor,

Reducing pulldown resistors on mode pins solved the problem...

Serkan.

Article: 154104
Subject: Re: spartan 6 ddr2 pinout
From: Gabor <gabor@szakacs.invalid>
Date: Wed, 08 Aug 2012 08:47:06 -0400
Links: << >>  << T >>  << A >>
colin wrote:
> I've just run a DDR2 based MIG through place and route and tried the simplest of pin swaps, which failed. The default pinout is terrible for PCB routing, does anyone know whether any swapping is possible if I drill down through the code. I had hoped that the hard silicon ddr core just made clock domain control trivial, with the functional stuff still soft.
> 
> Has anyone tried this?
> 
> Cheers
> 
> Colin

The core to IO routing is fixed.  That being said there are some groups
of pins that are swappable because they are equivalent.  For example
DQ pins within a byte can swap at the board level.  Or you can swap
the entire upper and lower DQ DM and DQS sets.  Unfortunately you
can't swap address pins.  I can't think why you couldn't re-arrange the
bank address pins, though.  I seem to remember that there was an
Answer Record discussing pins swapping with the MCB.

-- Gabor

Article: 154105
Subject: Re: spartan 6 ddr2 pinout
From: nico@puntnl.niks (Nico Coesel)
Date: Wed, 08 Aug 2012 17:12:30 GMT
Links: << >>  << T >>  << A >>
Gabor <gabor@szakacs.invalid> wrote:

>colin wrote:
>> I've just run a DDR2 based MIG through place and route and tried the simplest of pin swaps, which failed. The default pinout is terrible for PCB routing, does anyone know whether any swapping is possible if I drill down through the code. I had hoped that the hard silicon ddr core just made clock domain control trivial, with the functional stuff still soft.
>> 
>> Has anyone tried this?
>> 
>> Cheers
>> 
>> Colin
>
>The core to IO routing is fixed.  That being said there are some groups
>of pins that are swappable because they are equivalent.  For example
>DQ pins within a byte can swap at the board level.  Or you can swap
>the entire upper and lower DQ DM and DQS sets.  Unfortunately you
>can't swap address pins.  I can't think why you couldn't re-arrange the
>bank address pins, though.  I seem to remember that there was an

AFAIK you can't because the BA pins are also used during configuration
to select the configuration register. Anyway, the routing of the
address and control lines is way less critical than the data lines.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

Article: 154106
Subject: Re: spartan 6 ddr2 pinout
From: Gabor <gabor@szakacs.invalid>
Date: Wed, 08 Aug 2012 15:14:00 -0400
Links: << >>  << T >>  << A >>
Nico Coesel wrote:
> Gabor <gabor@szakacs.invalid> wrote:
> 
>> colin wrote:
>>> I've just run a DDR2 based MIG through place and route and tried the simplest of pin swaps, which failed. The default pinout is terrible for PCB routing, does anyone know whether any swapping is possible if I drill down through the code. I had hoped that the hard silicon ddr core just made clock domain control trivial, with the functional stuff still soft.
>>>
>>> Has anyone tried this?
>>>
>>> Cheers
>>>
>>> Colin
>> The core to IO routing is fixed.  That being said there are some groups
>> of pins that are swappable because they are equivalent.  For example
>> DQ pins within a byte can swap at the board level.  Or you can swap
>> the entire upper and lower DQ DM and DQS sets.  Unfortunately you
>> can't swap address pins.  I can't think why you couldn't re-arrange the
>> bank address pins, though.  I seem to remember that there was an
> 
> AFAIK you can't because the BA pins are also used during configuration
> to select the configuration register. Anyway, the routing of the
> address and control lines is way less critical than the data lines.
> 
O.K. - I found the answer record:

http://www.xilinx.com/support/answers/34153.htm

-- Gabor

Article: 154107
Subject: Re: spartan 6 ddr2 pinout
From: "maxascent" <56@embeddedrelated>
Date: Wed, 08 Aug 2012 15:15:56 -0500
Links: << >>  << T >>  << A >>
It's not the best pinout but it can be routed on a 6 layer board as I have
done it with a lx45 with two 16-bit DDR3 on either side of the device.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 154108
Subject: Re: spartan 6 ddr2 pinout
From: colin <colin_toogood@yahoo.com>
Date: Thu, 9 Aug 2012 00:17:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
Thanks for everyones replies.
The last time, I had an 80 bit wide DDR2 interface to virtex 5 and I spent ages playing with the pinout so I suppose that Xilinx have saved me some time as I can't play.

Article: 154109
Subject: xilinx fir compiler
From: "kaz" <3619@embeddedrelated>
Date: Thu, 09 Aug 2012 12:54:43 -0500
Links: << >>  << T >>  << A >>
I have used altera DSPBuilder for several multichannel multirate filter
designs. 
I have heard that xilinx fir compiler(latest one possibly) can process 
multichannels even if they have different input sampling rates on same
single 
path. 

Is that true? 

There is another restriction with altera upsampling fir: The input samples
must
not be applied in immediate succession i.e. samples must be dispersed apart
to
give room to new samples at output. Does this apply to xilinx fir compiler
as
well.

Thanks in advance

Kaz

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 154110
Subject: Re: xilinx fir compiler
From: Benjamin Couillard <benjamin.couillard@gmail.com>
Date: Thu, 9 Aug 2012 19:44:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
The best way to find out is to simulate the an instantiated core with Modelsim or Active-HDL or any other simulator.

About the upsampling FIR : If the processing clock is 100 MHz, the input sample rate is 50 MHz and the ouput sample rate. Then by definition, you can only have one new input sample every other clock cycle.

Article: 154111
Subject: Spartan 3AN prevent readback ?
From: Jon Elson <elson@pico-systems.com>
Date: Thu, 09 Aug 2012 22:23:32 -0500
Links: << >>  << T >>  << A >>
I am trying to prevent readback of the bit file from a
Spartan 3AN.  I am using ise 10.1 (need to keep that
for a while to support some older devices).  I looked
up how to do it in a Xilinx tutorial, but it doesn't seem
to work.  They say to go into generate programming file/
properties/readback options, and set it for disable readback
and reconfiguration.  I set this, regenerated the bit file,
but after programming the device with Impact, I can still
verify the config.  I'm assuming if you disable readback,
you can no longer verify the device, right?

I also tried all combinations in Impact, which are
data protect and data lockdown, these didn't seem to
prevent verify, either.

(I did a separate verify AFTER the one done automatically
when programming, presumably the read protect would be
set after the initial verify.)

Anyone been able to do this and know what I missed?

Thanks,

Jon

Article: 154112
Subject: Re: Spartan 3AN prevent readback ?
From: Jon Elson <elson@pico-systems.com>
Date: Thu, 09 Aug 2012 23:39:44 -0500
Links: << >>  << T >>  << A >>
Jon Elson wrote:

> I am trying to prevent readback of the bit file from a
> Spartan 3AN.

One additional tidbit of info, if you read the bitgen
report, it shows Readback as (Not Specified)*
so it looks like the GUI system is not passing the
disable readback requirement to bitgen.

Do I have to run bitget from the command line?
I've never done that before.

Thanks,

Jon

Article: 154113
Subject: Re: xilinx fir compiler
From: "kaz" <3619@embeddedrelated>
Date: Fri, 10 Aug 2012 01:26:26 -0500
Links: << >>  << T >>  << A >>
>About the upsampling FIR : If the processing clock is 100 MHz, the input
sample rate is 50 MHz and the ouput sample rate. Then by definition, you
can only have one new input sample every other clock cycle.
>

That is true but I might have my input samples coming in at 100 MHz say as
pairs of sample1 then 2 then two invalid clocks valid pattern of 1100.
instead of 1010. 

Thanks	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 154114
Subject: Re: Spartan 3AN prevent readback ?
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Fri, 10 Aug 2012 09:56:47 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Thu, 09 Aug 2012 23:39:44 -0500, Jon Elson wrote:

> Jon Elson wrote:
> 
>> I am trying to prevent readback of the bit file from a Spartan 3AN.
> 
> One additional tidbit of info, if you read the bitgen report, it shows
> Readback as (Not Specified)*
> so it looks like the GUI system is not passing the disable readback
> requirement to bitgen.

Quite possible.

> Do I have to run bitget from the command line?
> I've never done that before.

Worth learning how.

After using it in GUI, there should be a "command log" file (apologies 
for vagueness, it's been a while since I used 10.x) in the project 
folder. This will contain the command lines generated by the GUI. You can 
use these as a starting point and add the flags you need in a text editor.

http://forums.xilinx.com/t5/Hierarchical-Design/bitgen-command-line-vs-
documentation/td-p/94148
may be useful. There is a link there to more documentation.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_3/
devref.pdf
is the right manual for the wrong ISE version but there ought to be a 
devref.pdf in the "docs" folder of your installation.

Having started this route, you may find it easy to write a shell script 
(batch file if you're still using Windows) to repeat a complex series of 
commands such as rebuilding a stable design.

I still use the GUI for experiments, new designs, until they are 
reasonably stable, then create a shell script for consistency.

- Brian


Article: 154115
Subject: Re: Spartan 3AN prevent readback ?
From: Jon Elson <elson@pico-systems.com>
Date: Fri, 10 Aug 2012 11:55:21 -0500
Links: << >>  << T >>  << A >>
Brian Drummond wrote:


> After using it in GUI, there should be a "command log" file
Yes, I've got this in the bitgen report, it is 6 lines long
with TONS of switches.  Well, I'll try it.  But, is it true
that bitgen is where the bitfile protection is controlled for
the Spartan 3AN with Impact?  With CPLDs, it is an option
in Impact.

Thanks,

Jon

Article: 154116
Subject: RE: Problem in Xilkernel
From: Jone_yang <15108310803@163.com>
Date: Fri, 10 Aug 2012 13:00:05 -0500
Links: << >>  << T >>  << A >>
I have got the same problem.What is the reason?How do you solve it?
I really need your help.
Thank you very much!

--http://compgroups.net/comp.arch.fpga/problem-in-xilkernel/78179



Article: 154117
Subject: Re: Spartan 3AN prevent readback ?
From: Gabor <gabor@szakacs.invalid>
Date: Fri, 10 Aug 2012 16:11:18 -0400
Links: << >>  << T >>  << A >>
Jon Elson wrote:
> Brian Drummond wrote:
> 
> 
>> After using it in GUI, there should be a "command log" file
> Yes, I've got this in the bitgen report, it is 6 lines long
> with TONS of switches.  Well, I'll try it.  But, is it true
> that bitgen is where the bitfile protection is controlled for
> the Spartan 3AN with Impact?  With CPLDs, it is an option
> in Impact.
> 
> Thanks,
> 
> Jon
Are you talking about reading back the bitstream from the FPGA
or from the attached SPI flash?  I was under the impression that
bitgen only controls whether you can read back the bitstream
from the FPGA itself.  If you use the SPI flash embedded in the
Spartan 3AN, then I'm pretty sure anyone can read it back.

-- Gabor

Article: 154118
Subject: Re: Spartan 3AN prevent readback ?
From: Jon Elson <jmelson@wustl.edu>
Date: Fri, 10 Aug 2012 17:16:47 -0500
Links: << >>  << T >>  << A >>
Gabor wrote:


> Are you talking about reading back the bitstream from the FPGA
> or from the attached SPI flash?  I was under the impression that
> bitgen only controls whether you can read back the bitstream
> from the FPGA itself.  If you use the SPI flash embedded in the
> Spartan 3AN, then I'm pretty sure anyone can read it back.
Assuming this is possible, what I want to do is prevent readback
of the internal flash memory of the Spartan 3AN.  So, yes, I guess
I want to prevent readback from EITHER the live FPGA config OR
the flash memory inside the chip.

I thought this was possible, but further reading of Xilinx docs
just gets me confused.  Well, it is not a critical situation, but
I did want to protect my little bit of IP if it just required
clicking a button on the GUI or so.

Jon

Article: 154119
Subject: My Spartan3 video
From: Thorsten Kiefer <thorstenkiefer@gmx.de>
Date: Mon, 13 Aug 2012 15:04:31 +0200
Links: << >>  << T >>  << A >>
Hi,
I'm not sure, if I posted it allready, but here is my video again :

http://www.youtube.com/watch?v=ATiqjJi05IU

- Thorsten

Article: 154120
Subject: Re: My Spartan3 video
From: Gabor <gabor@szakacs.invalid>
Date: Mon, 13 Aug 2012 09:26:54 -0400
Links: << >>  << T >>  << A >>
Thorsten Kiefer wrote:
> Hi,
> I'm not sure, if I posted it allready, but here is my video again :
> 
> http://www.youtube.com/watch?v=ATiqjJi05IU
> 
> - Thorsten

Wow!  I'm dizzy.  Have you thought about getting a tripod?
Or at least reducing your caffeine intake?  ;-)

Nice work :-)


-- Gabor

Article: 154121
Subject: Re: My Spartan3 video
From: Thorsten Kiefer <thorstenkiefer@gmx.de>
Date: Mon, 13 Aug 2012 18:07:05 +0200
Links: << >>  << T >>  << A >>
Am 13.08.2012 15:26, schrieb Gabor:
> Thorsten Kiefer wrote:
>> Hi,
>> I'm not sure, if I posted it allready, but here is my video again :
>>
>> http://www.youtube.com/watch?v=ATiqjJi05IU
>>
>> - Thorsten
>
> Wow!  I'm dizzy.  Have you thought about getting a tripod?
> Or at least reducing your caffeine intake?  ;-)

No sorry, caffeine is my basic food :D

>
> Nice work :-)

Thanks

>
>
> -- Gabor


Article: 154122
Subject: Re: xilinx fir compiler
From: Benjamin Couillard <benjamin.couillard@gmail.com>
Date: Tue, 14 Aug 2012 08:02:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
I need more information. What core version, how many taps?

Anway like I said before, the best way is to simulate the design in Modelsim. Try the impulse response, step response, white noise, chirp response, etc. and compare the results to the one you would get in Matlab (or Octave).



Article: 154123
Subject: "Decimals" word in binary space
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Wed, 15 Aug 2012 13:35:55 +0200
Links: << >>  << T >>  << A >>
Im looking for an equivalent word for "decimal" in a binary number. The 
"deci" says it's all about base 10 numbers, but I miss an official term for 
the 1/(2^n) digits. I'm using "binimals"  in lack of a better word.
Also, is there a binary world equivalent for the "decimal" point?


Article: 154124
Subject: Re: My Spartan3 video
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Wed, 15 Aug 2012 13:42:04 +0200
Links: << >>  << T >>  << A >>
Have you tried to see how many iterations you can fit in if you do this in 
parallel realtime, and maybe add a fixed # of frames delay (using mem for 
saving temporary result) to expand # of iterations?




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