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Greg Neff wrote in message <88t88r$ari$1@nnrp1.deja.com>...
>In article <87v2b1$2ecj$1@noao.edu>,
> "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> wrote:
>(snip)
>>
>> The signals that go between the 80 and 40 MHz domains are simply
>flags that
>> get set or reset. These flags are used as clock enables (like, "turn
>> counter 3 on or off").
>>
>
>Better late than never...
and I'm even later responding. spent last week at the telescopes.
>Careful with the simple flags assumption. CE gets routed to ALL flops
>in the counter. If you have a timing violation on your flag when it
>changes state, then some flops might enable, and some might not. If
>this happens, then your counter output will be indeterminate, and
>potentially metastable. I have seen real and reproducible effects from
>this kind of failure mode,
that's an excellent point.
>as well as failures caused by clocks not
>routed on global clock assets.
My original thought, after seeing trce complain about something using
non-global resources, was that I had to find the problem and fix it.
Unfortunately, the xilinx tools don't have an "easy" way to tell which
flops, if any, are driven by non-global resources. I even tried printing
the chip from FPGA Editor to a color E-size plot, with my two BUFGLSed
clocks highlighted. Unfortunately, the plot was gray-scaled. Anyways, it
appears as if, in fact, all flops ARE clocked by a BUFGLSed clock signal.
>I have seen companies (yes, plural) that are shipping mission and
>safety critical products with incorrect FPGA clock implementation. They
>simply ignore the warnings from the Xilinx software, without giving it
>a second thought.
Rant noted. I remembered the rule I learned about C programming. "Turn all
warnings on, all the time." Seems reasonable that it should apply here.
And even more reasonable that the warnings - and timing failures - should be
heeded!
>Normally, we use one clock for the FPGA, and route slower frequency
>chip enables around to the flops. This can cause problems with routing
>resources, especially in older FPGAs. We have also implemented designs
>just the way you have now, but we treated all signals passing between
>clock domains as asynchronous, and used multi-stage registers to
>synchronous signals between domains. This works when you have more
>leftover flops available than routing resources.
I remembered why I wanted the divided-by-two clock. turns out that I'm
using a CORE FIFO in the chip and the datasheets tell me that it won't work
with an 80-MHz clock. I noticed that AFTER I'd done the design, with the
single 80 MHz clock, and it failed timing. RTFDS, I guess.
there's plenty of flops left in the design. I like the idea of resyncing in
the other domain. this design is such that if there's a couple of stages of
pipeline delay, it's not a problem.
thanks much for the advice.
--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20926Hiya, The quickest way would be to donwload a RS codec SW implementation. The generator polynomials can be usually found in the .h header file. rgd, Umesh Gowda "Pradeep Rao" <pradeeprao@planetmail.com> writes: >Hi, >I'm working on a Reed-Solomon codec RS(255,239). >Does anyone know where I might find tables for the generator polynomial >coefficients for different values of (n,k). >I've tried deriving them from the pimitive polynomial but it gets too >cumbersome to do it on paper for such large values. >Thanks in anticipation, >Regards, >Pradeep RaoArticle: 20927
Xilinx foundation 1.5
XABEL 6.3
The following example was modified from the Xilinx help file. What I
basically want to know is if, for each state, should the outputs change
prior to the execution of the goto statements. What happens when I try
to simulate the following code, is that the outputs stay stuck high.
But this changes based on the way my states are set up. For example, if
I were to change State three to:
State s3: outputs = [0,0,1];
goto s3;
and basically have an infinite loop unto itself, then I see the outputs
go from [1,1,1] to [0,0,1] . I never see the first two states execute.
What I want to see is the states change automatically with every clock
cycle. Any ideas about what I'm doing wrong?
Thanks, Chuck
module onehot
Title 'onehot'
Declarations
a PIN ;
b PIN ;
c PIN ;
clk PIN;
outputs2..outputs0 PIN ;
outputs = [outputs2..outputs0];
sbit STATE_REGISTER istype 'reg';
s1, s2, s3 STATE;
Equations
sbit.clk = clk;
sbit.ap=0;
State_Diagram sbit
State s1: outputs = [1,0,0];
goto s2;
State s2: outputs = [0,1,0];
goto s3;
State s3: outputs = [0,0,1];
goto s1;
end onehot;
Article: 20928
Hi all,
I need to implement an 8-bit register that can be written asynchronously
from two CPUs, in a Cypress CPLD.
Will the following always work?
library ieee;
use ieee.std_logic_1164.all;
entity async is
port (
reset : in std_logic;
cpua_wr_not : in std_logic;
cpua_data : in std_logic_vector (7 downto 0);
cpub_wr_not : in std_logic;
cpub_data : in std_logic_vector (7 downto 0);
outport : out std_logic_vector (7 downto 0)
);
end async;
architecture async_arch of async is
begin
process (reset, cpua_wr_not, cpua_data, cpub_wr_not, cpub_data)
begin
if reset = '1' then
outport <= "00000000";
elsif cpua_wr_not = '0' then
outport <= cpua_data;
elsif cpub_wr_not = '0' then
outport <= cpub_data;
end if;
end process;
end async_arch;
The Warp compiler turns it into equations like this:
outport(7) =
/reset * cpua_wr_not * cpub_wr_not * outport(7).CMB
+ /reset * cpua_wr_not * /cpub_wr_not * cpub_data(7)
+ /reset * /cpua_wr_not * cpua_data(7)
Ignoring the situation when the two CPUs are writing near-simultaneously,
will this kind of flipflop always work?
At the end of CPU A's write cycle where cpua_wr_not goes high and "control"
switches from the third to the first of the three prouct terms, can I be
sure that cpua_data(7) is actually latched in outport(7), and not some
glitch because of product term "speed" mismatch?
Or am I just paranoid?
Regards,
Karl Olsen
Article: 20929The kit does NOT contain a simulator, just synthesis and place & route. I have tried the kit with a processor interface design and an 8-bit adder and counter. It seemed to work very well, but I have not tested the result on hardware yet. Wiggo. myself wrote: > hi i just ordered the atmel fpga starter kit and will receive it in a > few weeks. > Does anybody have any experiance with them? What did you think? -- +---------------------------------------------------------------+ | Wiggo Olufsen | | Cypress Software AS Phone : +47-73-52 46 59 | | P.O.Box 2668 Fax : +47-73-52 46 80 | | N-7415 TRONDHEIM E-mail: wiggo.olufsen@online.no | | NORWAY | +---------------------------------------------------------------+ Linux is like a wigwam. No windows, no gates, and an Apache inside.Article: 20930
Does anybody know of a resource (web, book or article) describing architecture design for systems, storage or logic, whose components are prone to very high rate of failure, along the line of 0.1%-1%?Article: 20931
Well, it appears to be a Xilinx JTAG programmer problem. When I cut and jump the JTAG chain so the SPROM is before the FPGA, it erases, blank checks, programs and verifys fine! Of course, I specifically asked Xilinx if the chain order mattered, and was told no (and it shouldn't matter), but I guess no one ever tried out the simple combination of FPGA->SPROM... Austin Franklin <austin@da33rkroom.com> wrote in article <01bf80dc$79ef7580$207079c0@drt1>... > Minor update...according to the Xilinx web site, verify doesn't work. > Great. The only way to see if it was programmed is to look at the bit > stream (or let it program the FPGA and look for DONE)...but I currently get > all 1's out of the SPROM...as if it wasn't programmed at all. > > Also, the JTAG programmer claims it programs the SPROM just fine, and that > I can erase it just fine, but it fails blank check.... I'm led to believe > it just isn't programming the 1804 at all...even though it says it did. > > > Austin Franklin <austin@da33rkroom.com> wrote in article > <01bf80d1$393e2f00$207079c0@drt1>... > > I've got a board with one XCV300 and one SPROM (VQ-44) in a JTAG chain. > > The Virtex is first in the chain. I had an 1802 as the PROM, and it gave > > me an error when I tried to program it (saying it was read protected, and > > even erasing it wouldn't help), so Xilinx suggested replacing it with an > > 1804. Now I can program the SPROM, but it won't verify, and doesn't > appear > > to work. > > > > The Virtex loads just fine over JTAG, and works. No problems there. Has > > anyone had similar problems with the 1804, and has anyone gotten one to > > work? Voltage and pinouts all checkout fine, the JTAG programmer > > recognizes it just fine.... > > > > Thanks > > > > > > > > >Article: 20932
Hi,All, When I install Foundation2.i1, the startup splash screen appears, but then dissappears and install fails without errors. I enter Ctrl+Alt+Del, I can see Java is runing, but after a while, Java dissappers. I waited for a long time, but nothing happened. Before installation, I exit all other application programs. Before Foundation2.1i installation, I installed synopsys FPGA Express3.1 and Xilinx service package on it, and uninstalled service package incorrectly. But then I reinstalled them and uninstalled them correctly. I checked www.xilinx.com, the Answer Database Record#7074 didn't answer my question. The PC is Windows98 Second Edition,Pentium200M,32M Ram, 650M free disk space. The Foundation2.1i package is OK, because I tryed on other PC with Windows95, no problems. Thanks in advance.Article: 20933
Andy Peters wrote: ...snip... > >Normally, we use one clock for the FPGA, and route slower frequency > >chip enables around to the flops. This can cause problems with routing > >resources, especially in older FPGAs. We have also implemented designs > >just the way you have now, but we treated all signals passing between > >clock domains as asynchronous, and used multi-stage registers to > >synchronous signals between domains. This works when you have more > >leftover flops available than routing resources. > > I remembered why I wanted the divided-by-two clock. turns out that I'm > using a CORE FIFO in the chip and the datasheets tell me that it won't work > with an 80-MHz clock. I noticed that AFTER I'd done the design, with the > single 80 MHz clock, and it failed timing. RTFDS, I guess. > > there's plenty of flops left in the design. I like the idea of resyncing in > the other domain. this design is such that if there's a couple of stages of > pipeline delay, it's not a problem. > > thanks much for the advice. > > -- > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "Money is property; it is not speech." > -- Justice John Paul Stevens Rather than add registers to resynch, why not redo the FIFO to run at 80 MHz? I have not done one at that speed, but if you are not crossing clock domains with your FIFO, the design is very straightforward. I do them myself all the time. It is likely that the CORE FIFO has some features that slow it down a bit. If you don't need those features, you can probably get it to run at 80 MHz no sweat. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 20934
Dear Tester & Measurer, We own and use a Philips Logicanalyzer PM3585. Unfortunately Philips sold their Test&Measurement Division completely to Fluke, and Fluke dropped support of the Logicanalyzers immediately after their purchase. Today (Feb. 2000) there is no support neither from Philips nor from Fluke. I asked them both, but they told that they have physically shreddered all parts for this product?! What we are searching for is disassembler software for the Intel 80x86 line of processors. What we have is disassembler software for 8051 microcontrollers. Maybe someone has the ones we are searching for and wants the ones we have. Maybe someone has the ones we are searching for and dont want ours. Anyway: We need disassembler software for 80x86, 80286, 80386 and/or 80486 processors, so if you have or know who has, PLEASE mail to marquardt@alc.de Best regards Juergen MarquardtArticle: 20935
hello ive never programmed a fpga before, just read a few articles and looked at some basic vhdl code. at the moment i make delay lines using caps and inductors mainly for pulse applications, somtimes inconjunction with not gates to buffer the line. i was wondering if a delay line could be made easily in an fpga and if so are there any limitations ie. max delay, max frequency. any help or relevant links would be great thanks henryArticle: 20936
Hi thanks for the responses I am just starting out in the fpga aria and this kit looks like a excelent way to get some hands on experiance. I have already bought and 1/2 read two books on the subject and was just curious of others experiances with this kit even though it would not likely have changed my mind to try it at $150 US. I dont leave a correct email address on newsgroups as i think that is where some of my junk-mail originates. I did however forget to include my name. Its Martin.Article: 20937
Greg Deych wrote: > > Does anybody know of a resource (web, book or article) describing > architecture design for systems, storage or logic, whose components > are prone to very high rate of failure, along the line of 0.1%-1%? This is 'sort of' simple and obvious: You start with the component failure rate and the target failure rate. Then you decide if you need error correction or if error detection and retry is feasible. If every single component, including the error checking/voting hardware has the same, extremely high, error rate, then it becomes _very_ hard. What about the failures themselves? Are they silent, soft, hard? Will a faulty component stop working alltogether, or will it just produce wrong answers? Terje PS. It helps a _lot_ if you can assume that some components, are much better than the worst parts. :-) -- - <Terje.Mathisen@hda.hydro.com> Using self-discipline, see http://www.eiffel.com/discipline "almost all programming can be viewed as an exercise in caching"Article: 20938
No you're not paranoid, you can't be sure that cpua_data(7) is properly
latched. Transparent latches always need the redundant cover term when
implemented as combinatorial logic (i.e. without benefit of some predefined
latch in the hardware architecture). I've seen this failure with several
programmable devices.
When I used Warp I couldn't find a way to have it keep the necessary
redundant terms so unless the part you are targetting can guarantee that a
latch will be implemeted properly I wouldn't suggest trying it. If it does,
you might want to change the logic somewhat like...
latch_enable <= not(cpua_wr_not) or not(cpub_wr_not); -- Or together the
writes to create a latch enable
Make your process sensitive to latch_enable instead of cpua_wr_not and
cpub_wr_not and then use one of the write signals to select the data.
process (reset, latch_enable, cpua_data, cpub_data)
begin
if reset = '1' then
outport <= "00000000";
elsif latch_enable = '1' then
if (cpua_wr_not = '0') then
outport <= cpua_data;
else
outport <= cpub_data;
end if;
end if;
If you're lucky, the final equations will have some sort of .D equations and
some .LE equation for outport if the target part inherently supports
transparent latches. If it still gives only the single combinatorial
equation you might try just a simple latch
process (D, LE)
if (LE = '1') then
Q <= D;
end if;
If that still gives a single combinatorial equation then either...
- Pick another part that knows about latches.
- Rethink the real reason for your async requirement.
- Talk to the Cypress rep about how to keep redundant terms. Like I said
when I played with it, the VHDL signal attributes that they defined didn't
include any sort of "don't touch this
You will end up getting screwed if you go with something like what Warp is
giving you now (i.e. no inherent latch, no redundant cover term). If you're
lucky you'll find it when you build your first boards, if you're not you'll
find it in a year or so.
Karl Olsen <kro@post3.tele.dk> wrote in message
news:89etuo$fsi$1@news.inet.tele.dk...
> Hi all,
>
> I need to implement an 8-bit register that can be written asynchronously
> from two CPUs, in a Cypress CPLD.
>
> Will the following always work?
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity async is
> port (
> reset : in std_logic;
> cpua_wr_not : in std_logic;
> cpua_data : in std_logic_vector (7 downto 0);
> cpub_wr_not : in std_logic;
> cpub_data : in std_logic_vector (7 downto 0);
> outport : out std_logic_vector (7 downto 0)
> );
> end async;
>
> architecture async_arch of async is
>
> begin
>
> process (reset, cpua_wr_not, cpua_data, cpub_wr_not, cpub_data)
> begin
> if reset = '1' then
> outport <= "00000000";
> elsif cpua_wr_not = '0' then
> outport <= cpua_data;
> elsif cpub_wr_not = '0' then
> outport <= cpub_data;
> end if;
> end process;
>
> end async_arch;
>
>
> The Warp compiler turns it into equations like this:
>
> outport(7) =
> /reset * cpua_wr_not * cpub_wr_not * outport(7).CMB
> + /reset * cpua_wr_not * /cpub_wr_not * cpub_data(7)
> + /reset * /cpua_wr_not * cpua_data(7)
>
> Ignoring the situation when the two CPUs are writing near-simultaneously,
> will this kind of flipflop always work?
>
> At the end of CPU A's write cycle where cpua_wr_not goes high and
"control"
> switches from the third to the first of the three prouct terms, can I be
> sure that cpua_data(7) is actually latched in outport(7), and not some
> glitch because of product term "speed" mismatch?
>
> Or am I just paranoid?
>
> Regards,
> Karl Olsen
>
>
Article: 20939Systolix have just released an updated version of their free windows based digital filter synthesis tool FilterExpress. It is now available for download from Systolix home site at http://www.systolix.co.uk/swdownload.htm. FilterExpress supports the design and analysis of IIR, FIR and multirate FIR filters. Version 3.0 now supports the following: - Equiripple Filter Design - Gaussian Filters - Raised (Root) Cosine Filters - Hilbert Transforms - Halfband Filters - Coefficient Quantisation The free version of FilterExpress is fully functional and saves coefficient vaules to a simple text file suitable for export to other tools.Article: 20940
On Tue, 29 Feb 2000 14:45:28 +0100, Terje Mathisen <Terje.Mathisen@hda.hydro.com> wrote: > >If every single component, including the error checking/voting hardware >has the same, extremely high, error rate, then it becomes _very_ hard. That could be the case, but I think I'll start off with hardware which has more or less regular failure rates. > >What about the failures themselves? > >Are they silent, soft, hard? > >Will a faulty component stop working alltogether, or will it just >produce wrong answers? Actually, it's easier if the component just fails alltogether. That way, you can ignore it, rather then accounting for unpredictable values it may output.Article: 20941
I am in need of a good book covering VHDL techniques for synthesis in PLD's, especially FPGA's. A more general book covering VHDL for synthesis (not PLD's specifically) would be just as good. If anyone has any suggestions I would greatly appreciate it. Thanks in advance. John M. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20942
You can of course use an FPGA ( or CPLD) as a string of non-inverting buffers, resembling a delay line, and you could easily adjust the number of stages, but you would be very disappointed in the stability ( or lack thereof ) over supply voltage, temperature and process variations. Easily a 50% tolerance. Delays in ICs track very well, but their absolute stability is nothing to brag about. Much worse than your Ls and Cs. Peter Alfke, Xilinx Applications henry wrote: > hello > > ive never programmed a fpga before, just read a few articles and looked at > some basic > vhdl code. at the moment i make delay lines using caps and inductors mainly > for pulse > applications, somtimes inconjunction with not gates to buffer the line. > > i was wondering if a delay line could be made easily in an fpga and if so > are there any > limitations ie. max delay, max frequency. > > any help or relevant links would be great > > thanks > > henryArticle: 20943
test wrote:
> Xilinx foundation 1.5
> XABEL 6.3
> The following example was modified from the Xilinx help file. What I
> basically want to know is if, for each state, should the outputs change
> prior to the execution of the goto statements. What happens when I try
> to simulate the following code, is that the outputs stay stuck high.
> But this changes based on the way my states are set up. For example, if
> I were to change State three to:
>
> State s3: outputs = [0,0,1];
> goto s3;
>
> and basically have an infinite loop unto itself, then I see the outputs
> go from [1,1,1] to [0,0,1] . I never see the first two states execute.
> What I want to see is the states change automatically with every clock
> cycle. Any ideas about what I'm doing wrong?
>
Yes. A symbolic FSM in Abel is defined to be a one-hot. And in this case,
what you're FSM is doing is initializing to the all 0's state. Which, of
course, is not a defined state for a one-hot. I modified your design by
adding an ASYNC_RESET specification. Now it seems to work much better:
module onehot
Title 'onehot'
Declarations
a PIN ;
b PIN ;
c PIN ;
clk PIN;
outputs2..outputs0 PIN ;
outputs = [outputs2..outputs0];
sbit STATE_REGISTER istype 'reg';
s1, s2, s3 STATE;
Equations
sbit.clk = clk;
//sbit.ap=0;
State_Diagram sbit
ASYNC_RESET s1: a;
State s1: outputs = [1,0,0];
goto s2;
State s2: outputs = [0,1,0];
goto s3;
State s3: outputs = [0,0,1];
goto s1;
test_vectors ([clk,a,b,c] -> [outputs])
[0, 0,0,0] -> [.x.];
[0, 1,0,0] -> [.x.];
[.c.,0,0,0] -> [.x.];
[.c.,0,0,0] -> [.x.];
[.c.,0,0,0] -> [.x.];
[.c.,0,0,0] -> [.x.];
[.c.,0,0,0] -> [.x.];
end onehot;
I have specified that the "a" input will be used to initialize the FSM
flip-flops to state s1, asynchronously. If you prefer synchronous operation,
use SYNC_RESET instead.
BTW, one-hot is not usually a good FSM encoding for CPLDs. Unfortunatly,
Abel currently doesn't offer any alternative for symbolic FSMs. At some
point I'm gonna try and dig in and change that...
-Dennis McCrohan (speaking for myself, not Xilinx)
Article: 20944
henry wrote:
>
> hello
>
> i've never programmed a fpga before, just read a few articles and looked at
> some basic
> vhdl code. at the moment i make delay lines using caps and inductors mainly
> for pulse
> applications, somtimes inconjunction with not gates to buffer the line.
>
> i was wondering if a delay line could be made easily in an fpga and if so
> are there any
> limitations ie. max delay, max frequency.
>
If your pulse is serveral clock cycles wide you can do it
with a shift register or counter. An FPGA with a PLL clock
might be a good choice.
Limitations: pulse width distortion
Max delay = #of flops x clock period (for shift register)
If your pulse is narrower, keep your caps and inductors.
There's no clean way to do it on an FPGA.
-Mike Treseler
Article: 20945Tom Burgess wrote: > JRei7227 wrote: <snipped> > > > > Equations > > > > c = a & b; > > d = a # b; > > sreg1.clk = clk; > > You need a clock for your other regs: > > [c,d,e,f].clk = clk; > > regards, > Tom Burgess > -- > Digital Engineer > Dominion Radio Astrophysical Observatory > P.O. Box 248, Penticton, B.C. > Canada V2A 6K3 Correct. A couple of other points: 1. There was a time that this coding style would have worked - the Abel compiler supports a "compatibility implied" switch, which back in the old days (when a P22V10 was state of the art) would cause the compiler to figure out what macrocells were clocked based upon your device selection/pin-out. 2. You are specifying a symbolic FSM. Symbolic FSMs in Abel are always encoded one-hot. This is usually not optimal for PLDs. 3. Since you are specifying a symbolic FSM with the state_register, you also should really specify either SYNC_RESET or ASYNC_RESET. Otherwise, the initial state of your FSM will be unknown, and your test vectors will fail in the simulator and on a tester, and the behavior in the real world will be indeterminate. Actually, probably worse than indeterminate, since a lot of silicon these days has a pre-disposition to power-up to all 0's state, which would be a undefined or "hung" state for a one-hot. -Dennis McCrohan (speaking for myself, not Xilinx)Article: 20946
Yes. JTAG Programmer runs on Windows 2000 even though the release notes
do not say anything about it. Installing the WebPack2.1iwp5.x JTAG
Programmer (not Foundation) on Windows 2000, the following parts were
successfully programmed:
XC9536XL
XCV50
through the following cables:
Parallel Cable III
MultiLINX-Serial
If you are getting a software error, I suggest you open a web support
case with the hotline at: http://support.xilinx.com
Sincerely,
Robert Binkley
Xilinx Applications
Andrew McCartney wrote:
> Has anyone used the Xilinx JTAG Programmer SW and the Parallel Cable
> III with Windows 2000? I have installed and used the Fndtn 2.1i tools
> under 2000, but I cannot get the JTAG Programmer to work properly.
Article: 20947In article <5gqnbsg2kt0qjudf8bqgeh30a108jcjtdg@4ax.com>, gdeych@my-deja.com wrote: > On Tue, 29 Feb 2000 14:45:28 +0100, Terje Mathisen > <Terje.Mathisen@hda.hydro.com> wrote: > > > >If every single component, including the error checking/voting hardware > >has the same, extremely high, error rate, then it becomes _very_ hard. > > That could be the case, but I think I'll start off with hardware which > has more or less regular failure rates. > (snip) OK then, you might want to check out: "Fault Tolerant System Design" Shem-Tov Levi and Ashok K. Agrawala McGraw-Hill ISBN 0-07-037515-1 -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20948
Hi, I would recommend Peter Ashden: The designers guide to VHDL if you really want to learn VHDL, it has great examples, and explains VHDL in detail. If you want just a quick reference Jayaram Bhasker : A VHDL primer is a good choice, but just as reference. Hope this helps. Domagoj <stang99@my-deja.com> wrote in message news:89gro4$vbo$1@nnrp1.deja.com... > I am in need of a good book covering VHDL techniques for synthesis in > PLD's, especially FPGA's. A more general book covering VHDL for > synthesis (not PLD's specifically) would be just as good. If anyone has > any suggestions I would greatly appreciate it. Thanks in advance. > > John M. > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 20949
Has anybody used this full grid package for Virtex(-E) parts ? Matt Billenstein kindly sent me a picture of a suggested escape he got from a Xilinx FAE. Unfortunately on one of the inner layers it shows 2 traces coming out between vias. For the design rules quoted this gives 0.61mm (land) + 5 * 0.11mm (trace & gap) = 1.16mm! Is there a better way of doing this without using blind vias ? I suspect the trick is to remove or shrink the via pads on inner layers where there's no connection.
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