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TechOnline through its subnet DSPnet will be introducing in a couple of weeks the capability to compile, link download to a remote workstation and benchmark your code on 2 remote workstations hosting EVM's (hardware evaluation modules) based on Texas Instrument's TMS320C3X floating point processors. TechOnline through DSPnet introduced last week at DSPx this capability on a workstation developed for Arrow-Schweber, a distributor for Texas Instruments. Presently the workstations hosted on dsplab and reachable through the Texas Instruments page on DSPnet and through the TI corporate web site allow you to compile your code but not to download it into the actual hardware. The new capability will allow an engineer to benchmark and debug his/her code before making a decision as to which processors to use. An announcement is expected in a couple of weeks when the code download capability will become available to the general public. In the meantime TechOnline is revamping its site and will be adding capabilities to the present ones. URL http://www.techonline.com or http://www.dspnet.comArticle: 3051
I'm tyring to drop in a EEPROM for one of these chips and I can't find out what bus this part uses. First, am I SOL to start with or is this possible? I can speak IIC, uWire, and from there, SPI, et al are easy. (it's a serial protocol, how hard can it be?) I don't have any Xilinx documentation, so can anyone give me a hand? Cheers, DavidArticle: 3052
David A Willmore wrote: > > I'm tyring to drop in a EEPROM for one of these chips and I > can't find out what bus this part uses. First, am I SOL to > start with or is this possible? I can speak IIC, uWire, and > from there, SPI, et al are easy. (it's a serial protocol, > how hard can it be?) > > I don't have any Xilinx documentation, so can anyone give me > a hand? Its a new serial interface. But how hard can it be? It runs from 2.5MHz to 10MHz, which explains why none of the interface protocols you mentioned will work. Good luck trying to get a serial EEPROM to read that fast. Atmel makes EEPROM versions of this part, if you want to pay $8 for it. And the smallest array they have is a 64K. If you want a cheaper option and can modify the read speed we make a standard XI2C (2 address bytes) 64K serial that will read at 1MHz, called the 24FC65. We also make a 32K version. Xilinx's home page at http://www.xilinx.com has data sheets, conveniently located under fpga product literature. David WilkieArticle: 3053
Dear Colleague,
Just a reminder that the hotel room reservation deadline for the
1996 ACM/SIGDA Physical Design Workshop is only three days from now
(March 24). Room availability can not be guaranteed past this date.
PDW'96 is co-sponsored the U.S. National Science Foundation (see
the advance program below). This year's program will emphasize
deep-submicron and high-performance issues, and will also feature a
special track on micro electromechanical systems (MEMS), chaired by
Ken Gabriel of ARPA.
For more information, please see our WWW home page at:
http://www.cs.virginia.edu/~pdw96/
Thanks,
Gabe
======================================================
Name: Prof. Gabriel Robins
General Chair, PDW'96
U.S. Mail: Department of Computer Science
Thornton Hall
University of Virginia
Charlottesville, VA 22903-2442
Phone: (804) 982-2207
FAX: (804) 982-2214
E-mail: robins@cs.virginia.edu
WWW: http://www.cs.virginia.edu/~robins/
======================================================
=============================================================================
ADVANCE PROGRAM
Fifth ACM/SIGDA Physical Design Workshop
April 15-17, 1996 - The Sheraton Reston Hotel, Reston, Virginia USA
http://www.cs.virginia.edu/~pdw96/
The ACM/SIGDA Physical Design Workshop (PDW'96) provides a relaxed
atmosphere for exchange of ideas and promotes research in critical
subareas of physical design for VLSI systems.
This year's workshop emphasizes deep-submicron and high-performance
issues, and also provides a special focus on opportunities in CAD for
micro electromechanical systems (MEMS). There are four outstanding
panel sessions:
(1) future needs and directions for deep-submicron physical design,
(2) physical design needs for MEMS,
(3) manufacturing and yield issues in physical design, and
(4) critical disconnects in design views, data modeling, and back-end
flows (e.g., for physical verification).
There are also many outstanding technical paper sessions.
Free-flowing discussion will be promoted through the limited workshop
attendance, the poster session and the "open commentary" mechanism in
each technical session, as well as a concluding open problems session.
During the workshop, a benchmarks competition will occur in the areas
of netlist partitioning and performance-driven cell placement.
=============================================================================
SUNDAY, APRIL 14
=============================================================================
6:00pm-8:30pm: Registration
(the registration desk will also be open 8:00am-5:00pm on Monday
and 8:00am-12:00pm on Tuesday)
7:00pm-8:30pm: Reception (refreshments provided)
=============================================================================
MONDAY, APRIL 15
=============================================================================
8:30am-8:40am: Welcome
8:40am-10:00am: Session 1, Timing-Driven Interconnect Resynthesis
Interconnect Layout Optimization by Simultaneous Steiner Tree
Construction and Buffer Insertion, T. Okamoto and J. Cong (UC Los Angeles)
Simultaneous Routing and Buffer Insertion for High Performance
Interconnect, J. Lillis, C.-K. Cheng and T.-T. Lin (UC San Diego)
Timing Optimization by Redundancy Addition/Removal, L. Entrena, E. Olias
and J. Uceda (U. Carlos III of Madrid and U. Politecnica of Madrid)
Open Commentary - Moderators: D. Hill (Synopsys),
P. Suaris (Interconnectix)
10:00am-10:20am: Break
10:20am-12:00pm: Session 2, Interconnect Optimization
Optimal Wire-Sizing Formula Under Elmore Delay Model,
C. P. Chen, Y. P. Chen and D. F. Wong (U. Texas Austin)
Reducing Coupled Noise During Routing, A. Vittal and M. Marek-Sadowska
(UC Santa Barbara)
Simultaneous Transistor and Interconnect Sizing Using General
Dominance Property, J. Cong and L. He (UC Los Angeles)
Hierarchical Clock-Network Optimization, D. Lehther, S. Pullela,
D. Blaauw and S. Ganguly (Somerset Design Center and Motorola)
Open Commentary - Moderators: D. Hill (Synopsys),
M. Lorenzetti (Mentor)
12:00pm-2:00pm: Lunch
Workshop Keynote Address: Prof. C. L. Liu, U. of Illinois
Algorithmic Aspects of Physical Design of VLSI Circuits
2:00pm-2:45pm: Session 3, A Tutorial Overview of MEMS
Speaker: K. Gabriel (ARPA)
2:45pm-3:00pm: Break
3:00pm-4:15pm: Session 4, Physical Design for MEMS
Physical Design for Surface Micromachined MEMS, Gary K. Fedder and
Tamal Mukherjee (Carnegie-Mellon U.)
Physical Design Support for MCNC/MUMPS, R. Mahadevan (MCNC)
Synthesis and Extraction for MEMS Design, E. Berg, N. Lo and
K. Pister (UC Los Angeles)
4:15pm-4:30pm: Break
4:30pm-6:00pm: Session 5, Panel: Physical Design Needs for MEMS
Moderator: K. Pister (UC Los Angeles)
Panelists include:
S. Bart (Analog Devices)
G. Fedder (Carnegie-Mellon U.)
K. Gabriel (ARPA)
I. Getreu (Analogy)
R. Grafton (NSF)
R. Mahadevan (MCNC)
J. Tanner (Tanner Research)
6:00pm-8:00pm: Dinner
8:00pm-9:30pm: Session 6, Panel: Deep-Submicron Physical Design:
Future Needs and Directions
Panelists include:
T. C. Lee (former VP Eng, SVR; President/CEO, Neo Paradigm Labs)
L. Scheffer (Architect, Cadence)
W. Vercruysse (UltraSPARC III CAD Manager, Sun)
M. Wiesel (Design Manager, Intel)
T. Yin (VP R&D, Avant!)
=============================================================================
TUESDAY, APRIL 16
=============================================================================
8:30am-9:50am: Session 7, Partitioning
VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement
Techniques, S. Dutt and W. Y. Deng (U. Minnesota and LSI Logic)
A Hybrid Multilevel/Genetic Approach for Circuit Partitioning,
C. J. Alpert, L. Hagen and A. B. Kahng (UC Los Angeles and Cadence)
Min-Cut Replication for Delay Reduction, J. Hwang and A. El Gamal
(Xilinx and Stanford U.)
Open Commentary - Moderators: J. Frankle (Xilinx),
L. Scheffer (Cadence)
9:30am-10:10am: Break
10:10am-11:50am: Session 8, Topics in Hierarchical Design
Two-Dimensional Datapath Regularity Extraction, R. Nijssen and
J. Jess (TU Eindhoven)
Hierarchical Net Length Estimation, G. Zimmermann (U. Kaiserslautern)
Exploring the Design Space for Building-Block Placements Considering
Area, Aspect Ratio, Path Delay and Routing Congestion, H. Esbensen and
E. S. Kuh (UC Berkeley)
Genetic Simulated Annealing and Application to Non-Slicing Floorplan
Design, S. Koakutsu, M. Kang and W. W.-M. Dai (Chiba U. and UC Santa Cruz)
Open Commentary
11:50pm-1:30pm: Lunch
1:30pm-3:00pm: Session 9, Poster Session
Physical Layout for Three-Dimensional FPGAs, M. J. Alexander, J. P.
Cohoon, J. Colflesh, J. Karro, E. L. Peters and G. Robins (U. of Virginia)
Efficient Area Minimization for Dynamic CMOS Circuits, B. Basaran
and R. Rutenbar (Carnegie-Mellon U.)
A Fast Technique for Timing-Driven Placement Re-engineering,
M. Hossain, B. Thumma and S. Ashtaputre (Compass Design Automation)
Computer Aided Micro-Machining for Wet Etch Fabrication,
M. K. Long, J. W. Burdick and T. J. Hubbard (Caltech)
Over-the-Cell Routing with Vertical Floating Pins, I. Peters, P. Molitor
and M. Weber (U. Halle and Deuretzbacher Research GmbH)
Congestion- Balanced Placement for FPGAs, R. Sun, R. Gupta and C. L. Liu
(Altera and U. Illinois)
Fanout Problems in FPGA, K.-H. Tsai, M. Marek-Sadowska and S. Kaptanoglu
(UC Santa Barbara and Actel)
An Optimal Pairing and Chaining Algorithm for Layout Generation,
J. Velasco, X. Marin, R. P. Llopis and J. Carrabina (IMB-CNM
U. Autonoma de Barcelona, Philips Research Labs Eindhoven)
Clock-Delayed Domino in Adder and Random Logic Design, G. Yee and
C. Sechen (U. Washington)
3:00pm-4:00pm: Session 10, Manufacturing/Yield Issues I
Layout Design for Yield and Reliability, K. P. Wang, M. Marek-Sadowska
and W. Maly (UC Santa Barbara and Carnegie-Mellon U.)
Yield Optimization in Physical Design, V. Chiluvuri (Motorola)
(invited survey paper)
4:00pm-4:15pm: Break
4:15pm-5:45pm: Session 11, Panel: Manufacturing/Yield Issues II
Panelists include:
V. Chiluvuri (Motorola)
I. Koren (U. Massachusetts Amherst)
J. Burns (IBM Watson Research Center)
W. Maly (Carnegie-Mellon U.)
5:45pm-7:30pm: Dinner
7:30pm-9:30pm: Session 12, Panel: Design Views, Data Modeling and
Flows: Critical Disconnects
A Talk by C. Sechen (U. Washington)
A Gridless Multi-Layer Channel Router Based on Combined Constraint Graph
and Tile Expansion Approach, H.-P. Tseng and C. Sechen (U. Washington)
A Multi-Layer Chip-Level Global Route, L.-C. E. Liu and C. Sechen
(U. Washington)
Panelists include:
W. W.-M. Dai (UC Santa Cruz, VP Ultima Interconnect Technologies)
L. Jones (Motorola)
D. Lapotin (IBM Austin Research Center)
E. Nequist (VP R&D, Cooper & Chyan)
R. Rohrer (Chief Scientist, Avant!)
P. Sandborn (VP, Savantage)
=============================================================================
WEDNESDAY, APRIL 17
=============================================================================
8:30am-9:50am: Session 13, Performance-Driven Design
A Graph-Based Delay Budgeting Algorithm for Large Scale Timing-Driven
Placement Problems, G. Tellez, D. A. Knol and M. Sarrafzadeh
(Northwestern U.)
Reduced Sensitivity of Clock Skew Scheduling to Technology Variations,
J. L. Neves and E. G. Friedman (U. Rochester)
Multi-Layer Pin Assignment for Macro Cell Circuits, L.-C. E. Liu and
C. Sechen (U. Washington)
Open Commentary
9:50pm-10:10pm: Break
10:10am-11:30am: Session 14, Topics in Layout
Constraint Relaxation in Graph-Based Compaction, S. K. Dong, P. Pan,
C. Y. Lo and C. L. Liu (Silicon Graphics, Clarkson U., Lucent, U. Illinois)
An O(n) Algorithm for Transistor Stacking with Performance Constraints,
B. Basaran and R. Rutenbar (Carnegie-Mellon U.)
Efficient Standard Cell Generation When Diffusion Strapping is Required,
B. Guan and C. Sechen (Silicon Graphics and U. Washington)
Open Commentary - Moderator: A. Domic (Cadence)
11:30am-12:00pm: Session 15, Open Problems
Moderators: A. B. Kahng (UC Los Angeles), B. Preas (Xerox PARC)
12:00pm-2:00pm: Lunch (and benchmark competition results)
2:00pm: Workshop adjourns
=============================================================================
TRAVEL AND ACCOMODATIONS
=============================================================================
PDW '96 is being held at the Sheraton Reston in Reston, Virginia, near
Washington, D.C. The hotel is minutes from Dulles International
Airport (IAD), and 24-hour courtesy shuttles are available from the
airport to the hotel. The area is also served by Washington National
Airport (DCA), about 20 miles away, and Baltimore-Washington
International Airport (BWI), about 50 miles away.
The Sheraton Reston is located at:
11810 Sunrise Valley Drive
Reston, Virginia 22091
phone: 703-620-9000
fax: 703-860-1594
reservations: 800-392-ROOM
*** Please make your room reservation directly with the Reston ***
*** Sheraton hotel. ***
Driving directions from Dulles Airport: take the Washington Dulles
Access and Toll Road (route 267) to the Reston Parkway Exit (3). Turn
right at the light after paying toll. Take the next left onto Sunrise
Valley Drive, and continue for a couple blocks to the Sheraton (on
your left).
A block of rooms is being held for the nights of Sunday through
Wednesday (April 14 through April 17). Room rates are $95 per night
for single occupancy, and $105 per night for double occupancy. The
number of rooms available at these rates is limited, and they are only
being held through March 24 (so early registration is highly recommended).
The Washington D.C. weather tends to be chilly in April, so warm dress
is suggested for the outdoors.
=============================================================================
SIGHTSEEING AND ATTRACTIONS
=============================================================================
The Nation's Capitol offers much in the way of sightseeing. The most
popular destinations are located in downtown Washington D.C.,
surrounding several square miles of park area known as the "National
Mall." There is no charge to visit the National Memorials located on
the Mall, which include the Washington Monument, where you may ascend
555 feet to an observation post; the Lincoln Memorial, whose design
adorns the back of the US penny; the Jefferson Memorial, which
includes a 19-foot bronze statue of Thomas Jefferson; and the Vietnam
Memorial, a long wall of black Indian granite dedicated in 1982.
The Smithsonian Institution (telephone (202) 357-2700) operates a
number of superb museums that flank the National Mall, including:
Freer Gallery of Art (Asian and 19th and 20th-century American art)
Hirshhorn Museum and Sculpture Garden (modern and contemporary art)
National Air and Space Museum (history of aviation and space exploration)
National Museum of African Art (collection and study of African art)
National Museum of American Art (paintings, graphics, and photography)
National Museum of American History (technology and culture in America)
National Museum of Natural History (history of the natural world)
National Portrait Gallery (portraits of distinguished Americans)
National Postal Museum (history of postal communication and philately)
Sackler Gallery of Asian art (from ancient to present)
Other attractions and tours around the D.C. area include (please call
the numbers below for schedules):
Arlington National Cemetary (703) 697-2131
Bureau of Engraving and Printing (202) 622-2000
Congressional buildings (202) 225-6827
FBI Headquarters (202) 324-3447
Library of Congress (202) 707-5000
National Aquarium (202) 482-2825
National Archives (202) 501-5000
National Zoological Park (202) 673-4821
The Pentagon (703) 695-1776
Supreme Court (202) 479-3030
Treasury Department (202) 622-2000
The White House (202) 456-7041
There are a number of reasonably priced eating places on the Mall; the
East Wing of National Gallery and the Air and Space Museums offer good
food and a place to sit down after sightseeing. Provisions will be
made for low-cost transportation to and from the Mall and downtown
Washington D.C., so bring your camera and strolling shoes and enjoy
our Nation's Capital!
=============================================================================
WORKSHOP ORGANIZATION
=============================================================================
General Chair:
G. Robins (U. of Virginia)
Technical Program Committee:
C. K. Cheng (UC San Diego)
J. P. Cohoon (U. of Virginia)
J. Cong (UC Los Angeles)
A. Domic (Cadence)
J. Frankle (Xilinx)
E. Friedman (Rochester)
D. Hill (Synopsys)
L. Jones (Motorola)
A. B. Kahng (UC Los Angeles, Chair)
Y.-L. Lin (Tsing Hua)
K. Pister (UC Los Angeles)
M. Marek-Sadowska (UC Santa Barbara)
C. Sechen (Washington)
R.-S. Tsay (Avant!)
G. Zimmermann (Kaiserslautern)
Steering Committee:
M. Lorenzetti (Mentor Graphics)
B. Preas (Xerox PARC)
Keynote Address:
C. L. Liu (Illinois)
Benchmarks Co-Chairs:
F. Brglez (NCSU)
W. Swartz (TimberWolf Systems)
Local Arrangements Chair:
M. J. Alexander (U. of Virginia)
Treasurer:
S. B. Souvannavong (HIMA)
Publicity Chair:
J. L. Ganley (Cadence)
Sponsors:
ACM / SIGDA
U.S. National Science Foundation
Avant! Corporation
=============================================================================
WORKSHOP REGISTRATION
=============================================================================
Fifth ACM/SIGDA Physical Design Workshop
April 15-17, 1996 - The Sheraton Reston Hotel, Reston, Virginia USA
Name: _______________________________________________________________
Company/University: _________________________________________________
Title: ______________________________________________________________
Address: ____________________________________________________________
City: _________________________________________ State: ______________
Phone: ____________________________ Email: __________________________
Registration Fees (Includes All Meals)
Advance (Through April 1) Late (After April 1/On-Site)
ACM Members __ $355 __ $440
Non-ACM __ $455 __ $540
Students __ $250 __ $250
ACM Membership Number: _____________________________
Dietary restrictions, if any: ______________________
Special needs: _____________________________________
The registration fee includes the workshop proceedings and all meals
(i.e., 3 breakfasts, 3 lunches, and 2 dinners), refreshments during
breaks, and a reception on Sunday evening. The total number of
attendees is limited (registrations will be returned if the workshop
is oversubscribed).
*** Note: Hotel reservations must be made directly with the Sheraton ***
*** (please call: 703-620-9000 to make a room reservation) ***
The only acceptable forms of payment are checks (personal, company,
and certified/bank checks) in US funds drawn on a US bank and made
payable to "1996 Physical Design Workshop" (credit cards will not be
accepted). Payment must accompany your registration. No FAX or Email
registrations will be processed.
Please mail your payment (checks only) along with this registration form to:
Sally Souvannavong, Treasurer
1996 ACM/SIGDA Physical Design Workshop
Department of Computer Science
Thornton Hall
University of Virginia
Charlottesville, VA 22903-2442 USA
Phone: (804) 982-2200
Email: pdw96@cs.virginia.edu
Cancellations must be in writing and must be received by March 31, 1996.
=============================================================================
The Latex and postscript versions of this advanced program may be
obtained from http://www.cs.virginia.edu/~pdw96/
=============================================================================
Article: 3054David A Willmore wrote: > > I'm tyring to drop in a EEPROM for one of these chips and I > can't find out what bus this part uses. First, am I SOL to > start with or is this possible? I can speak IIC, uWire, and > from there, SPI, et al are easy. (it's a serial protocol, > how hard can it be?) > > I don't have any Xilinx documentation, so can anyone give me > a hand? > > Cheers, > David The Xilinx PROMs use a proprietary serial protocol. Atmel makes compatible serial EEPROMs. The devices you want are the AT17C65/128/256. The smallest part, AT17C65, is more than large enough to replace the 1736. Data sheets are available at: http://www.atmel.com/atmel/products/products3.html Regards, ScottArticle: 3055
Don Husby <husby@fnal.gov> said:
>On the other hand, if you spend a couple of hours to analyze the
>algorithm and code it in a form that works well with FPGAs,
>you get a circuit (for the 16/8 case) that fits into 12 PFUs
>(about 48 Altera LCs) in an ORCA chip and can run at 20ns cycle
>times.
I took his C version of the sqrt code, and ran it through tmcc. Tmcc
didn't do as well as that, but it is faster by a factor of 6 or so (for
large inputs) over the results of a few days ago. He then pointed out:
>And if you're willing to risk looking like a complete geek, you
>might observe that you could completely unroll the loop and come up
>with a circuit that uses 24 ORCA PFUs and computes the full 16/8-bit
>square root in 87 ns.
>
>(This circuit relies heavily on the ORCA FE-MUX and would translate
>to about 140 Altera LCs or 70 Xilinx-4000 CLBs)
I tried that, and the new circuit is about 80% faster again. Tmcc produces
a fairly deep circuit in this case, but it does run in one cycle. Here
are all the results for the Altera 10K, for 16 bit inputs and 8 bit outputs.
Note that all the sizes include the fixed overhead of the main() routine:
Circuit LCs FFs cycle time (ns) Cycles/input bit
original via Schmit 626 135 172 1
my modification 610 154 96 2
Husby 136 77 60 .5
unrolled Husby 167 39 268 .0625
Don Husby again:
>What does this demonstrate? Many people have suggested that a goal
>is to compile "dusty-deck" code into FPGAs and capitalize on the
>zillions of lines of C that already exist. I think that it's very
>unlikely that this is a useful goal. I think most people will be
>willing to do substantial work to make their algorithms run
>much-much faster.
> Eperiments on theoretical physicists have shown them willing to
>learn new programming languages (C instead of FORTRAN) and re-code
>their algorithms if the speed up is significant.
Yes, it is possible to speed up algorithms so that they execute faster on
FPGAs, and we need good support for that. However, if we can do it
without having to force people into learning a new language, we'll have
an advantage. As a guess, they could get most of the speedup by modifying
only the interesting 20% of a dusty-deck. If they can avoid having to
re-write the other 80%, it will save them a lot of work, and make FPGA based
computing more attractive.
Here is the Transmogrifier C (tmcc) version of Don Husby's sqrt routine:
#pragma intbits 8
int
sqroot(N)
#pragma intbits 16
int N;
{
#pragma intbits 4
int Bit=8;
#pragma intbits 24
int N_reg= N;
int R_reg=0;
int Tmp;
#pragma intbits 8
int Rt=0;
while (Bit--)
{ R_reg = (Rt<<16)|0x4000;
Tmp= (N_reg-R_reg);
if (Tmp >= 0)
{ N_reg= Tmp << 2;
Rt= (Rt << 1)|1; }
else
{ N_reg= N_reg<<2;
Rt= (Rt << 1) ; }
}
return (Rt);
}
main() {
int i,t;
outputport(t);
while(1) {
i = 4;
while(i<50) {
t = sqroot(i);
i++;
}
t = sqroot(0xffffffff);
}
}
Tmcc web page: http://www.eecg.toronto.edu/EECG/RESEARCH/tmcc/tmcc
Article: 3056I have implemented delta sigma D/A which involves feeding back an adder's output to its input and filtering the the MSB output to generate an analog value proportional to the the input. How would one go about the inverse if that is even the right way to put it? Block diagrams of sigma-delta A/Ds contain D/As and blocks called decimation filters. I am still confused as to what the analog values could possibly mean to to a digital input pin I am guessing the signal are differentiated and perhaps mixed with an oversampling frequency then you get some kind of freq or pwm bit stream. I know, I am rambling. I am posting here because I want put this in a Lattice 1016 which are very easy to use by the way.Article: 3057
I am currently using Synopsys / Xilinx and targeting a 4005 part. I would like to perform post-route timing simulation of the device. Unfortunately, we have not purchased VSS (Synopsys Simulator). I would like to know if anybody out there has used either Model-Technology or Mentor's Quick-VHDL to do post route timing SIMs w/Xilinx. I have gotten this to work from the Altera Tools, but have not figgured it out for Xilinx Thanks: Dean S. Susnow susnow@cle.ab.comArticle: 3058
I'm expanding my tools set, and I'm looking for additional licenses for the following PC-based design tools: XACT Viewlogic (PRO or Workview) (with/without ViewSIM/ProSIM) If you have an extra license which you no longer use; I'd like to transfer the license from you, and pay an appropriate fee. Bob Elkind ************************************************************************** Bob Elkind email:videotek@rain.com CIS:72022,21 Video processing, R&D, ASIC, FPGA design consulting 7118 SW Lee Road part-time fax number: 503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903Article: 3059
If you need to use a VHDL type simulator such as MTI; you need to obtain the Vital libraries for the FPGA you're simulating. In case of Xilinx, last time I checked Xilinx still does not have the libraries but MTI will sell it for $3000. Hope this helps! Kayvon IraniArticle: 3060
Xilinx Vital libraries are available from Exemplar Logic. They have a product called Time Explorer that performs back annotation to Vital, schematic viewing and timing analysis (critical path analysis). Since they are part of Antares, as is MTI, they have QAed the libraries with the MTI simulator. They can be contacted at 510-337-3700 and ask for sales, or info@Exemplar.com or www.exemplar.com. In <3154F09F.2629@cinenet.net> Kayvon Irani <kirani@cinenet.net> writes: > >If you need to use a VHDL type simulator such as MTI; you need > to obtain the Vital libraries for the FPGA you're simulating. > In case of Xilinx, last time I checked Xilinx still does not have > the libraries but MTI will sell it for $3000. Hope this helps! > >Kayvon IraniArticle: 3061
klindwor@tech17.informatik.uni-hamburg.de (Andre Klindworth) >We use Altera MAX9000 CPLDs for a couple of designs, but have >a lot of troubles with downloading the configuration data via >the Bitblaster. On average, only one out of 5 programming attempts >succeed. 80% of the downloads end up with a "Device not in socket" >or verification errors. We allready added small capacitors (50 pF) >an serial as well as pull-up/pull-down transistors to the download >wires, but none of these measures increased the robustness of the >programming procedure. > >Naturally, we tried different boards to exclude device or board >errors. > >Has anybody experienced similar problems or has an idea what may >go wrong? Any help/suggestions appreciated. Have you checked your power supply. I have had similar problems (non Altera) on low VCC. T.H.Article: 3062
>>>>> "DAW" == David A Willmore <willmore@whelk.cig.mot.com> writes:
DAW> I'm tyring to drop in a EEPROM for one of these chips and I
DAW> can't find out what bus this part uses. First, am I SOL to
DAW> start with or is this possible? I can speak IIC, uWire, and
DAW> from there, SPI, et al are easy. (it's a serial protocol,
DAW> how hard can it be?)
It's straightforward - clock in, data out. No special protocol is
used, other than the one programmed into the bitstream stored in the
EEPROM. You can find documentation on these circuits on the WWW:
http://www.xilinx.com/products/fpgaspec.htm
Look under the "Serial Configuration PROMs" section.
--
Torbjorn Bakke (tb@vingmed.no) Tel: +47 33 04 21 32
Article: 3063Joe Hass wrote: > I'm looking for an FPGA or EPLD to replace about a dozen CMOS > MSI and SSI parts. I expect to need about 40 I/Os. A very > important requirement is that the power consumption falls to > typical static CMOS levels (tens of microamps) when the clock > is stopped. I've noticed that the Altera Classic EP910 and > EP1810 seem to meet this requirement (in non-turbo mode), but > I'm wondering if there are others I should consider. Be very careful if you are considering using the Altera Classic family for a new design. Since buying out the Intel equivalent PLD line, Altera has been phasing out parts. Several speed grades and packages have already disappeared from the EP910 line up and a whole series of 1810s is currently under notice of obsolescence. Check with your rep! Altera has been encouraging us to move instead to the MAX7000 family. Unfortunately, the MAX7000 parts are not supported by our ABEL and we would have to buy software to use them. Catherine Gyselinck ---------------------------- MPB Technologies | Speak softly but carry | gcat@dorval.mpbtech.qc.ca | a +6 two-handed sword | tel: (514) 683-1490 ---------------------------- fax: (514) 683-1727Article: 3064
The Altera EPX740/780 would meet your needs. They effectively go to 0 current draw when they are idle. On board EPROM config bits, but SRAM working logic. 10ns Tpd. The EPxxx parts did go to "sleep" if you set the non-turbo mode bit, but the EP1810 was always a little bizarre, and scooping up random logic was sometimes tough in the segmented architecture. There are some AMD, Lattice or Cypress parts that would also meet your requirements, specifically the Mach series. A big PLD type device is usually easier to quickly vacuum up existing random logic than an FPGA style device. For one thing, the timing is often simpler. But, that is just my opinion (after having done it for a number of years) Start hunting the Web pages for more info though. If you are looking at things like the EP1810, I think you need more up to date information and databooks. --Richard Vireday Scott Kroeger <scott.kroeger@mei.com> wrote: >Joe Hass wrote: >> >> I'm looking for an FPGA or EPLD to replace about a dozen CMOS >> MSI and SSI parts. I expect to need about 40 I/Os. A very >> important requirement is that the power consumption falls to >> typical static CMOS levels (tens of microamps) when the clock >> is stopped. I've noticed that the Altera Classic EP910 and >> EP1810 seem to meet this requirement (in non-turbo mode), but >> I'm wondering if there are others I should consider. >> > >Xilinx XC3000L (3.3V) family parts have the lowest spec'd Q currents >I've seen (30uA max), and unlike the Altera EPxxx parts, their operating >currents are a product of gate count and the switching frequency of >those gates (like CMOS MSI and SSI). XC3000A (5V) are around 500uA Q. > >In general you will find that SRAM and (Anti)Fuse based FPGA's have low >Q currents and EPROM/Flash based FPGA's do not. > >Remember that the SRAM based parts must be loaded from some external >source and that's another Q current you must consider. Xilinx has app >notes describing how to unpower the configuration PROM after >configuration, so it's Q current can be eliminated. Mostly true for the Xilinx devices, but not for others. >If you find something else in the range of the XC3000L let me know, I >have interest in ultra-low power designs as well. > >Regards, >ScottArticle: 3065
Is there any chance of running XACT Step 6.0 or earlier windows releases under NT?Article: 3066
Has anyone ever gotten LOG/ic PLD Compiler from ISDATA to install? I've downloaded the english and german versions, and locks up every time. My system is 486/50, 8 meg ram, 1.2 gig hard drive, Windows 3.1. I've tried no expanded, and with expanded, but it always locks up. Changed my video driver, still lock. Thanks, EricArticle: 3067
We are just finishing the preliminary design evaluation and specifications for
a RAD-HARD FPGA suitable for military and space applications. Is there any
interest and/or suggestions in the user community for such a device? All
inputs welcomed.
--------------------------------------------------------------------
_______ _______ ?
/ _____ \ / _____ \ AEROSPACE DESIGN CONCEPTS ^
/ / \ \ / / \ \ MEMORIES INTO SPACE ^
__/ /__ | |__| | __\ \__ PLVS VLTRA . . . . .^
/__| |_ \ / \ / _| |__\
| | | | | _ _ | | | | | THE RAMMAN
| |_| | | \\ // | | |_| | Richard Greene
\___/ \ " " / \___/ E-MAIL:RGREENE@NETAXS.COM
| | HUMAN:(609) 859-8833
| oo | FAX: (609) 859-3671
\__/ VINCENTOWN, NJ 08088
Article: 3068In article <1996Mar20.143442.3496@mdl.sandia.gov> kjhass@sandia.gov (Joe Hass) writes: >From: kjhass@sandia.gov (Joe Hass) >Subject: Low-power FPGA or EPLD >Date: Wed, 20 Mar 1996 14:34:42 GMT >I'm looking for an FPGA or EPLD to replace about a dozen CMOS >MSI and SSI parts. I expect to need about 40 I/Os. A very >important requirement is that the power consumption falls to >typical static CMOS levels (tens of microamps) when the clock >is stopped. I've noticed that the Altera Classic EP910 and >EP1810 seem to meet this requirement (in non-turbo mode), but >I'm wondering if there are others I should consider. >Availability of bare die and a few Schmitt inputs would be >significant bonuses, too. >Any suggestions are appreciated. Joe, A couple of years ago I designed an FPGA for customer using the Quicklogic Ql8X12. The customer chose the QL family because they had the lowest power consumption of the available parts and they were avialable as a bare tested die. I know QL has 3.3V parts now so I definitely think they are worth a call. Their phone number is 1-800-842-3742 and they have a web page at www.quicklogic.com. Good Luck Mike Kelly Cogent Computer Systems, Inc. (508) 632-2020Article: 3069
Does anyone have a tool for downloading a configuration file for a Altera MAX9000 CPLD via the Altera BitBlaster - or knows where to get one (perhaps it is allready included in MAX+plusII and we just haven't found it)? The point is that we'd like to provide a remote updating capability for our customer without forcing him to install anything beyond what is really essential. Thanks for your help. -- --------------------------------------------------------------------------- Andre' Klindworth Universitaet Hamburg, FB Informatik klindwor@informatik.uni-hamburg.de Vogt-Koelln-Str.30, D-22527 Hamburg http://tech-www.informatik.uni-hamburg.de/Personal/klindwor/Klindworth.htmlArticle: 3070
I have stumbled across a problem with an archived Minc DSL design targeting a Xilinx 3064PQ160. The design was originally completed with the 9403 version of Cadence's Picdesigner. Now, using 9502 Picdesigner with the same DSL source, the Xilinx part is dead. I have tried numerous experiments including makebits options, seeds, aprloops, and guide files. Nothing worked. Out of frustration, I have restored the 9403 version of Picdesigner in order to process the design. This works... The last experiment tried was to process the design through the PL-Partition step in 9502 and 9403, swap the XNF files, then continue processing the design through the Cadence/Minc flow. The results: XNF file generated by 9502 Picdesigner (Partition) failed XNF file generated by 9403 Picdesigner (Partition) worked This could be a timing related issue: Xdelay outputs from both routes are quite different. Interestingly, the Verilog timing simulations from both working and non-working routes are the same.... Has anyone else had a similar experience? Thanks, Tom ----- Thomas Lane | The opinions expressed here are my own and thomas.lane@tek.com | not those of my employer. Tektronix, Inc |Article: 3071
Scott Kroeger wrote: > The Xilinx PROMs use a proprietary serial protocol. Atmel makes > compatible serial EEPROMs. The devices you want are the > AT17C65/128/256. The smallest part, AT17C65, is more than large enough > to replace the 1736. > > Data sheets are available at: > > http://www.atmel.com/atmel/products/products3.html I found it and I've requested a sample and databook. Thanks for the help. ;) Cheers, DavidArticle: 3072
Torbjoern Bakke wrote: > It's straightforward - clock in, data out. No special protocol is > used, other than the one programmed into the bitstream stored in the > EEPROM. You can find documentation on these circuits on the WWW: > > http://www.xilinx.com/products/fpgaspec.htm > > Look under the "Serial Configuration PROMs" section. Thanks! I hadn't found this one. I'll take a look. ;) Cheers, DavidArticle: 3073
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / Verilog Testbenches for The Great ESDA Shootout
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Here's a copy of the two testbenches plus vector files for those who want
to try for themselves the Great ESDA Shootout from the recent HP Design
SuperCon. To get the details of the contest, read the current issue of
"Integrated System Design" magazine (it's in the April '96 issue which was
mailed out to readers last week.)
To run the first testbench:
UNIX>verilog machine3.v tester3.v -i vector_file3.vec
To run the Post-ECO testbench:
UNIX>verilog machine4.v tester4.v -i vector_file4.vec
For those who try this contest at home: I'd like to hear how you do!
For those who don't try but want to comment on the Shootout after reading
about it, I'd like to hear what you have to say, too!
- John Cooley
the ESNUG guy
----------- template.v ---------------------------------------------------
module machine (a, b, c, state, clock, reset, d, e, dstate, estate, f, g, h, i);
input a, b, d, e, clock, reset, f, g;
input [0:2] c;
output h, i;
output [0:3] state;
reg [0:3] state;
output [0:1] dstate, estate;
reg [0:1] dstate, estate;
// put your design in here and relabel the file "machine3.v" !!!!
endmodule
----------- tester3.v ----------------------------------------------------
//
// "tester3.v" -- the Verilog testbench for use at the HP Design Supercon's
// Great ESDA Shootout for testing "machine3.v" using "vector_file3.vec"
//
module tester ();
reg a, b, d, e, clock, reset, f, g;
reg [0:2] c;
wire h, i;
wire [0:3] state;
wire [0:1] dstate, estate;
reg [0:19] t_vec;
reg [0:9] george_out;
reg [0:19] test_vectors [0:46];
integer int;
// load up the 45 20-bit test vectors & test the design
initial
begin
$readmemb("vector_file3.vec", test_vectors);
reset = 1'b0;
@(negedge clock);
for (int = 0; int < 47 ; int = int + 1)
begin
t_vec = test_vectors[int];
{a, b, c, d, e, f, g} = {t_vec[0:4], t_vec[10:11], t_vec[16:17]};
reset = t_vec[9];
@(negedge clock);
george_out = { state, dstate, estate, h, i };
if ( {t_vec[5:8], t_vec[12:15], t_vec[18:19]} == george_out )
begin
$display("\t\t INPUTS BEFORE posedge CLOCK reset = %b", reset);
$display("\t\t were: a = %b", a, " b = %b ", b, " c = %b ", c);
$display("\t\t d = %b", d, " e = %b ", e, " f = %b ", f, " g = %b ", g);
$display("\t\t AFTER posedge CLOCK: state = %b", state, " dstate = %b", dstate,
" estate = %b", estate, " h = %b ", h, " i = %b ", i);
$display("\t Cool! Just what I expected! \t\t Sim Time = %t", $time, "\n");
end
else
begin
$display("\n\t ****** BAD NEWS, DUDE! ***********");
$display("\t\t INPUTS BEFORE posedge CLOCK reset = %b", reset);
$display("\t\t were: a = %b", a, " b = %b ", b, " c = %b ", c);
$display("\t\t d = %b", d, " e = %b ", e, " f = %b ", f, " g = %b ", g);
$display("\t\t AFTER posedge CLOCK: state = %b", state, " dstate = %b", dstate,
" estate = %b", estate, " h = %b ", h, " i = %b ", i);
$display("\t\t I EXPECTED: state = %b", t_vec[5:8], " dstate = %b", t_vec[12:13],
" estate = %b", t_vec[14:15], " h = %b ", t_vec[18], " i = %b ", t_vec[19]);
$display("\n\t ... check your state flow, dude. \t\t Sim Time = %t", $time, "\n");
$finish;
end
end
$display("\n ###### CONGRATS! -- THIS IS A FUNCTIONALLY CORRECT DESIGN!!!! ###### \n\n");
$finish;
end
// create clock
initial clock = 1'b0;
always #50 clock = !clock;
// instantiate design to be tested
machine george (a, b, c, state, clock, reset, d, e, dstate, estate, f, g, h, i);
endmodule
----------- vector_file3.vec ---------------------------------------------
X0XXX00001XX00000000
X0111010100100001001
XX000010100100001100
XX010010101001011001
XX01101100XX01010000
XXXXX10000XX01010000
XXXXX00001XX00000000
X1XXX000100100000000
X0XXX001101001010110
XX10101000XX01011000
01XXX00100XX01010000
XX11100100XX01011100
XX00000010XX01010110
XXXXX00110XX01010000
XX01101010XX01011001
XXXXX00001XX00000100
X1XXX000101001010000
XXXXX00110XX01010000
XX10101000XX01010000
11XXX10000XX01010000
X0XXX11010XX10010000
XX000110100X11010000
XX01111100XX00010000
XXXXX111100X00010000
XXXXX000001X01010000
X0XXX01010XX01100000
XX01101100X101110000
XXXXX10000XX01000000
X1XXX10010X010010000
XXXXX101101X00010000
XX101110000X00010000
00XXX110001X01010000
01XXX10100XX01011001
XX10010100XX01010110
XX00010010XX01010000
XXXXX10110XX01010000
XX10111000XX01010000
1XXXX11110XX01010000
XXXXX00000XX01010000
X0XXX01010XX01100000
XX01101100X001000000
XXXXX10000X101000000
X1XXX100100010010000
XXXXX101101X00010000
XX011110101X01010000
XXXXX00001XX00000000
XXXXX00001XX00000000
----------- tester4.v ----------------------------------------------------
//
// "tester4.v" -- the Verilog testbench for use at the HP Design
// Supercon's Great ESDA Shootout for testing the *post-ECO*
// "machine4.v" using "vector_file4.vec"
//
module tester ();
reg a, b, d, e, clock, reset, f, g;
reg [0:2] c;
wire h, i;
wire [0:3] state;
wire [0:1] dstate, estate;
reg [0:19] t_vec;
reg [0:9] george_out;
reg [0:19] test_vectors [0:44];
integer int;
// load up the 45 20-bit test vectors & test the design
initial
begin
$readmemb("vector_file4.vec", test_vectors);
reset = 1'b0;
@(negedge clock);
for (int = 0; int < 45 ; int = int + 1)
begin
t_vec = test_vectors[int];
{a, b, c, d, e, f, g} = {t_vec[0:4], t_vec[10:11], t_vec[16:17]};
reset = t_vec[9];
@(negedge clock);
george_out = { state, dstate, estate, h, i };
if ( {t_vec[5:8], t_vec[12:15], t_vec[18:19]} == george_out )
begin
$display("\t\t INPUTS BEFORE posedge CLOCK reset = %b", reset);
$display("\t\t were: a = %b", a, " b = %b ", b, " c = %b ", c);
$display("\t\t d = %b", d, " e = %b ", e, " f = %b ", f, " g = %b ", g);
$display("\t\t AFTER posedge CLOCK: state = %b", state, " dstate = %b", dstate,
" estate = %b", estate, " h = %b ", h, " i = %b ", i);
$display("\t Cool! Just what I expected! \t\t Sim Time = %t", $time, "\n");
end
else
begin
$display("\n\t ****** BAD NEWS, DUDE! ***********");
$display("\t\t INPUTS BEFORE posedge CLOCK reset = %b", reset);
$display("\t\t were: a = %b", a, " b = %b ", b, " c = %b ", c);
$display("\t\t d = %b", d, " e = %b ", e, " f = %b ", f, " g = %b ", g);
$display("\t\t AFTER posedge CLOCK: state = %b", state, " dstate = %b", dstate,
" estate = %b", estate, " h = %b ", h, " i = %b ", i);
$display("\t\t I EXPECTED: state = %b", t_vec[5:8], " dstate = %b", t_vec[12:13],
" estate = %b", t_vec[14:15], " h = %b ", t_vec[18], " i = %b ", t_vec[19]);
$display("\n\t ... check your state flow, dude. \t\t Sim Time = %t", $time, "\n");
$finish;
end
end
$display("\n ###### CONGRATS! -- THIS IS A *Post-ECO* CORRECT DESIGN!!!! ###### \n\n");
$finish;
end
// create clock
initial clock = 1'b0;
always #50 clock = !clock;
// instantiate design to be tested
machine george (a, b, c, state, clock, reset, d, e, dstate, estate, f, g, h, i);
endmodule
----------- vector_file4.vec ---------------------------------------------
XXXXX00101XX00110000
X0XXX00000XX01000000
X1XXX00010X101000000
XXXXX00010X101001100
XXXXX00110X001010110
XX10101000XX01011000
1XXXX10000XX01010110
X1XXX10010XX11011100
XXXXX100100X00010000
X1XXX101101X10011100
X1101110001X10011000
01XXX101001X10011001
XX101101000X11010000
XX00010010XX00011000
X0XXX100100X01011000
XXXXX101101X01011000
XX01111100XX01011000
XXXXX11110XX01011000
XXXXX00100XX01011000
XXXXX00000XX01100100
X1XXX00010X001000100
XXXXX00110X001011000
XX10101000XX01011000
0111001000XX01011000
0000001000XX01011000
0101001000XX01011000
0100000010XX01011000
XXXXX00110X001011000
XX10001110XX01011000
XXXXX01010XX01011001
XX11001010XX01010000
XX01101100XX01011000
XXXXX10000XX01011000
X0XXX11010XX11011000
XX10011010XX00011000
X001111100XX01011000
XXXXX11110XX01011000
XXXXX00100XX01011000
XXXXX00000XX01101000
X0XXX01010X101111001
XXXXX00101XX00111000
XXXXX00101XX00111000
XXXXX00101XX00111000
XXXXX00101XX00111000
XXXXX00101XX00111000
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4126 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3074
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / VHDL Testbenches for The Great ESDA Shootout
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Here's a copy of the two testbenches plus vector files for those who want
to try for themselves the Great ESDA Shootout from the recent HP Design
SuperCon. To get the details of the contest, read the current issue of
"Integrated System Design" magazine (it's in the April '96 issue which was
mailed out to readers last week.)
To run the first testbench using Cadence Leapfrog:
UNIX>cv -m machine3.vhd tester3.vhd
UNIX>ev -m work.tester:foo
UNIX>sv -b -run work.tester:foo
To run the Post-ECO testbench:
UNIX>cv -m machine4.vhd tester4.vhd
UNIX>ev -m work.tester:foo
UNIX>sv -b -run work.tester:foo
For those who try this contest at home: I'd like to hear how you do!
For those who don't try but want to comment on the Shootout after reading
about it, I'd like to hear what you have to say, too!
- John Cooley
the ESNUG guy
----------- template.vhd -------------------------------------------------
library ieee, std;
use std.textio.all;
use ieee.std_logic_1164.all;
entity machine is
port ( a, b : in std_logic;
c : in std_logic_vector(0 to 2);
state : buffer std_logic_vector(0 to 3);
clock : in std_logic;
reset : in std_logic;
d, e : in std_logic;
dstate : buffer std_logic_vector(0 to 1);
estate : buffer std_logic_vector(0 to 1);
f, g : in std_logic;
h, i : out std_logic);
end machine;
architecture gooby of machine is
begin
-- Put your design in here and relabel it "machine3.vhd" !!!!!
end gooby;
----------- tester3.vhd --------------------------------------------------
--
-- "tester3.vhd" -- the VHDL testbench for use at the HP Design Supercon's
-- Great ESDA Shootout for testing "machine3.vhd" using "vector_file3.vec"
--
library ieee, std;
use std.textio.all;
use ieee.std_logic_1164.all;
-- use work.all;
entity tester is
end tester;
architecture foo of tester is
function stdvc_2_str (inp : std_logic_vector ) return string is
variable temp : string(1 to inp'right+1);
begin
for i in inp'range loop
if (inp(i) = '1' ) then
temp(i+1) := '1';
elsif (inp(i) = '0' ) then
temp(i+1) := '0';
else
temp(i+1) := 'X';
end if;
end loop;
return temp;
end;
function str_2_stdvc (inp : string ) return std_logic_vector is
variable temp : std_logic_vector(0 to inp'right-1);
begin
for i in inp'range loop
if (inp(i) = '1' ) then
temp(i-1) := '1';
elsif (inp(i) = '0' ) then
temp(i-1) := '0';
else
temp(i-1) := 'X';
end if;
end loop;
return temp;
end;
function std_2_str (inp : std_logic ) return string is
variable temp : string(1 to 1);
begin
if (inp = '1' ) then
temp(1) := '1';
elsif (inp = '0' ) then
temp(1) := '0';
else
temp(1) := 'X';
end if;
return temp;
end;
component machine
port ( a, b : in std_logic;
c : in std_logic_vector(0 to 2);
state : buffer std_logic_vector(0 to 3);
clock : in std_logic;
reset : in std_logic;
d, e : in std_logic;
dstate : buffer std_logic_vector(0 to 1);
estate : buffer std_logic_vector(0 to 1);
f, g : in std_logic;
h, i : out std_logic);
end component;
for all : machine use entity work.machine(gooby);
signal a, b : std_logic := 'X';
signal c : std_logic_vector(0 to 2) := "XXX";
signal state : std_logic_vector(0 to 3) := "XXXX";
signal clock : std_logic := 'X';
signal reset : std_logic := 'X';
signal d, e : std_logic := 'X';
signal dstate : std_logic_vector(0 to 1) := "XX";
signal estate : std_logic_vector(0 to 1) := "XX";
signal f, g : std_logic := 'X';
signal h, i : std_logic := 'X';
signal done : std_logic := '0';
begin
process
file test_vectors : text is in "vector_file3.vec";
variable t_vec_line : line;
variable t_vec_str : string(1 to 20);
variable t_vec : std_logic_vector(0 to 19);
variable george_out : std_logic_vector(0 to 9);
variable george_expected : std_logic_vector(0 to 9);
variable tmp_state : std_logic_vector(0 to 3);
variable tmp_dstate : std_logic_vector(0 to 1);
variable tmp_estate : std_logic_vector(0 to 1);
variable tmp_h, tmp_i : std_logic;
variable fileline : line;
begin
reset <= '0';
wait until clock = '0' and clock'event;
while (not endfile(test_vectors)) loop
readline (test_vectors, t_vec_line);
read (t_vec_line, t_vec_str);
t_vec := str_2_stdvc(t_vec_str);
a <= t_vec(0);
b <= t_vec(1);
c <= t_vec(2 to 4);
d <= t_vec(10);
e <= t_vec(11);
f <= t_vec(16);
g <= t_vec(17);
tmp_state := t_vec(5 to 8);
tmp_dstate := t_vec(12 to 13);
tmp_estate := t_vec(14 to 15);
tmp_h := t_vec(18);
tmp_i := t_vec(19);
reset <= t_vec(9);
wait until clock = '0' and clock'event;
george_out := ( state & dstate & estate & h & i);
george_expected := ( t_vec(5 to 8) & t_vec(12 to 15) & t_vec(18 to 19));
if ( george_expected = george_out ) then
assert false
report
" INPUTS BEFORE positive edge of CLOCK reset = " &
std_2_str(reset) & lf &
" were: a = " & std_2_str(a) & " b = " & std_2_str(b) & " c = " &
stdvc_2_str(c) & lf &
" d = " & std_2_str(d) & " e = " & std_2_str(e) &
" f = " & std_2_str(f) & " g = " & std_2_str(g) & lf &
" AFTER positive edge of CLOCK: state = " & stdvc_2_str(state) &
" dstate = " & stdvc_2_str(dstate) & " estate = " &
stdvc_2_str(estate) & " h = " & std_2_str(h) & " i = " & std_2_str(i) & lf &
" Cool! Just what I expected! " & lf
severity note;
else
assert false
report
"************** BAD NEWS, DUDE! *************" & lf &
" INPUTS BEFORE positive edge of CLOCK reset = " &
std_2_str(reset) & lf &
" were: a = " & std_2_str(a) & " b = " & std_2_str(b) &
" c = " &
stdvc_2_str(c) & lf &
" d = " & std_2_str(d) & " e = " & std_2_str(e) &
" f = " & std_2_str(f) & " g = " & std_2_str(g) & lf &
" AFTER positive edge of CLOCK: state = " & stdvc_2_str(state) &
" dstate = " & stdvc_2_str(dstate) & " estate = " &
stdvc_2_str(estate) & " h = " & std_2_str(h) & " i = " &
std_2_str(i) & lf &
" I EXPECTED: state = " &
stdvc_2_str(tmp_state) &
" dstate = " & stdvc_2_str(tmp_dstate) &
" estate = " & stdvc_2_str(tmp_estate) &
" h = " & std_2_str(tmp_h) &
" i = " & std_2_str(tmp_i) & lf &
" ... check your state flow, dude. " & lf
severity failure;
done <= '1';
end if;
end loop;
assert false
report lf & lf &
" ###### CONGRATS! -- THIS IS A FUNCTIONALLY CORRECT DESIGN!!!! ###### "
& lf & lf
severity failure;
done <= '1';
end process;
process -- clock generation
begin
while ( done = '0' ) loop
clock <= '1';
wait for 50 ns;
clock <= '0';
wait for 50 ns;
end loop;
end process; -- clock generation
george : machine
port map ( a, b, c , state, clock, reset, d, e, dstate, estate, f, g, h, i);
end foo;
----------- vector_file3.vec ---------------------------------------------
X0XXX00001XX00000000
X0111010100100001001
XX000010100100001100
XX010010101001011001
XX01101100XX01010000
XXXXX10000XX01010000
XXXXX00001XX00000000
X1XXX000100100000000
X0XXX001101001010110
XX10101000XX01011000
01XXX00100XX01010000
XX11100100XX01011100
XX00000010XX01010110
XXXXX00110XX01010000
XX01101010XX01011001
XXXXX00001XX00000100
X1XXX000101001010000
XXXXX00110XX01010000
XX10101000XX01010000
11XXX10000XX01010000
X0XXX11010XX10010000
XX000110100X11010000
XX01111100XX00010000
XXXXX111100X00010000
XXXXX000001X01010000
X0XXX01010XX01100000
XX01101100X101110000
XXXXX10000XX01000000
X1XXX10010X010010000
XXXXX101101X00010000
XX101110000X00010000
00XXX110001X01010000
01XXX10100XX01011001
XX10010100XX01010110
XX00010010XX01010000
XXXXX10110XX01010000
XX10111000XX01010000
1XXXX11110XX01010000
XXXXX00000XX01010000
X0XXX01010XX01100000
XX01101100X001000000
XXXXX10000X101000000
X1XXX100100010010000
XXXXX101101X00010000
XX011110101X01010000
XXXXX00001XX00000000
XXXXX00001XX00000000
XXXXX00001XX00000000
XXXXX00001XX00000000
XXXXX00001XX00000000
XXXXX00001XX00000000
----------- tester4.vhd --------------------------------------------------
--
-- "tester4.vhd" -- the VHDL testbench for use at the HP Design
-- Supercon's Great ESDA Shootout for testing the *post-ECO*
-- "machine4.vhd" using "vector_file4.vec"
--
library ieee, std;
use std.textio.all;
use ieee.std_logic_1164.all;
-- use work.all;
entity tester is
end tester;
architecture foo of tester is
function stdvc_2_str (inp : std_logic_vector ) return string is
variable temp : string(1 to inp'right+1);
begin
for i in inp'range loop
if (inp(i) = '1' ) then
temp(i+1) := '1';
elsif (inp(i) = '0' ) then
temp(i+1) := '0';
else
temp(i+1) := 'X';
end if;
end loop;
return temp;
end;
function str_2_stdvc (inp : string ) return std_logic_vector is
variable temp : std_logic_vector(0 to inp'right-1);
begin
for i in inp'range loop
if (inp(i) = '1' ) then
temp(i-1) := '1';
elsif (inp(i) = '0' ) then
temp(i-1) := '0';
else
temp(i-1) := 'X';
end if;
end loop;
return temp;
end;
function std_2_str (inp : std_logic ) return string is
variable temp : string(1 to 1);
begin
if (inp = '1' ) then
temp(1) := '1';
elsif (inp = '0' ) then
temp(1) := '0';
else
temp(1) := 'X';
end if;
return temp;
end;
component machine
port ( a, b : in std_logic;
c : in std_logic_vector(0 to 2);
state : buffer std_logic_vector(0 to 3);
clock : in std_logic;
reset : in std_logic;
d, e : in std_logic;
dstate : buffer std_logic_vector(0 to 1);
estate : buffer std_logic_vector(0 to 1);
f, g : in std_logic;
h, i : out std_logic);
end component;
for all : machine use entity work.machine(gooby);
signal a, b : std_logic := 'X';
signal c : std_logic_vector(0 to 2) := "XXX";
signal state : std_logic_vector(0 to 3) := "XXXX";
signal clock : std_logic := 'X';
signal reset : std_logic := 'X';
signal d, e : std_logic := 'X';
signal dstate : std_logic_vector(0 to 1) := "XX";
signal estate : std_logic_vector(0 to 1) := "XX";
signal f, g : std_logic := 'X';
signal h, i : std_logic := 'X';
signal done : std_logic := '0';
begin
process
file test_vectors : text is in "vector_file4.vec";
variable t_vec_line : line;
variable t_vec_str : string(1 to 20);
variable t_vec : std_logic_vector(0 to 19);
variable george_out : std_logic_vector(0 to 9);
variable george_expected : std_logic_vector(0 to 9);
variable tmp_state : std_logic_vector(0 to 3);
variable tmp_dstate : std_logic_vector(0 to 1);
variable tmp_estate : std_logic_vector(0 to 1);
variable tmp_h, tmp_i : std_logic;
variable fileline : line;
begin
reset <= '0';
wait until clock = '0' and clock'event;
while (not endfile(test_vectors)) loop
readline (test_vectors, t_vec_line);
read (t_vec_line, t_vec_str);
t_vec := str_2_stdvc(t_vec_str);
a <= t_vec(0);
b <= t_vec(1);
c <= t_vec(2 to 4);
d <= t_vec(10);
e <= t_vec(11);
f <= t_vec(16);
g <= t_vec(17);
tmp_state := t_vec(5 to 8);
tmp_dstate := t_vec(12 to 13);
tmp_estate := t_vec(14 to 15);
tmp_h := t_vec(18);
tmp_i := t_vec(19);
reset <= t_vec(9);
wait until clock = '0' and clock'event;
george_out := ( state & dstate & estate & h & i);
george_expected := ( t_vec(5 to 8) & t_vec(12 to 15) & t_vec(18 to 19));
if ( george_expected = george_out ) then
assert false
report
" INPUTS BEFORE positive edge of CLOCK reset = " &
std_2_str(reset) & lf &
" were: a = " & std_2_str(a) & " b = " & std_2_str(b) & " c = " &
stdvc_2_str(c) & lf &
" d = " & std_2_str(d) & " e = " & std_2_str(e) &
" f = " & std_2_str(f) & " g = " & std_2_str(g) & lf &
" AFTER positive edge of CLOCK: state = " & stdvc_2_str(state) &
" dstate = " & stdvc_2_str(dstate) & " estate = " &
stdvc_2_str(estate) & " h = " & std_2_str(h) & " i = " & std_2_str(i) & lf &
" Cool! Just what I expected! " & lf
severity note;
else
assert false
report
"************** BAD NEWS, DUDE! *************" & lf &
" INPUTS BEFORE positive edge of CLOCK reset = " &
std_2_str(reset) & lf &
" were: a = " & std_2_str(a) & " b = " & std_2_str(b) &
" c = " &
stdvc_2_str(c) & lf &
" d = " & std_2_str(d) & " e = " & std_2_str(e) &
" f = " & std_2_str(f) & " g = " & std_2_str(g) & lf &
" AFTER positive edge of CLOCK: state = " & stdvc_2_str(state) &
" dstate = " & stdvc_2_str(dstate) & " estate = " &
stdvc_2_str(estate) & " h = " & std_2_str(h) & " i = " &
std_2_str(i) & lf &
" I EXPECTED: state = " &
stdvc_2_str(tmp_state) &
" dstate = " & stdvc_2_str(tmp_dstate) &
" estate = " & stdvc_2_str(tmp_estate) &
" h = " & std_2_str(tmp_h) &
" i = " & std_2_str(tmp_i) & lf &
" ... check your state flow, dude. " & lf
severity failure;
done <= '1';
end if;
end loop;
assert false
report lf & lf &
" ###### CONGRATS! -- THIS IS A *Post-ECO* CORRECT DESIGN!!!! ###### "
& lf & lf
severity failure;
done <= '1';
end process;
process -- clock generation
begin
while ( done = '0' ) loop
clock <= '1';
wait for 50 ns;
clock <= '0';
wait for 50 ns;
end loop;
end process; -- clock generation
george : machine
port map ( a, b, c , state, clock, reset, d, e, dstate, estate, f, g, h, i);
end foo;
----------- vector_file4.vec ---------------------------------------------
XXXXX00101XX00110000
X0XXX00000XX01000000
X1XXX00010X101000000
XXXXX00010X101001100
XXXXX00110X001010110
XX10101000XX01011000
1XXXX10000XX01010110
X1XXX10010XX11011100
XXXXX100100X00010000
X1XXX101101X10011100
X1101110001X10011000
01XXX101001X10011001
XX101101000X11010000
XX00010010XX00011000
X0XXX100100X01011000
XXXXX101101X01011000
XX01111100XX01011000
XXXXX11110XX01011000
XXXXX00100XX01011000
XXXXX00000XX01100100
X1XXX00010X001000100
XXXXX00110X001011000
XX10101000XX01011000
0111001000XX01011000
0000001000XX01011000
0101001000XX01011000
0100000010XX01011000
XXXXX00110X001011000
XX10001110XX01011000
XXXXX01010XX01011001
XX11001010XX01010000
XX01101100XX01011000
XXXXX10000XX01011000
X0XXX11010XX11011000
XX10011010XX00011000
X001111100XX01011000
XXXXX11110XX01011000
XXXXX00100XX01011000
XXXXX00000XX01101000
X0XXX01010X101111001
XXXXX00101XX00111000
XXXXX00101XX00111000
XXXXX00101XX00111000
XXXXX00101XX00111000
XXXXX00101XX00111000
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4126 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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