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E2W3: Electrical Engineering WWW Hotlist at http://www.e2w3.com/ Upgraded We have just completed our first major upgrade to E2W3 since launching it last January with the goal of providing the working engineer and engineering manager with pointers to resources that they can use in their work. The site now points to more than 250 unique WWW resources organized into 16 categories: EDA Software Vendors; PC and Workstation Hardware; PC and Workstation Software; ASIC and FPGA Vendors; Semiconductor Manufacturers; Disk Drives and Controllers; Connectors and Cables; Power Supplies and Batteries; Distributors, VARs and Dealers; Contract Design and Manufacturing Services; Manufacturing, Assy, and Test Equipment Vendors; Periodicals and Publishers; Conferences; Professional Associations & Non-Profits; USENET News Archives & FAQs; Other Directories. Because of the increase in sites we have added a "What's New" page that is a rolling list of sites added in the last thirty days and a simple search function that permits you to display all of the entries whose title, text, or URL contain a target word or phrase. Also, it is now possible to add a new site immediately to a category, or modify the text, title, or URL for a site you have already entered--so if we have overlooked your WWW or FTP site, please feel free to use your forms-equipped browser to add it. ______________________________________________________________________________ Sean Murphy, President, Leader-Murphy, Inc. (skmurphy@netcom.com 408 252-9676) WWW-Enabled Applications and Methodology Consulting: "Knowledge, Refined from Information Derived from Data, is the Fundamental Asset of the Enterprise" URL: http://www.l-m.com/l-m.html & http://www.e2w3.com/ ______________________________________________________________________________Article: 1676
>You wrote:
>>
>>In article <40ggn1$41o@ocean.silcom.com>, ksteele@silcom.com wrote:
>>>In <40d8s8$pod@ingate.adc.com>, swam@adc.com (Steve Swam) writes:
>>>
>>>>John Obenauf (John.Obenauf%aeup@msg.ti.com) wrote:
>>>>: Does anyone know of who makes alternative devices to Xilinx's
>PROMs?
>>>>: Specifically interested in the 1765 deivce.
>>>>
>>>>Atmel makes a series of replacement parts. They are also
>reprogrammable.
>
Okay folks, here's the scoop...Atmel makes an EEPROM version of the
17CXXX family of parts that is pin compatable with the OTP EPROM
version available else-where. The parts are in system
(re)-programmable (5V) via a 2 wire serial interface. The parts are
available in 8 pin dip, 20 pin soic and 20 pin plcc. They are
available in production volumes in two densities currently, the AT17C65
and the AT17C128. A higher density version of the part will be along
soon.
There is one additional feature of the parts that is neat. Pin 7
(usually reserved for 12V/5V Vpp on the EPROM parts) can be used to
switch between 17CXXX mode and 24CXXX mode on the EEPROM parts. This
allow you to re-program the serial or move arround in the memory space.
For example the serial could contain FPGA programming info. at 0000
address and some configration setup data further up the memory space
that is addressed after the FPGA has loaded.
If you would like more info. on these parts please send your snail mail
address to martin@atmel.com. and I will make sure that a data sheet is
sent out by return. If you have questions drop me an e-mail and I'll
get an answer back to you asap.
Regards
Martin Mason
FPGA Systems Architect.
Atmel Corp.
2125 O'Nel Drive
San Jose, CA 95131
Martin@atmel.com Tele (408) 436 4178 Fax (408) 436 4300
Article: 1677> > In article <08-08-1995.66392@dilleng> Tom Dillon, tom@dilleng.wa.com > writes: > >>I'm a fairly new user of Xilinx FPGAs. > >>I'm having a few problems with my current design using a Xilinx xc4013 > >>FPGA. With only around 84% CLB utlilzation and under 40% flip-flop > >>utilization, the XACT software is crashing on routing. It always ends up > >>with 70 unroutes. > >> > >>I'm sure I'm not pushing it to more than available routing resources when > >>the CLB utilization is not filled. > >> > >>Handrouting all the signals is the last thing that I'm opting for. > >> > >>Any help is well appreciated > > > >That is a very high usage for a 4013. It would be more confortable around 60 to 65%. > > You could get upto more than 95% utilization for 4013s as with all other members of xc4000 family with the exception of 4025. Here are a few suggestions, 1. The IO placement is something user can control easily using the constraints (cst) file. Try a few different IO placements which makes sense to your design 2. If this is not a timing critical design, you could actually run router in 2 passes First pass to route the design ignoring the net delays and if the design can be routed the second pass will improve the net delays. This is a really helpful option 3. Try some combinations of higher placer efforts and router efforts default I guess is 2 for both p.e and r.e and it goes upto 5 for both 4. If you are using higher placer efforts, you might also want to try different seeds. I guess the seeds does matter for placer efforts > 4 5. Try to work on relaxing TIMESPECS if you have some really stringent 6. If all the above fails call up their Support Line. I've heard that they are very helpful over there.. Good Luck.Article: 1678
John Forrest (jf@ap.co.umist.ac.uk) wrote: : Does anyone know the format of timespecs in Xilinx XNF v5. I want to : include : some in a handwritten xnf file. : Even an example would help. >From a .xnf file generated from a Mentor schematic with TIMESPEC and TIMEGROUP properties:Article: 1679
As the other replies have indicated, you cannot convert the bit stream. Although Xilinx hardware and 3rd party asics are an option, the may not be optimal solutions for low volume applications. Perhaps the easiest way is to go back to your original design and retarget the device for an epld. This is quite easy if you have used xilinx's unified libraries to create you schematic. any text-based heirarchy should port right over. when you retarget the part, the libraries are also changed to the epld version of the libraries. Since the libraries are unified, a counter (for example) in a 4000 library will appear exactly the same as the same-named counter in the epld library. the design tools will implement the same counter function in the epld as it would in the fpga. Good Luck, John DeHaven - Field Applications Engineer, Marshall Industries.Article: 1680
I'll try again - my last posting got chopped in half (why?)... John Forrest (jf@ap.co.umist.ac.uk) wrote: : Does anyone know the format of timespecs in Xilinx XNF v5. I want to : include : some in a handwritten xnf file. : Even an example would help. >From a .xnf file generated from a Mentor schematic with TIMESPEC and TIMEGROUP properties:Article: 1681
Nick Gent (nickg@hpqt0220.sqf.hp.com) wrote: : I'll try again - my last posting got chopped in half (why?)... : John Forrest (jf@ap.co.umist.ac.uk) wrote: : : Does anyone know the format of timespecs in Xilinx XNF v5. I want to : : include : : some in a handwritten xnf file. : : Even an example would help. : From a .xnf file generated from a Mentor schematic with TIMESPEC and : TIMEGROUP properties: Nick appears to be having a bit of trouble here! I'll have a go! >From a .xnf file generated from a Mentor schematic with TIMESPEC and TIMEGROUP properties:Article: 1682
Final Call for papers
1 day colloquium
Verification of hardware-software codesigns
The second one day colloquium in the IEE "Hardware/Software Codesign"
series, 'Verification of hardware-software codesigns' is being
organised by PG C2 (Hardware and Systems Engineering) and PG C6
(Systems Engineering for Automation) at Savoy Place, London, England
on Tuesday 17 October 1995.
Codesign refers to the simultaneous process of designing both hardware
and software to meet some specified performance objectives. Unlike
more traditional approaches to system engineering where the hardware
and software partitions are relatively rigid, codesigns are
characterised by flexible partitions that may be shifted to meet
changing performance criteria. One consequence of this is that
sophisticated and flexible specification, synthesis, verification &
validation tools become essential to the design process.
The first colloquium in this series addressed current research and
practice in the area of partitioning codesigns. The purpose of this
colloquium is to examine the verification and validation processes
essential for effective hardware-software codesign. Papers are invited
on all aspects of verification and validation. Papers which address
toolsets and their practical application are especially welcome.
Prospective authors are invited to submit a synopsis of about 300
words before August 18 1995, to
Richard Taylor, Hewlett-Packard Laboratories, Bristol, Filton Road,
Stoke Gifford, Bristol, BS12 6QZ, United Kingdom. tel.(+44) 117 922
9545 fax : (+44) 117 922 8925 email : rwt@hplb.hpl.hp.com
Trevor York Department of Electrical and Electronic Engineering,
UMIST, P.O. Box 88, Manchester M60 1QD United Kingdom Tel. (+44) 61
2004729 Fax. (+44) 61 200 4781 Email. york@fs5.ee.umist.ac.uk
--
Richard Taylor, __o o __o __o
Hewlett-Packard Laboratories, Bristol, UK. `\<, \\_/\_, `\<,-`\<,
rwt@hplb.hpl.hp.com O/ O O O O/----/ O
phone : +44 (0) 117 922 9545
fax : +44 (0) 117 922 8925
Article: 1683Does anyone know, if there are ZIF sockets (PGA 429 zig-zag) available for ATT ORCA devices 2C26 and 2C40 ? I would appreciate, if you could tell also manufacturers device number, and some pricing info. Thanks, IlmariArticle: 1684
In article <40npl7$jsj@yama.mcc.ac.uk> John Forrest <jf@ap.co.umist.ac.uk> writes: >In article <08-08-1995.66392@dilleng> Tom Dillon, tom@dilleng.wa.com >writes: >>>I'm a fairly new user of Xilinx FPGAs. >>>I'm having a few problems with my current design using a Xilinx xc4013 >>>FPGA. With only around 84% CLB utlilzation and under 40% flip-flop >>>utilization, the XACT software is crashing on routing. It always ends up >>>with 70 unroutes. >>> >>>I'm sure I'm not pushing it to more than available routing resources when >>>the CLB utilization is not filled. >>> >>>Handrouting all the signals is the last thing that I'm opting for. >>> >>>Any help is well appreciated >> >>That is a very high usage for a 4013. It would be more confortable around 60 to 65%. >> > >I'm used to getting above 85% utilisation on 4010s - does this mean that >utilisation under 4013s is nothing like as good? I have found that it depends an several things, CLB usage, TBUF usage, type of design, and how well the I/O are layed out. Also the speed you are trying to run the device has alot to do with what is an exceptable route. As the device gets bigger (i.e. 4010 -> 4013), the percentage of total utilization goes down. I don't like to get a 4010 above 70%, especially if there will be future changes to the design. Therefor, I would recommend keeping a 4013 below 65%. This assumes that you are trying to run it fairly fast, other wise any route with zero unroutes would be exceptable. In this case you could get by with more usage. It really depends upon how much work you want to do to make it fit and run fast enough. Tom Dillon DILLON ENGINEERING 2017 Continental Place Suite 5 Mount Vernon, WA 98273-5649 e-mail: tom@dilleng.wa.com Voice : (360) 424-3794 FAX : (360) 424-5894Article: 1685
In article <40nea4$gkk@neptunus.pi.net> albo@pi.net (Alfred Bos) writes: >From: albo@pi.net (Alfred Bos) >Subject: Need information on MACH,FLEXlogix,ISPlsi >Date: Mon, 14 Aug 1995 12:08:29 GMT >Who can tell me where I can find information about INTEL/ALTERA's >FLEXlogix, AMD's MACH and Lattice's ISPlsi. >Free sotfware or text files or whatever. >Greetings, > Alfred Bos (albo@pi.net) Check these sites : www.actel.com www.amd.com www.altera.com you can find software on these FTP sites : www.altera.com/pub nic.funet.fi/pub/cae ftp.cs.indiana.edu/pub/goo/PLD good luck Gerd.Article: 1686
Martin Curran-Gray (marting@hpqt0219.sqf.hp.com) wrote: : Nick Gent (nickg@hpqt0220.sqf.hp.com) wrote: : : I'll try again - my last posting got chopped in half (why?)... : : John Forrest (jf@ap.co.umist.ac.uk) wrote: : : : Does anyone know the format of timespecs in Xilinx XNF v5. I want to : : : include : : : some in a handwritten xnf file. : : : Even an example would help. : : From a .xnf file generated from a Mentor schematic with TIMESPEC and : : TIMEGROUP properties: : Nick appears to be having a bit of trouble here! : I'll have a go! : From a .xnf file generated from a Mentor schematic with TIMESPEC and : TIMEGROUP properties: This is rapidly becoming a farce. John, I've mailed you the file that was meant to be appended to these messages - handle with care :-) NickArticle: 1687
In article <40g0t7$oo3@newsgate.sps.mot.com>
rxjf20@email.sps.mot.com "Doug Shade" writes:
"In article <40d39r$5hk@mksrv1.dseg.ti.com>
"John.Obenauf%aeup@msg.ti.com (John Obenauf) writes:
"
"> Does anyone know of who makes alternative devices to Xilinx's PROMs?
"> Specifically interested in the 1765 deivce.
"
"Microchip sells 37LV65 and 37LV128 (64K & 128k, 8 pin)
"Motorla sells MPA1765 and MPA17128 (64K & 128k, 8 pin)
"
"Support on Logical Devices, System General and DATA I/O programmers
"will be available next releases (or sooner on BBS services).
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
i.e. "is not available"
These (and the Xilinx, AT&T and Atmel devices) are supported on the
BP Microsystems range of programmers *right now*. :-)
--
David Pashley
Article: 1688
work, damn you
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Os - andrew.ostler@raytech.co.uk
Visit http://194.72.60.96/www/os/ for music, graphics and recipes
-----------------------------------------------------------------
Article: 1689
In Article <40pceq$r1r@hustle.rahul.net>
"Bond , James" <bond@rahul.net> writes:
>
>
>>
>> In article <08-08-1995.66392@dilleng> Tom Dillon, tom@dilleng.wa.com
>> writes:
>> >>I'm a fairly new user of Xilinx FPGAs.
>> >>I'm having a few problems with my current design using a Xilinx xc4013
>> >>FPGA. With only around 84% CLB utlilzation and under 40% flip-flop
>> >>utilization, the XACT software is crashing on routing. It always ends up
>> >>with 70 unroutes.
>> >>
>> >>I'm sure I'm not pushing it to more than available routing resources when
>> >>the CLB utilization is not filled.
CLB utilization has very little correlation to the available routing resources.
Much more important is the number of signals connected at each CLB! Based on
the information here, I think you **are** exceeding the available routing
resources. Furthermore, I suspect that even if you handrouted the current
design, you'd run into the same problem. I've seen designs with close to 100%
CLB utilization route flawlessly and I've seen designs with as low as 50%
absolutely choke. Please see item 7 below, which I added to Mr. Bond's list of
helpful hints.
[snip]
>Here are a few suggestions,
>
>1. The IO placement is something user can control easily using
> the constraints (cst) file. Try a few different IO placements
> which makes sense to your design
Better yet, let the tool pick the I/O if at all possible. I realize that in
most cases the PWB is the long pole in the schedule (I rarely see cases where
the I/O assignment is not needed before the FPGA design is complete). When you
need to have a final I/O assignment before the design is done, please use some
sense in assigning the pins. Generally speaking, you are better off spreading
related I/O out rather than clumping it at one place. Think about how the
design would get laid out in the part before you assign I/O. Remember, the
routing to random pin assignments is much easier on the PWB than it is in the
FPGA!
>
[snip]
>4. If you are using higher placer efforts, you might also want
> to try different seeds. I guess the seeds does matter for
> placer efforts > 4
>
The tool uses a new seed everytime it runs unless you specify a seed in the
cst file. You can set the tool up to run multiple times (like if you leave it
to route overnight) using different seeds. If you are getting the same
unrouted nets each time regardless of your seed, this won't help. See item 7
below. As far as manually assigning seeds, I see no value at all unless you
are trying to duplicate an earlier route and you know the seed that was used.
There is no way to predict whether a given seed is a good one or a bad one.
The seed affects the placer regardless of the placer effort. It essentially
gives a starting point for the placement algorithm. The results on two
consecutive runs using the same design and a different seed can be markedly
different at any placer effort level.
[snip]
7. By the ratio of CLBs to flops, and the relatively low density of your
design, my guess is that you have some pretty wide combinatorial functions.
Try breaking them up a bit, either by pipelining or by using maps to force
less inputs to each CLB. If you are trying to use most of the inputs to
several CLBs in the same neighborhood the routing quickly gets congested.
My guess is that this is what you are running into, especially if you get
many of the same nets unrouted each time. Also, if you have too many wide
fanout signals leading into a small amount of logic, you will use up the
long lines. Keep in mind the number of long lines available in each
row/column, and remember some are used by global signals. This again gets
back to tailoring your design to the architecture.
8. If your design is done with the CLB architecture in mind, then you should
have a good feel as to how you would lay out the CLBs. Try floorplanning
the areas where you are having problems. As good as the PPR may be at
doing the place and route, the human mind is still at least 10 x better.
-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930 FAX 401/884-7950
email randraka@ids.net
The Andraka Consulting Group is a digital hardware design firm specializing in
obtaining the maximum performance from FPGAs. Services include complete
design, development, simulation, and integration of these devices and the
surrounding circuits. We also evaluate, troubleshoot, and improve existing
designs. Please call or write for a free brochure.
Article: 1690
With considerable effort, my logic design routed in isp1048C. It uses nearly
all of the I/O pins. I completed the route by locking my three bidir. busses
to likely good pins of three different megablocks. (The design would not
route using only GROUP properties; locking some pins was essential...)
Without changing anything in the AHDL design file, this design will not
re-route with acceptable delay if I add the "-y pins_file" option to lock
all pins to match the earlier run. The longest path increases from 2 GLB
levels to 3, which is not acceptable.
Has anyone hacked this kind of problem with Lattice's fitter before?
I'd like to try a tool that extracts the GLB grouping from the successful
run and generates GROUP properties to guide the new run having locked pins.
Pointers to experimental Lattice-fitting tools would be appreciated.
--
----------------------------------------------------------------------------
Greg Waters waters@npss.enet.dec.com
High-Performance Networks Engineering
Digital Equip. Corp., Littleton, MA (508) 486-5854
Article: 1691Hello, My current FPGA application uses Actel FPGAs with small external look- up tables using about 2kbits to 8kbits of RAM. I am now considering options for my second generation and am looking at FPGA families with on-board RAM. As far as I can determine, my options are AT&T and Xilinx, whose PLCs and CLBs can be used as small RAM blocks. I have also read that Altera is cooking up a new family with embedded diffused SRAM blocks. Does anyone know if this new family is out? As anyone used it? Does anybody have any experiences to share regarding the use of RAM in Xilinx and AT&T? Any problems with routability, timing? Does it impact on percentage utilization in the logic portion of the design? How do the tools handle RAM? Any input welcome.... Thanks Catherine Gyselinck ---------------------------- MPB Technologies | Speak softly but carry | gcat@dorval.mpbtech.qc.ca | a +6 two-handed sword | tel: (514) 683-1490 ---------------------------- fax: (514) 683-1727Article: 1692
One strategy that often works well is the following: 1) Pre-place the obvious pins, TBUFs, and logic blocks - those that are on regular busses, arrays, counters, wide registers, etc. Also, place critical random logic in approximate locations. This first step is kind of tedious and can take a couple of hours. (I use AWK filters to scan the LCA or NCD files and create a skeleton placement file.) 2) Dump the design into the Place-and-route program (APR,PPR, or NeoCad PAR) with all of the pre-placed blocks locked in place and allow the automatic placer put the rest in. 3) Unlock all of the blocks (and pins) and dump it into the place-n-router again. This time, it starts with the whole design placed fairly well, but has the freedom to move all of the blocks around. This turns out to do much better than just dumping a completely randomly-placed design into the PAR, and is much quicker than doing a thorough hand placement.Article: 1693
Hello. Does anyone can help find and Email address where i can place some doubts to Xilinx about Viewlogic version of their development system ? Emanuel FontesArticle: 1694
Try hotline@xilinx.com
--
**********************************************************
Jorgen Gade
ABB Industrial Systems AB
jgade@hw.seisy.abb.se
**********************************************************
Article: 1695In article <1995Aug16.203135.24706@super.org> <GCAT@dorval.mpbtech.qc.ca> writes: >From: <GCAT@dorval.mpbtech.qc.ca> >Subject: FPGAs with embedded RAM >Date: Wed, 16 Aug 1995 20:31:35 GMT >Hello, >My current FPGA application uses Actel FPGAs with small external look- >up tables using about 2kbits to 8kbits of RAM. I am now considering >options for my second generation and am looking at FPGA families with >on-board RAM. >As far as I can determine, my options are AT&T and Xilinx, whose >PLCs and CLBs can be used as small RAM blocks. I have also read that >Altera is cooking up a new family with embedded diffused SRAM blocks. >Does anyone know if this new family is out? As anyone used it? >Does anybody have any experiences to share regarding the use of RAM >in Xilinx and AT&T? Any problems with routability, timing? Does >it impact on percentage utilization in the logic portion of the >design? How do the tools handle RAM? >Any input welcome.... Thanks >Catherine Gyselinck ---------------------------- >MPB Technologies | Speak softly but carry | >gcat@dorval.mpbtech.qc.ca | a +6 two-handed sword | >tel: (514) 683-1490 ---------------------------- >fax: (514) 683-1727 Actel has a new FPGA family, 3200DX - System Logic Integrator Family. These devices have up to 40K gates, 4Kbits of dual port SRAM, fast decode circuitry, JTAG boundary scan interface, and up to 292 user programmable I/O pins. The family is brand new. The first available parts are the A3265DX and A32140DX. Both do not have SRAM modules. I have not used this family yet. Check with Actel for details about their 3200DX FPGA family. Paul T. Shultz <shultz@clark.net>Article: 1696
Xilinx has recently added some dual port and synchronous features to RAM implementation since I used the feature last. The last time I used this feature I was able to put a small (48bitsX8) RAM block in a 4003 without too much difficulty. The main issues were the differences in routing delays for the Write Enable line between all of the CLB's I was using for the RAM (12). As usual with FPGAs I found I could get the best performance by understanding how best to place CLBs, and lock regular sections (registers, counters, RAMs) in place and let the PPR stuff place and route the miscellanious logic. Also check out the Altera, and Actel WWW sites; they have both recently announced parts with embedded RAM blocks: http://www.altera.com/ http://www.actel.com/ I dont know when these parts will be available, but both offer more RAM thatn the Xilinx parts. ------------------------------ Steve Holmes sherlock@bnr.caArticle: 1697
hello, we are designing a latched crossbar switch for digital video, which is part of an image processor board. it's general profile is a device very high in IO - around 200 pins - but relatively low in core logic. the conventional FPGAs that we know of are limited in user IO, and when they have enough user IO (>200) they are the biggest and most expensive devices. anyone know of a solution for this problem - some high pinout device which is not the biggest and most expensive in it's family? thanks odedArticle: 1698
><GCAT@dorval.mpbtech.qc.ca> wrote: > >As far as I can determine, my options are AT&T and Xilinx, whose >PLCs and CLBs can be used as small RAM blocks. I have also read that >Altera is cooking up a new family with embedded diffused SRAM blocks. > >Does anyone know if this new family is out? As anyone used it? >> >Any input welcome.... Thanks > you might like to check out the altera home page for more info on the embedded ram family (flex10k). the address is www.altera.com -- stephen smith (sjsmith@aimnet.com)Article: 1699
In article <1995Aug16.203135.24706@super.org>, <GCAT@dorval.mpbtech.qc.ca> wrote: >Hello, > >My current FPGA application uses Actel FPGAs with small external look- >up tables using about 2kbits to 8kbits of RAM. I am now considering >options for my second generation and am looking at FPGA families with >on-board RAM. > >As far as I can determine, my options are AT&T and Xilinx, whose >PLCs and CLBs can be used as small RAM blocks. I have also read that >Altera is cooking up a new family with embedded diffused SRAM blocks. > >Does anyone know if this new family is out? As anyone used it? > >Does anybody have any experiences to share regarding the use of RAM >in Xilinx and AT&T? Any problems with routability, timing? Does >it impact on percentage utilization in the logic portion of the >design? How do the tools handle RAM? > >Any input welcome.... Thanks > > >Catherine Gyselinck ---------------------------- >MPB Technologies | Speak softly but carry | >gcat@dorval.mpbtech.qc.ca | a +6 two-handed sword | Catherine, check out Actel's new 3200DX family. It has dual port sram, fast wide decode and tons of logic modules--JTAG is also supported. Nelson Soria nsoria@joule.calpoly.edu
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