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I am synthesizing VHDL using the Compass Asic Synthesizer, and then using the ASYL FPGA Optimiser to target my XC3000L series device. I cannot get ASYL to generate CLB flip-flops that are clocked on the falling edge of the global clock. I have tried re-writting my VHDL many different ways, but cannot get the correct xnf out of ASYL. The clock should be inverted in the CLB, but everything I try results in a CLB inverter inserted into the clock net, which precludes use of the direct clock input TCLKIN. Has anyone a fix, suggestions etc., I have resorted to editing the xnf file, which is not funny.Article: 1251
Salutations: Paul Walker <paul@walker.demon.co.uk> writes: > Altera's publicity also claims to offer something on PCI, but I have so far > had no joy in extracting any info. Altera has a "PCI design kit" available which includes a disk containing macrofunctions for the FLEX8000, MAX7000, MAX9000 and FlashLogic families of parts. There are macros for masters and targets optimized for each family. All four families have members which are are certified as compliant by PCI SIG. The macros are written in Altera AHDL, except for FlashLogic which are done in the PALASM-like language for PLDShell. The macros have a generic "back-end", but hook right up to the PCI bus. The macros themselves are available on the BBS (408)954-0104, under the name "pci_20a.exe". Other PCI related info is App Note 41, PCI Bus Applications and App Brief 140, PCI Compliance. You can request all of this info, including the the design kit by faxing a request to (408)894-7144. Hope that helps! Regards, Bill HarrisArticle: 1252
I'll have one more *simple* assignment given out around May 24th, and due May 31st. This assignment will cover the discussion of the exam done today, tail-recursion optimization (see posting in the class newsgroup), and a bit of denotational semantics (to be covered 24th and 31st. I'll keep this assignment as simple as I can to allow you maximum time for projects. Speaking about projects, please feel free to see me ANYTIME for discussions. If you have preferred times, plz mail them to me and I will put those times into my calendar. Clint will be recording the midterm scores some time today, and will make the exams available thru the CS office "soon" (ask Clint for details). Cheers, GaneshArticle: 1253
Does anyone know of a web site , or failing that a good book that can cover the essentials of CUPL. For programming PLD's Anything on ABEL (ABLE ??) would be good too. I am going to purchase/order some books this weekend. Thanks Clive B.Article: 1254
Ganesh C. Gopalakrishnan (ganesh@bliss.cs.utah.edu) wrote: : I'll have one more *simple* assignment given out around May 24th, and due ... stuff deleted... : Cheers, : Ganesh TERRIBLY SORRY! I accidentally posted a message intended for my class newsgroup into comp.arch.fpga. I perhaps accidentally selected comp.arch.fpga while in my newsreader "tin" and it took me a while to realize to my chagrin that the posting had gone astray. Again, please accept my apologies. Sincerely, GaneshArticle: 1255
SPECIAL! SPECIAL Price on 1/2 day seminars $25 each SPECIAL
Introduction to VHDL: 8:30-12:00, Wed, June 21, 1995
Huntsville Marriott, #5 Tranquility Base, Huntsville, Alabama
Object Based Top Down (OBTD) ASIC and FPGA development:
1:00-4:30, Wed, June 21, 1995
Huntsville Marriott, #5 Tranquility Base, Huntsville, Alabama
Reserve your space by telephone or e-mail
Charles F. Shelor cfshelor@acm.org
SHELOR ENGINEERING VHDL Training, Consulting, Models
3308 Hollow Creek Rd (817) 467-9367
Arlington, TX 76017-5346
Introduction to VHDL
This introductory seminar addresses the use of VHDL in the
development of ASICs, FPGAs, and CPLDs. A short history of
the language provides the background for why it is the best
language, from a life cycle and full system perspective, for
the development of hardware devices. The features of VHDL are
explained by the use of a =D2real world=D3 example. The course is
intended to provide program managers, engineering managers, and
practicing engineers sufficient information to determine if VHDL
would be appropriate for their application. It will show some
of the power of VHDL and will remove the mystique surrounding
VHDL. It will not create VHDL programmers nor will it be able
to discuss every minute detail of the language. The use of VHDL
in system modeling, design verification, and logic synthesis will
be emphasized. The benefits and pitfalls of synthesis will be
discussed. Sources for more information on VHDL will be provided.
Object Based Top Down ASIC Development
This tutorial describes a top down development methodology where
the partitioning process is guided by object based considerations.
The methodology emphasizes designing for reuse as the greatest
engineering productivity enhancement in current technology. The
methodology also stresses routing considerations since routing is
very important to sub-micron ASICs and to many FPGAs. VHDL
beginners can benefit from the tutorial by seeing a non-trivial
VHDL implementation. VHDL experts can benefit from the tutorial
by learning the OBTD methodology from requirements through
implementation. The tutorial uses the VIUF 1994 Design Contest
problem, an airport baggage handling system, as the design example.
Outline:
Introduction to Object Terminology
Application of Object Based Techniques to ASIC and FPGA Development
Problem Requirements
Top Level Design Considerations
Intermediate Design Constraints
Example Implementation
Planning and Scheduling with OBTD methodology
About the author:
Charles Shelor is an independent VHDL methodology consultant and
trainer. He has twenty years experience in the design of high
performance embedded systems. He was the winner in the user
category of the VIUF 1994 Design Contest. He has presented over
a dozen papers at various conferences, a design feature in
Electronic Design News, and is the author of the VHDL Designer
column in the =D2VHDL Times=D3. He has a BSEE, MSEE, and is pursuing
a PhD in Computer Engineering. He has a patent in multiple
processor computer architectures.
Charles F. Shelor cfshelor@acm.org
SHELOR ENGINEERING VHDL Training, Consulting, Models
3308 Hollow Creek Rd (817) 467-9367
Arlington, TX 76017-5346
Article: 1256Why don't you just phone a distributor, they will send you FREE OF CHARGE a box containing the manual, disk and every think you need. Alas, the current generation expects instant gratification. Of course, we've been waiting for *our* copy for two weeks now... -- Roger Williams Coelacanth Engineering | Numeric stability is probably not all Middleborough, Mass | that important when you're guessing...Article: 1257
In article <12146@eagle.ukc.ac.uk> sjba@ukc.ac.uk (S.J.B.Acock) writes: > >I would like to know if anyone has a simple Xilinx XC4000 series fpga download >program which would allow me to send a raw bit file or exormax file via a PC >parallel port (lpt1) to a Xilinx device working in slave serial mode. >I have XACT software installed on a PC and a workstation allowing downloading >from the XDE, but a simple DOS based downloader for the PC would be preferable. > >Thanks in advance. > >Steven Acock, >Electronic Laboratories, >University of Kent, >Kent, >England CT2 7NT >sjba@ukc.ac.uk > The program you want is on your disk :-) and is called XCHECKER. Assuming your path points at you \XACT directory (among other things) the following command should do the trick for you: c:\>xchecker project.rbt It should respond that it has found a parallel-91 cable connected to LPT1. My version reports that it is XCHECKER version 5.1.0 Hope this is what you needed, All the best, Philip Freidin.Article: 1258
Wasted bandwidth follows. It's late and I can't help myself. (hit 'n' now unless you are really bored) In article <3pr4f9$bdk@magus.cs.utah.edu> ganesh@bliss.cs.utah.edu (Ganesh C. Gopalakrishnan) writes: >I'll have one more *simple* assignment given out around May 24th, and due >May 31st. This assignment will cover the discussion of the exam done today, >tail-recursion optimization (see posting in the class newsgroup), and a bit of >denotational semantics (to be covered 24th and 31st. I'll keep this assignment >as simple as I can to allow you maximum time for projects. I certainly would like maximum time for my projects, and I put in a requisition about 3 years ago for some 38 hour days, and some 18 day weeks. They haven't turned up yet. One of the problems of c-a-fpga is that its original charter seems to have been forgotten, and almost everything seems to be off topic (including my posts). The above post seems to be slightly more off topic than usual, but what do I know. On the otherhand, this news group has become an excellent clearing house for all FPGA related stuff and so I continue to be gratefull for its existence. For reference, the group alt.comp.hardware.homebuilt now contains 50% messages proposing new names for the group so that all the PC assemblers will stop anoying the 'real' users of the group, those that build CPUs from the ground up (about 2% of the readership). The other 50% are questions about overclocking their pentium chips, and how to plug SCSI drives into IDE controllers :-) > >Speaking about projects, please feel free to see me ANYTIME for discussions. >If you have preferred times, plz mail them to me and I will put those times >into my calendar. > >Clint will be recording the midterm scores some time today, and will make >the exams available thru the CS office "soon" (ask Clint for details). > >Cheers, > >Ganesh > > AND ALL THE BEST FROM ME TOO... Philip FreidinArticle: 1259
If you want to use only the falling edge of the clock, may be you can first invert the input clock, and then instantiate ACLK or GCLK buffer in your VHDL code, and supply the output of that buffer to all clock inputs in your design. If you are using both edges of the same clock, then you can try using both buffers, one for driving rising edge, one for driving falling edge. Please let me know if it helps. Note:I am using Synopsys XSI interface, and I never needed to do such a thing. When all the FF clocks in the design are drived from one source, the XSI automatically uses a global clock buffer and does not insert an inverter for falling edge. Yuce BESER -- (quess what? not speaking for my company) --Article: 1260
I have a customer that is using Altera for two designs to implement the PCI Bus. There is a specific design kit that is available from Altera that has detailed information, including the macrofunctions needed to implement the design. There are also application notes available. Please call your local Altera Rep or you may call the Altera hotline 800 800-EPLD to get this information.Article: 1261
In article <801143337snz@walker.demon.co.uk> Paul Walker, paul@walker.demon.co.uk writes: >In article <3pij15$m3t@newsbf02.news.aol.com> > billaltfae@aol.com "Billaltfae" writes: >[snipped] >>... Intel developed PLDShell tool. It is still free and is >>available though Altera sales reps and >>distributors. The latest version is 4.01. > >Not sure it is any different from V4.01, but I was using V3.0 and >suffering from a couple of bugs, and received V5.0 today. > >Although the older versions have a few bugs, most of the bugs are >livable with. Overall, the combination of PLDshell with a >download cable and reloadable devices, all for not much more >than $100, is very good value. V4 was a major improvement over v3, and made it much easier to use some of the more esoteric features - such as using both pin and internal feedbacks from macrocells. Does anyone know anything about v5? JohnArticle: 1262
> Are there any multi chip partitioners for XC4000 devices which can > be used to generate multiple XNF files NeoCAD, which is now Xilinx, has been selling a multi chip partitioner, called Prism, for a couple of years now. It works on XC3000 series and XC4000 series devices. It does not create multiple XNF files. Instead it works on the physical database which has already been mapped. It is also timing driven. Let me know if you want more details. Steve Lass Technical Marketing Manager Xilinx, Boulder lass@neocad.com (303)442-9121 x104Article: 1263
I just received my copy after waiting for 2 weeks. I installed it couple days ago and found that an executable, pldv.exe, was missing. This pldv.exe is probably for plotting out simulation results. I tried to reinstall the program carefully but this pldv.exe was still missing. Does anyone encounter similar problem? Or it is just something wrong with my copy. +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Eric Ko Argonne National Laboratory kko@phebos.aps.anl.gov 9700 S. Cass Ave. Work: (708) 252-7351 Bldg. 362 Rm. C381 Argonne, IL 60439 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++Article: 1264
In article <MSNOOK.95May22200143@sun61.armltd.co.uk>
msnook@armltd.co.uk "Mark Snook" writes:
"I am synthesizing VHDL using the Compass Asic Synthesizer, and then
"using the ASYL FPGA Optimiser to target my XC3000L series device. I
"cannot get ASYL to generate CLB flip-flops that are clocked on the
"falling edge of the global clock.
"
ASYL+ vn 3.2 works fine with falling edge clocks on XC3000L. I
assume that what you have there is an old Compass-OEMed version.
--
David Pashley
Article: 1265A few weeks ago I've seen a posting about 'altera vs xilinx' but i just missed that one. Could the sender repost that one ? thanx in advanceArticle: 1266
In article <3pr0pr$dlb@newsbf02.news.aol.com>
billaltfae@aol.com "Billaltfae" writes:
>Altera has a "PCI design kit" available
[details snipped]
> You can request all of
>this info, including the the design kit by faxing a request to
>(408)894-7144.
>
>Hope that helps!
Yes it does, except that the phone number you give is the voicemail
of a lady in the literature depatment at Altera, not a fax number.
--
Paul Walker 4Links for technical help
+44 1908 566253 P O Box 816, Two Mile Ash
paul@walker.demon.co.uk Milton Keynes MK8 8NS, UK
Article: 1267> - What company bought NeoCAD (Xilinx, AT&T) ? Xilinx > - Since NeoCAD was the only design system for FPGAs from > Motorola, what is happening with the support for these > devices, now that NeoCAD is not independent anymore. This is currently being discussed. I think Pilkington, who licensed the architecture to Motorola, also has some type of software for Motorola devices. > - Will NeoCAD eventually disappear? NeoCAD is now known as Xilinx, Boulder. We will be producing the core software tools for Xilinx FPGAs. Steve (These are my views, not those of my employer.)Article: 1268
>Altera has a "PCI design kit" available
[details snipped]
> You can request all of
>this info, including the the design kit by faxing a request to
>(408)894-7144.
Boy, who would have thought that mirroring the BBS to the FTP site
would turn out to be such a big technical challenge? ;-)
--
Roger Williams
Coelacanth Engineering | Numeric stability is probably not all
Middleborough, Mass | that important when you're guessing...
Article: 1269Hi all I'm trying to program an Altera/Intel Flex780 through the JTAG port and most times get an error message from PLDShell's PENGN program. I'm using version 3.5 on a PC. The error code is 7041 and sometimes 7045 and my documentation (from version 3.1) only has the codes up to 7037. Anyone have a list of error codes above 7037? Rob Christopher robc@appliedmicro.ns.ca Hardware Designer Applied Microelectronics Phone: (902)421-1250 1046 Barrington St. Fax: (902)429-9983 Halifax, N.S.Article: 1270
Paul Walker <paul@walker.demon.co.uk> wrote: >>Altera has a "PCI design kit" available [details snipped] >> You can request all of >>this info, including the the design kit by faxing a request to >>(408)894-7144. >> >>Hope that helps! >Yes it does, except that the phone number you give is the voicemail >of a lady in the literature depatment at Altera, not a fax number. OOPS. I'm getting old and going blind. Try (408)944-0953. Regards, Bill H.Article: 1271
Eric K. (Ka-shu) Ko (kko@aps.anl.gov) wrote: : I just received my copy after waiting for 2 weeks. I installed it couple days ago : and found that an executable, pldv.exe, was missing. This pldv.exe is probably for : plotting out simulation results. I tried to reinstall the program carefully but : this pldv.exe was still missing. Does anyone encounter similar problem? Or it is : just something wrong with my copy. I have had a similar problem. It would seem that Altera forgot to include that file in its distribution. What I did was to take the pldv.exe that I had gotten from the Intel distribution on the assumption that Altera did not really change any of the internals of the programs. So far everything works the way that it should. Heinz SeltmannArticle: 1272
Hi guys I am trying to program xilinx prom XC1736 but it looks like I lost the XC1736.hex file. Can somebody provide me a copy of this file please. (ftp would be fine) Thanks in advance. -- Oscar Calvo | calvo@venus.fisica.unlp.edu.ar L.E.I.C.I. | Tel. (54-21)259306 Facultad de Ingenieria | Fax. (54-21)250804 Departamento de Electrotecnia Universidad Nacional de La Plata Calle 48 y 116 (1900) La Plata, ArgentinaArticle: 1273
John Forrest <jf@ap.co.umist.ac.uk> writes: >V4 was a major improvement over v3, and made it much easier to use some >of the more esoteric features - such as using both pin and internal >feedbacks from macrocells. Does anyone know anything about v5? Altera is rolling the development support for the FlexLogic (now known as FlashLogic) into their MAX+Plus II toolset. I doubt that there are any plans for continued development of the PLDShell tool. The MAX+Plus II tool is more complete by orders of magnitude over PLDShell. The word is that FlashLogic support will be available in version 6.0 of MAX+plus II which is slated for release in 95Q3. Regards, Bill H.Article: 1274
there seems to be a lot of "is anyone using fpgas to do a pci interface" type of question and where can they get help. altera does have these type of macrofunctions (PCI, ATM, ...) but currently they are only available from the bbs. these macrofunctions will be mirrored to the ftp site in the next few weeks. be patient, in the meantime here are some contact numbers: phone: (800) 800-epld or (408) 894-7000 fax: (408) 954-0348 bbs (8,n,1): (408) 954-0104 literature: (408) 894-7144 customer service: (800) sos-epld automated literature fax server: (800) 5-altera www: http://www.altera.com -- stephen smith sjsmith@altera.com
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