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I needed to do the same thing recently, with the same parts and about the same utilization 60-65% max. I didn't have any real problems with routing. Although I made some educated guesses about where to lock pins at: - I had some counter chains that needed pin access, and I assigned pins so that the counter chan could be kept in one row, and fast track connections cound be made to the counters. Look at the Floorplanner in the MAXPLUS2 tools to get an idea of how the Altera parts like to do their placement. As my design got more dense, with functionality additions I found that I could no longer keep carry chains together on long counters, I had to disable the Altera built-in carry logic on my slower counters. Steve Holmes sherlock@bnr.caArticle: 1551
I've been using them for a few months now. I've designed and routed three chips, but haven't actually built any hardware yet. I used the NeoCad software, so was able to try my circuits in both Orca and Xilinx X4000 - my conclusion is that ORCA beats Xilinx on speed, price, pin count, and usability. (My rule of thumb is that the ORCA PFU is equivalent to 1.5 to 2.5 X4000 CLBs). Orca is well suited for data path and arithmetic functions. I was able to implement a circuit with sixteen 24 bit wide FIFO's with 20ns cycle times on a single 2C12 chip ($300). This circuit was impossible to do in Xilinx because of the speed and because of the limited number of internal tri-state busses. Orca has 8 tristate drivers per PFU which can drive horizontal and vertical long lines. X4000 has two TBUFs per CLB that can drive horizontal lines only. (Also note here the effect of granularity - a 24-bit wide RAM takes 6 PFUs, but 12 CLBs. Routing the address and control lines to 12 destinations burns a lot more routing resources than routing to 6 closely packed PFUs.) Another feature that seems to give the Orca a big advantage is the multiplexers at the register inputs. At first, this doesn't seem all that useful, but it turns out that about 30% of my blocks use it. So, for example, I can implement a 4-bit wide, 3-to-1 registered multiplexer in a single PFU. It would take 4 CLB's to do the same function. The new X4000E chips look like they'll be able to compete with ORCA in speed, and they have a few other selling points such as synchronous RAM. Xilinx also has a larger user community, a better software base, and other families of chips, which probably makes them a better choice if you can only buy one development system. (Even though it pains me to say so, since Xilinx removed the NeoCad option by buying the NeoCad company and eliminating its ORCA support).Article: 1552
If you have lots of margin in your design and you tell the fitter not to keep your LAB assignment, then I don't think there will be a problem even at 80% utilization. You can also ask the compiler to "try harder" just in case. If you have speed critical blocks, you can assign them to cliques with the additional constrain of "the best possible", then even long counter will be kept on adjacent LABs on the same row. I have a 14 bit up counter built from A_8COUNT running at 84.24MHz using the 81188A-3. After the counter was assigned to a clique, I never had any timing problem from re-compile. Good Luck in your design, Hing-FaiArticle: 1553
>> From musall@fstop.csc.ti.com (Ed Musall) >> Newsgroups: comp.arch.fpga >> Subject: Flex 8000: Locking down pins >> Date: 12 Jul 1995 16:08:36 GMT >> I am presently working on a couple of Altera FLEX 8000 designs targeted for >> 8820As. I have captured the designs but I haven't verified them yet. >> One of the designs utilizes 50% and the other is at 60%. I was hoping >> to go ahead and lock down the pins and procede with the board layout but >> I am apprehensive about the Fitters ability to succede when I make changes >> with the pins lock down. Please comment on my situation if you >> have experience with the FLEX 8000 devices. What is your I/O utilization? Try to be conservative and keep it below 70% ,if possible. With 50/60 internal utilization and 70-80% I/O, you are probably ok. Anything above the Altera recommended 80% I/0 util should be considered the final route at that pin assignment. J.P.Article: 1554
TAKE PART IN A LIVE, INTERACTIVE BROADCAST ON ESDA If you're an electronic designer interested in Electronic System Design Automation (ESDA), or if you are evaluating this technology, please consider attending an interactive broadcast titled, "ESDA: Real Users, Real Tools." It's sponsored by Mentor Graphics and Hewlett-Packard. The broadcast will feature three users discussing how they employ ESDA and what results they are achieving. In addition to learning from their experiences, you will have an opportunity to ask them questions. You can attend this broadcast for FREE at a Hewlett-Packard sales office near you. The program airs Tuesday, July 25, 9 a.m. to 10:30 a.m. PDT (noon to 1:30 p.m. EDT). TO RESERVE YOUR SPOT (because seating is limited), please call 1-800-274-0924. Or, simply reply to this message. Please include your e-mail address and your telephone number. This is your chance to discover first hand what ESDA can really do for you. ** ESDA users share their experiences ** Ask them questions about ESDA. ** It's free. Just reply to this message or call 1-800-274-0924 ** Tuesday, July 25, 9 a.m. PDT; noon EDT at an HP sales office near you ** Co-sponsored by Mentor Graphics and Hewlett PackardArticle: 1555
I am looking for informations about the new XILINX XC6200-FPGA.
All I have is: some copies of foils of the
"Programmable Logic Breakthrough '95, Technical Conference and
Seminar Series" with these infos:
- reconfiguarable coprocessor
- SRAM-based
- ultra fast reconfiguration, full or partial
- 8, 16, 32 bit processor interface
- 60k -100k Gates
- efficient, symmetric architecture
- availability : 1996
Are there any more informations available? What kind of CLBs or
configurable processor-kernel or other structures are used?
Markus Wannemacher
-------------------------------------------------------------------------------
@@ @@ Markus Wannemacher
@@@ @@@ @@@@@@ @ @ FernUniversit"at Hagen
@@@@ @@@@ @ @@@ @ @ Faculty of Electr. Engineering
@@@@ @@@@ @@@@ @@@@ @ @ @ @ Chair for Real-Time Systems
@@@ @@@@ @@@ @ @@@@@ @ @ D-58084 Hagen, Germany
@@@@@@@@@@@@ @ @ @ @ phone +49 2331 987 4547
@@@@@@@@@@ @ @@@ @@@@ fax: +49 2331 987 375
Internet: E-Mail: Markus.Wannemacher@FernUni-Hagen.De
WWW: html://www.fernuni-hagen.de/www2bonsai/IT/team/wm.html
--------------------------------------------------------------------------------
Article: 1556kugel@mp-sun6.informatik.uni-mannheim.de (Andreas Kugel) writes: >I compiled two xilinx xc3000 designs with synopsys. the chips >are connected together as master and slave. I'd like to have a >common testbench for both designs. >in the testbench I instantiate two components MASTER and SLAVE >and configure both components. >vhdldbx cannot load both sdf files, generates lots of errors >with the options: >-sdf master_vss.sdf -sdf_top /testbench/MASTER -sdf slave_vss.sdf -sdf_top /testbench/SLAVE >is this the wrong syntax ? (it works with ONE component that way!) >all hint welcome >- >-------------------------------------------------------- >Andreas Kugel >Chair of Computer Science V Phone:(49)621-292-5755 >University of Mannheim Fax:(49)621-292-5756 >A5 >D-68131 Mannheim >Germany >e-mail:kugel@mp-sun1.informatik.uni-mannheim.de >-------------------------------------------------------- Andreas, try out to place the option -sdf_top before the corresponding -sdf. Hope this helps, Martin. -- Martin Radetzki, University of Oldenburg email: martin.radetzki@informatik.uni-oldenburg.deArticle: 1557
This is a multi-part message in MIME format. ---------------------------------103177974118310988981205339619 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii We don't have a license to run ActGen! wrt VHDL, I can do it with lots of individual signals - any ideas on how to do it with vectors? Geoff Rubner. ---------------------------------103177974118310988981205339619 Content-Transfer-Encoding: 7bit Content-Type: text/plainArticle: 1558
The xilinx 6200 series is a successor of the ALOGOTRONIX fpga chips. Xilinx announced to put them into market until end of this year (whatever this means) They are not available right now. --- -------------------------------------------------------- Andreas Kugel Chair of Computer Science V Phone:(49)621-292-5755 University of Mannheim Fax:(49)621-292-5756 A5 D-68131 Mannheim Germany e-mail:kugel@mp-sun1.informatik.uni-mannheim.de --------------------------------------------------------Article: 1559
Greetings, I have a system where I have to program a ispLSI2032 FPGA by software. I have got some sources for that from our local Lattice representative; but the problem is, that these sources are for the earlier ispLSI1000 series. And of course I found it out near the end of the project! So I ask: Have you got newer program sources to program the 2032 in-circuit with the five-wire programming interface, that you are willing to share? If you do, please mail me or reply here. Thank you for your time, JouniArticle: 1560
"SURFACE MOUNT ASSEMBLY AND FINE PITCH" 2-day Short Course August 8-9, 1995 at the San Francisco Airport, Burlingame, California, USA This course gives you the details you need to understand the terminology and the many options of SMT/FPT and to achieve a successful execution of the design and manufacturing of an SMT/FPT printed wiring assembly. TOPICS INCLUDE: Introduction; SMT/FPT Components; SMT Substrates; Types of SMT/FPT Assemblies; Design for Manufacturability; SMT Process Details; Typical Defects and Inspection; Rework/Repair; Starting and SMT Operation. LECTURER: CHARLES HUTCHINS, Ph.D., an independent consultant recognized worldwide for his experience in Surface Mount Technology. He was at Texas Instruments for 22 years as Engineering Manager, Quality Dept. Manager, and Product Manager. Most recently he was responsible for engineering management at TI's SMT Center where he worked with process engineering. Dr. Hutchins was author or co-author of more than 30 papers and a textbook on SMT and FPT. He was president of the SMTA for 1991-1992 and Vice President in 1989. He writes a monthly article on SMT manufacturing for Surface Mount Technology Magazine. COURSE FEE: $850 includings course materials, morning and afternoon refreshments and luncheon each day. For a DETAILED BROCHURE: reply with your complete POSTAL ADDRESS or FAX numberArticle: 1561
"SURFACE MOUNT ASSEMBLY AND FINE PITCH" 2-day Short Course August 8-9, 1995 at the San Francisco Airport, Burlingame, California, USA This course gives you the details you need to understand the terminology and the many options of SMT/FPT and to achieve a successful execution of the design and manufacturing of an SMT/FPT printed wiring assembly. TOPICS INCLUDE: Introduction; SMT/FPT Components; SMT Substrates; Types of SMT/FPT Assemblies; Design for Manufacturability; SMT Process Details; Typical Defects and Inspection; Rework/Repair; Starting and SMT Operation. LECTURER: CHARLES HUTCHINS, Ph.D., an independent consultant recognized worldwide for his experience in Surface Mount Technology. He was at Texas Instruments for 22 years as Engineering Manager, Quality Dept. Manager, and Product Manager. Most recently he was responsible for engineering management at TI's SMT Center where he worked with process engineering. Dr. Hutchins was author or co-author of more than 30 papers and a textbook on SMT and FPT. He was president of the SMTA for 1991-1992 and Vice President in 1989. He writes a monthly article on SMT manufacturing for Surface Mount Technology Magazine. COURSE FEE: $850 includings course materials, morning and afternoon refreshments and luncheon each day. For a DETAILED BROCHURE: reply with your complete POSTAL ADDRESS or FAX numberArticle: 1562
I am currently failing to synthesise some ROM cells into a Xilinx 4000 from VHDL. My problem is not being able to pass the INIT=******** attribute which determines the ROM contents. Has anyone sorted this out ?? At present I can pass a generic string through the component declaration and then parse the XNF file to convert to the correct syntax. There must be a better way. Ta, Andy Electronic Systems Group, University of Sheffield. U.K e.mail A.Shelley@sheff.ac.ukArticle: 1563
In article <3u3b9c$ir1@fnnews.fnal.gov>, Don Husby <husby@fnal.gov> wrote: > I've been using them for a few months now. I've designed and routed three >chips, but haven't actually built any hardware yet. I used the NeoCad >software, so was able to try my circuits in both Orca and Xilinx X4000 - my >conclusion is that ORCA beats Xilinx on speed, price, pin count, and >usability. (My rule of thumb is that the ORCA PFU is equivalent to 1.5 to >2.5 X4000 CLBs). > I obtained similar results when I compared Xilinx X4013 to ORCA 2c15. I got a 25% improvement in speed and a slight reduction in area. (Results will very widely depending on the type of design though.) //Celia ClauseArticle: 1564
Hi there! I"m looking for info on the wavelet video compression algorithm for my current research. I know it was develop in Texas A&M university by Dr.Yuen. I appreciate any pointers to papers published, any practical work on it or Dr. Yuen's e-mail. Thanks, Moshe Zalcberg Tel Aviv University IsraelArticle: 1565
Please add me to your mailing list. Thanks. Rod ZimmermanArticle: 1566
In article <GRCOOK.95Jul13104057@bhars10a.bnr.co.uk> grcook@bhars10a.bnr.co.uk (Gary Cook) writes: >Hi, > >Can anyone give me any feedback on how AT&T FPGAs compare with the other major >vendors, such as Xilinx and Altera ??? Email me direct if you want. > We use Xilinx where speed is not critical, but used AT&T Orca 1C03's for 2 designs which needed 32 Mhz state machines. We didn't think Xilinx 4000 series would be fast enough. Be careful about the design tools. When we started AT&T Synopsys libraries were not ready and we spent 3 months waiting for AT&T to get them working. We used Verilog input to Synopsys and Neocad for place/route. That is all working now, but if you use a different tool set, be sure it really works. DaveArticle: 1567
I apologize if this is not the right place to post my question. I am looking for benchmarks and public domain program for channel routing problem. Could anyone help me? Thank you in advance. Kai-Ping WangArticle: 1568
Hello, I'm programming a microcode-controlled processor in VHDL using Synopsys V3.3a and map it onto a Xilinx FPGA using XACT V5.0. This step works fine but recreation of VHDL code from the mapped and routed design with "xnf2vss" from XACT tools generates a VHDL code which cannot be compiled successfully with Synopsys. This abnormal behaviour comes into beeing when RAM16X1 or RAM31X1 instances are used. The Xilinx tool "xnf2vss" cannot make distinctions between RAM16X1 and RAM32X1 components! So far so good, and now my question: Does anybody detect the same error and if so does any workaround exist? I'm very grateful for any comment Hans JoergArticle: 1569
Please could you tell me how you add critical (fast/medium/non-critical) properties to NETS on ACTEL Designs on Mentor. The Action Logic System (ALS) manual is of no help at all. Thank you in advance.Article: 1570
In article <3udap2$sic@hippo.shef.ac.uk>, ajs@shef.ac.uk (Andrew Shelley) says:
>
>I am currently failing to synthesise some ROM cells into a Xilinx 4000 from VHDL.
>My problem is not being able to pass the INIT=******** attribute which determines
>the ROM contents. Has anyone sorted this out ??
>At present I can pass a generic string through the component declaration and then
>parse the XNF file to convert to the correct syntax. There must be a better way.
>
>Ta, Andy
>
>Electronic Systems Group,
>University of Sheffield.
>U.K
>e.mail A.Shelley@sheff.ac.uk
>
>
Hello Andy,
in my designs I use some ROM too, but I describe the complete ROM with VHDL statements
as an array with constant values. Look at the following code segment.
Bye
Hans Joerg
--==================================================================================
-- This VHDL code segment was automatically generated by MICASS (Version: 31.5.95)
--
-- Time: Mon Jul 17 22:20:46 1995
-- MicSig file: <prefctrl.sig>
-- MicAss file: <prefctrl.i>
--==================================================================================
-- synopsys translate_off
signal R_MicroInstr: std_logic_vector( 45 downto 0 ) :=
"0000000000000000000000111000000001111000000000";
alias MI_ArgInAck: std_logic is R_MicroInstr( 45 );
alias MI_Mem4_W: std_logic is R_MicroInstr( 44 );
alias MI_Mem4_R: std_logic is R_MicroInstr( 43 );
alias MI_Mem3_W: std_logic is R_MicroInstr( 42 );
alias MI_Mem3_R: std_logic is R_MicroInstr( 41 );
alias MI_Mem2_W: std_logic is R_MicroInstr( 40 );
alias MI_Mem2_R: std_logic is R_MicroInstr( 39 );
alias MI_Mem1_RW: std_logic is R_MicroInstr( 38 );
alias MI_Mem1_OE: std_logic is R_MicroInstr( 37 );
alias MI_Mem1_CE: std_logic is R_MicroInstr( 36 );
alias MI_Mem0_RW: std_logic is R_MicroInstr( 35 );
alias MI_Mem0_OE: std_logic is R_MicroInstr( 34 );
alias MI_Mem0_CE: std_logic is R_MicroInstr( 33 );
alias MI_NodeType: std_logic is R_MicroInstr( 32 );
alias MI_OutDisable: std_logic is R_MicroInstr( 31 );
alias MI_Ctrl1: std_logic is R_MicroInstr( 30 );
alias MI_Ctrl0: std_logic is R_MicroInstr( 29 );
alias MI_CtrlInfo_R: std_logic_vector( 1 downto 0 ) is R_MicroInstr( 28 downto 27 );
alias MI_CtrlInfo_En: std_logic is R_MicroInstr( 26 );
alias MI_BufferReg_En: std_logic is R_MicroInstr( 25 );
alias MI_AddrReg_En: std_logic is R_MicroInstr( 24 );
alias MI_ALU_Op: std_logic_vector( 2 downto 0 ) is R_MicroInstr( 23 downto 21 );
alias MI_ALU_Reg_En: std_logic is R_MicroInstr( 20 );
alias MI_RF_In: std_logic is R_MicroInstr( 19 );
alias MI_RF_W: std_logic is R_MicroInstr( 18 );
alias MI_RF_Addr_W: std_logic_vector( 1 downto 0 ) is R_MicroInstr( 17 downto 16 );
alias MI_RF_R: std_logic is R_MicroInstr( 15 );
alias MI_RF_Addr_R: std_logic_vector( 1 downto 0 ) is R_MicroInstr( 14 downto 13 );
alias MI_CCM_Op: std_logic_vector( 3 downto 0 ) is R_MicroInstr( 12 downto 9 );
alias MI_Seq_Else: std_logic is R_MicroInstr( 8 );
alias MI_Seq_Op: std_logic_vector( 1 downto 0 ) is R_MicroInstr( 7 downto 6 );
alias MI_Seq_Addr: std_logic_vector( 5 downto 0 ) is R_MicroInstr( 5 downto 0 );
-- synopsys translate_on
type T_MicroROM is array( 0 TO 55 ) of std_logic_vector( 45 downto 0 );
constant MicroROM: T_MicroROM := (
-- Start: 0x0
"0000000000000000000010111100001111111010000000",
"0000000000000000000000111011110000000000000000",
"0000000000000000000000111000000000000000010000",
"0000000000000000000000111000000000000000010000",
"0000000000000000000000111000000000000000010000",
"0000000000000000000000111000000000000000010011",
"0000000000000000000000111000000000000000010111",
"0000000000000000000000111000000000000000011101",
"0000000000000000000000111100001010000000100001",
"0000000000000000000000111100001010000000100100",
"0000000000000010010101101001010000000000101100",
"0000000000000000000000111100001010000000101110",
"0000000000000000010100101001100000000000110001",
"0000000000000000010100101001100000000000110011",
"0000000000000000000000111000000000000000110101",
"0000000000000000000000111000000000000000000000",
-- LoadArg: 0x10
"0000000000000000000001101001000001111000000000",
-- LoadArg_L1: 0x11
"0000010000000000000000111000000000100000010001",
"1000000000000000000001000001001000001100010001",
-- Insert1: 0x13
"0000000000000010001101101001010001111000000000",
-- Insert1_L1: 0x14
"0111101000000000000100111000000001111000000000",
"0000000000000000000001000001011010110000010100",
"0000000000000100000000111000000000000000000000",
-- Insert2: 0x17
"0000000000000000001100111000000000101000011010",
"0000000000000000000000110001010001111000000000",
"0000000000000000000001101001100000000000011011",
-- Insert2_L0: 0x1a
"0000000000000000000001111001101011111000000000",
-- Insert2_L1: 0x1b
"0111101000000000000100111000001101111000000000",
"0000000000000000000001000001101100110100011011",
-- Search: 0x1d
"0000000000000010001101101001000001111000000000",
-- Search_L1: 0x1e
"0010101000000000000100111000000001111000000000",
"0000000000000000000001000001001000110000011110",
"0000000000000100000000111000000000000000000000",
-- WritePrefix: 0x21
"0000000000000000000001101001000001111000000000",
-- WritePrefix_L1: 0x22
"0010100101101000000000111000000001111000000000",
"0000000000000000000001000001001000011100100010",
-- WritePrefix2: 0x24
"0000000000000000000000101001000001111000000000",
"0000000000000000000000111000001100011000101001",
-- WritePrefix2_L0: 0x26
"0000000000000000000001111000001000010000101000",
"0010100101101000100000000001001000000000100110",
-- WritePrefix2_L1: 0x28
"0010100101101001000000000001001001111000000000",
-- WritePrefix2_L5: 0x29
"0000000000000000000000111100001101111000000000",
-- WritePrefix2_L6: 0x2a
"0000000000000000000001111000001000010000000000",
"0010100101101000000000000001001000000000101010",
-- GetPrevSlice: 0x2c
"0010101000000000000100111000000001111000000000",
"0000000000000000000001000001011010110100101100",
-- UpdatePMask: 0x2e
"0000000000000000000001101001000001111000000000",
-- UpdatePMask_L1: 0x2f
"0010000101000000000000111000000001111000000000",
"0000000000000000000001000001001000011100101111",
-- ReadPMask: 0x31
"0110000011000000000100111000000001111000000000",
"0000000000000000000001000001101100110100110011",
-- ReadPrefix: 0x33
"0101000011011000000100111000000001111000000000",
"0000000000000000000001000001101100110100110011",
-- WriteArgs: 0x35
"0000000000000000000001101001000001111000000000",
-- WriteArgs_L1: 0x36
"0010110000000000000000111000001001111000000000",
"0000000000000000000001000001001000001100110110"
);
--==================================================================================
-- End of automatically generated VHDL code segment
--==================================================================================
Article: 1571I am searching for a PD routing tool for FPGAs. In my case these are Xilinx xc4000. I want to route ready placed FPGAs. Any help welcome Marco -- Marco Schmidt schmidt@peanuts.informatik.uni-tuebingen.de kunz@irc http://wsiserv.informatik.uni-tuebingen.de/~schmidtArticle: 1572
In article <3uh2ms$ba@yama.mcc.ac.uk> mkh@sn2.ee.umist.ac.uk (VLSI) writes: >From: mkh@sn2.ee.umist.ac.uk (VLSI) >Subject: ACTEL PLACE AND ROUTE >Date: 18 Jul 1995 19:40:12 GMT >Please could you tell me how you add critical (fast/medium/non-critical) >properties to NETS on ACTEL Designs on Mentor. >The Action Logic System (ALS) manual is of no help at all. >Thank you in advance. On the PC platform, using ALS 2.3.2, net criticality is assigned using a file with a .crt extension. The format of the file starts with a DEF <design name> and ends with an END. statement. Critical net assignments are found between the DEF and END statements and have the following format: NET <net name>;;CRT:<criticality assignment>. Criticality assignments (for 2.3.2) are F for fast, M for medium, and U for uncritical. Unassigned nets use default criticality. A sample CRT file has the following format: DEF sample NET U1/net1;;CRT:F. NET U2/net2;;CRT:M. NET U3/net3;;CRT:U. END. Complete path names (relative from the top level schematic) are required for all nets. There are two limitations when assigning net criticality. First there is a limit to the number of critical nets and types found in a design. The second limitation reduces the fanout of critical nets. Hope this helps, Paul T. Shultz <shultz@clark.net>Article: 1573
Does anyone have feel for what FPGA software is good
and inexpensive for implementing decoders and counters etc.
I currently have Altera software but would like to use other
mfg's. I need more density and lower power.
Thank-In-Advance.
/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
\ James "frizby" Grandt: Instrumentation Specialist ECE /
/ Department of Geology & Geophysics UW - Madison \
\ BELL: (6O8) 262-9698 Work/884-92O2 Home /
/ Internet: frizby@geology.wisc.edu \
\ WWW: http://geology.wisc.edu/~frizby/ /
/ Don't Fix What Aint Broke Just Make It Better \
\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/
Article: 1574
In article <shultz.17.300CF5D6@clark.net>,
Paul T. Shultz <shultz@clark.net> wrote:
>In article <3uh2ms$ba@yama.mcc.ac.uk> mkh@sn2.ee.umist.ac.uk (VLSI) writes:
>>From: mkh@sn2.ee.umist.ac.uk (VLSI)
>>Subject: ACTEL PLACE AND ROUTE
>>Date: 18 Jul 1995 19:40:12 GMT
>
>>Please could you tell me how you add critical (fast/medium/non-critical)
>>properties to NETS on ACTEL Designs on Mentor.
>
>>The Action Logic System (ALS) manual is of no help at all.
I know that the PC version of ALS program preserves net
attributes/properties. Thus an attribute of 'CRT=F' on a net or bus
assigns the criticality.
Eric
--
Eric Pearson -- Focus Systems -- Waterloo, Ontario
ecp@focus-systems.on.ca (519) 746-4918
"We Engineer Innovative Imaging Solutions"
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