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Any opinions out there on the 5200 series vs. the 3000. I've done several 3000 series designs and am considering migrating. Also, has anyone have good/bad experiences using Xilinx-ABEL for entire chip designs? CharlieArticle: 2426
Charles Y. Hitchcock (Charles.Y.Hitchcock@dartmouth.edu) wrote: : Any opinions out there on the 5200 series vs. the 3000. I've done : several 3000 series designs and am considering migrating. Also, has : anyone have good/bad experiences using Xilinx-ABEL for entire chip : designs? : Charlie The 5200 is much more flexible. I think it gives you much more FPGA for the same money. However, I think the fastest 3000 chips outper- form anything you can find in the 5200 series. The biggest problem of XABEL is that you cannot use it as a standalone design - there is no way to describe IO blocks and internal tristate buffers in XABEL. You will have to pull them out of your .abl file and use some kind of schematic entry. Other than that I had no problems with it (except for the bugs and there is a lot of them in XABEL but in most of the cases you can find workaro- unds using good old schematic). My last design was using an XC4006 part and consisted of a big .abl file (about 40 Kbytes) and a small ViewLogic schematic.Article: 2427
Hi, In our company we want to start using SRAM based FPGA devices with a Verilog or VHDL environment to complement our present Quicklogic/Verilog environment. The choice is between Xilinx or Altera. If anybody has experience with either the devices or the software environment, I would like to know both positive and negative aspects of both. I had some experience with the Xilinx 3100 family and Xilinx Abel some 2 years ago, but that was not very positive. I tried to design a VESA local bus interface, but could not get the desired timing. There seemed to be a large difference between the specs and the actual obtainable results. The week point seemed to be the interconnect which limited the maximum speed and the gate usage to about 65%. Also fixing pin locations often resulted in non routable designs. Are the new parts (4000 and 5000) better or do they still suffer from similar weakness? I have no experience whatsoever with Altera, but due to my previous negative experience with Xilinx I'm slightly biased to Altera. Thanks for any info Jean-Paul SmeetsArticle: 2428
Viewlogic will have Chronologic VCS released on Window'95 too by early '96 Ravi suzanne@world.std.com (suzanne M southworth) wrote: >Frontline is offering a two for one sale. Here is there >phone #: 408-456-0222, ask for Rich Curtin. >I would suggest you try them all out. Wellspring has a real good >product too, by the way.Article: 2429
Hey, I am looking for a 5x5 (or 3x3) median filter with 8 bits input and a maximum processing rate of 10 Mhz. Is there any comercially available component for this task or any proposed solutions for implementation in an FPGA (Xilinx)? Knut Tvete Senior Scientist Norwegian Defence Research Establishment email: knut.tvete@ffi.noArticle: 2430
Hey, I am looking for a 5x5 (or 3x3) median filter with 8 bits input and a maximum processing rate of 10 Mhz. Is there any comercially available component for this task or any proposed solutions for implementation in an FPGA (Xilinx)? Knut Tvete Senior Scientist Norwegian Defence Research Establishment email: knut.tvete@ffi.noArticle: 2431
Hey, I am looking for a 5x5 (or 3x3) median filter with 8 bits input and a maximum processing rate of 10 Mhz. Is there any comercially available component for this task or any proposed solutions for implementation in an FPGA (Xilinx)? Knut Tvete Senior Scientist Norwegian Defence Research Establishment email: knut.tvete@ffi.noArticle: 2432
Hey, I am looking for a 5x5 (or 3x3) median filter with 8 bits input and a maximum processing rate of 10 Mhz. Is there any comercially available component for this task or any proposed solutions for implementation in an FPGA (Xilinx)? Knut Tvete Senior Scientist Norwegian Defence Research Establishment email: knut.tvete@ffi.noArticle: 2433
Hey, I am looking for a 5x5 (or 3x3) median filter with 8 bits input and a maximum processing rate of 10 Mhz. Is there any comercially available component for this task or any proposed solutions for implementation in an FPGA (Xilinx)? Knut Tvete Senior Scientist Norwegian Defence Research Establishment email: knut.tvete@ffi.noArticle: 2434
In article <4a1dm2$6jl@stargate.telnetwork.it>, >ESPRESSO II or MV >Multiple logic value minimizer. Alberto, I think this was done at UC-Berkeley, though I could be wrong. Good luck in your search!! Erik Jessen Com-Solutions, Inc. (619) 942-9790 The views expressed here are purely my own.Article: 2435
George Noten (garyk@svpal.svpal.org) wrote: : The biggest problem of XABEL is that you cannot use it as a standalone : design - there is no way to describe IO blocks and internal tristate : buffers in XABEL. You will have to pull them out of your .abl file : and use some kind of schematic entry. This isn't true: Xilinx document #15778 describes how to do it. I'd quote from it here, but Xilinx specifically prohibits the document's "dissemination or distribution" ! I suggest you ask them for a copy. Richard.Article: 2436
I'm having a bit of a problem using Altera's Verilog output as input to a Verilog XL clone simulator. The Altera design leaves both the CLRN and PRN inputs to a DFF floating and the Verilog output file correctly shows both of these inputs tied to VCC in the DFF primitive instantiation. The DFF UDP also contains an initial statement to initialize Q to zero at time zero. Unfortunately, when I simulate this circuit, Q is X initially and remains so until sometime later when the first clock edge appears. Since my simulator is an XL clone, I thought that perhaps others had run across this problem. Any help would be appreciated. Joe.Article: 2437
FINAL CALL FOR PAPERS (extended DEADLINE - December 20)
******************************************************
SPECIAL SESSION ON REAL-TIME SYSTEMS
ELEVENTH INTERNATIONAL CONFERENCE ON SYSTEMS ENGINEERING (ICSE '96)
UNIVERSITY OF NEVADA, LAS VEGAS
9-11 July 1996
Session Organizers:
Professor Sajal K. Das Dr. Raja Neogi
Department of Computer Science Tektronix Inc.
University of North Texas P. O. BOX 500
P.O. Box 13886 MS 50-470
Denton, TX 76203-6886, USA Beaverton, Oregon 97077
Email: das@cs.unt.edu Email: rajan@salsa.labs.tek.com
Voice: (817) 565-4256 Voice: 503-627-5640
Fax: (817) 565-2799 Fax: 503-627-1736
This series of International Conferences is jointly organized on
a rotational basis among the three Institutions, University of
Nevada, Las Vegas, USA the Technical University of Wroclaw,
Poland and Coventry University, UK. The 11th International
Conference on Systems Engineering takes place at the
Howard R. Hughes College of Engineering, University of Nevada,
Las Vegas on July 9-11, 1996.
The special session on Real-Time Systems is planned to
cover various aspects of real-time systems with
specific emphasis on multimedia, graphics and associated
networking technologies.
SPECIAL SESSION PREVIEW:
------------------------
Emerging networked multimedia applications characterized
by intense video-signal/graphics processing (100-10K MIPS)
and high bandwidth video traffic requirements
demand specialized architectures focused on a narrow
range of applications to keep the price/performance attribute
attractive. The pace at which the marketplace is changing,
however, calls for programmable architectures in which a
common hardware platform can be used to rapidly develop
new silicon solutions based on software development only.
It is expected that such software/firmware layer(s) sitting
atop specialized real-time kernels will allow enough
dynamic reconfiguration/programmability
at reasonable price points. In the past,
high power-consumption and degraded
performance have been the deterring factors for
building such systems on silicon.
It is expected that recent advances in VLSI
technology will foster new research in this direction.
Topics of interest include, but are not limited to:
Indexing, Accessing and Processing Real-time Media
Real-time Image Processing Architectures
High-performance Architectures for 2D/3D Graphics
Multimedia System Architectures
Real-time Operating Systems for Multimedia
High-performance Programmable Packet Switching Architectures
Real-time Network Routing
Specialized Architectures for set-top Decoders / interactive Television
Models of Inter-Processor Communication
VLSI Implementations
Applications of Video Signal Processors
SUBMISSION POLICIES:
-------------------
Authors are encouraged to submit SIX copies of an
abstract of their manuscript (approximately 1000 words)
so as to reach to the session chairs on or before December 1, 1995.
The abstract, written in English, should be typed double spaced
and must be suitable for a technical review.
Electronic submission of postscript files is strongly encouraged.
Refereeing of abstracts submitted before the deadline date will
take place on a regular basis. This will allow early decisions
to be taken and should assist authors in their projected
planning arrangements. At least one author of an
accepted paper in the special session will be expected
to attend the conference. (Abstracts, that cannot be accommodated in
the special session, will be considered for other related sessions
of the conference.)
A special issues of a Journal is being planned to publish
selected papers from this session.
Since conference proceedings will be available for participants,
the following deadlines for submission of abstracts/papers
should be strictly adhered to.
DEADLINES:
---------
Submission of Abstracts Dec. 1, 1995 (DEADLINE extended to December 20)
Acceptance Decisions Feb. 15, 1996
Submission of Full Papers Mar. 15, 1996
Please send your abstract for the session on Real-time Systems to:
(Electronic Submission, ascii Or postscript, of ABSTRACT is preferred)
Dr. Raja Neogi
Tektronix Inc.
P. O. BOX 500
MS 50-470
Beaverton, Oregon 97077
Email: rajan@salsa.labs.tek.com
Voice: 503-627-5640
Fax: 503-627-1736
PRELIMINARY ARRANGEMENTS:
------------------------
Conference fees, provisionally estimated at $250, include a copy of
the Conference Proceedings, the Conference Banquet, a Civic
Reception and lunch on the three conference days. Participants will
have the option of being accommodated in the University dormitories
at a nominal fee. The Conference fee is exclusive of accommodation
charges. The working language of the Conference is English, which
will be used for all presentations, discussions and printed
material. A full social program for accompanying persons will be
organized providing sufficient numbers are interested in participating.
Article: 2438In article <30C3F771.4B26@ffi.no> Knut Tvete <ktv@ffi.no> writes: >Hey, > >I am looking for a 5x5 (or 3x3) median filter with 8 bits input and a >maximum processing rate of 10 Mhz. Is there any comercially available >component for this task or any proposed solutions for implementation in >an FPGA (Xilinx)? > > >Knut Tvete > >Senior Scientist >Norwegian Defence Research Establishment > >email: knut.tvete@ffi.no Although you asked 5 times, I'll only answer once. I have built just such a filter recently for one of my clients. It is a 3x3 median, using 8 bit data, and runs at 25MHz in an XC4008-5. It basically takes the 9 pixels, and passes them through a network of sorting blocks that are each a pipeline stage. The pipe is 5 deep, and delivers a new result every 40nS. 5x5 would be a bit harder. Philip Freidin.Article: 2439
In article <4a00f3$agm@tuegate.tue.nl> jeanpaul@stack.urc.tue.nl (Jean-Paul Smeets) writes: >Hi, > >In our company we want to start using SRAM based FPGA devices with a >Verilog or VHDL environment to complement our present >Quicklogic/Verilog environment. > >The choice is between Xilinx or Altera. If anybody has experience with >either the devices or the software environment, I would like to know >both positive and negative aspects of both. We use Verilog with Exemplar (synthesis) and Silos III (simulation) to create all Xilinx designs. > >I had some experience with the Xilinx 3100 family and Xilinx Abel some >2 years ago, but that was not very positive. I tried to design a VESA >local bus interface, but could not get the desired timing. There >seemed to be a large difference between the specs and the actual >obtainable results. The week point seemed to be the interconnect which >limited the maximum speed and the gate usage to about 65%. Also fixing >pin locations often resulted in non routable designs. > >Are the new parts (4000 and 5000) better or do they still suffer from >similar weakness? There are some features that will make your life easier now: 1. Perfomance based place/route. Will let you know immediately if you are meeting your specs. 2. Faster and larger parts. As always, the larger the part, the more work you have to do to utilize the same percentage of gates. To use 80-90% of a large part, you will have to do alot of up-front planning and probably use some floor planning tools. > >I have no experience whatsoever with Altera, but due to my previous >negative experience with Xilinx I'm slightly biased to Altera. We have not used Altera, mainly because Xilinx was the first SRAM FPGA and we became familiar with their tools and have never found it necessary to learn a new set of tools. Good luck, Tom Dillon DILLON ENGINEERING 2017 Continental Place Suite 5 Mount Vernon, WA 98273-5649 e-mail: tom@dilleng.wa.com Voice : (360) 424-3794 FAX : (360) 424-5894Article: 2440
Knut Tvete <ktv@ffi.no> wrote:
>Hey,
>
>I am looking for a 5x5 (or 3x3) median filter with 8 bits input and a
>maximum processing rate of 10 Mhz. Is there any comercially available
>component for this task or any proposed solutions for implementation in
>an FPGA (Xilinx)?
>
>
>Knut Tvete
>
>Senior Scientist
>Norwegian Defence Research Establishment
>
>email: knut.tvete@ffi.no
Actually, this is every practical using distributed arithmetic techniques on
Xilinx 4K series FPGAs. You could look at my thesis online for some
information on this:
My page at BYU:
http://www.ee.byu.edu/~petersr/russ.html
The lab's home page:
http://splish.ee.byu.edu/
My thesis is huge unfortunately and I don't have time at the moment to reduce
it for better transport over the net. In any case, what you are asking has
been and can be done using several types of FPGAs.
Russell Petersen
russp@valhalla.fc.hp.com
--
_______________________________________________
** ** ****** Russell Petersen
** ** * * russp@valhalla.fc.hp.com
****** ****** voice: (970) 229-7007
** ** *
** ** *
_______________________________________________
Article: 2441Hi all! I'm doing my final University Thesis on Logic Design. Specifically, I have to project a computer aided integrated environment to develepe finite state machines, under Windows 3.1. I need some public domain programs, possibly in C or C++ language, implementing some fundamental algorithms. I've already done my searches with no result. I'be grateful to everybody who will give me information about the sites where I can find these programs, or similar ones, implementing the same algorithms, or sites containing archive on these subjects or information about the places where looking for them. The programs I'm looking for are: ENCORE - Encoding Reduction An algorithm for constrained encoding of Finite State Machine. NOVA - State Assignement of finite state machine for two level logic implementation using group approach. DIET - Optimal state assignment for finite state machine using constrained method. KISS - Keep Internal States Simple Optimal state assignment for finite state machine with grouping method ESPRESSO II or MV Multiple logic value minimizer. MIS Multiple level logic optimization systems. MUSTANG State assignment of finite state machine targeting multiple level logic implementation STG - Sequential test generation A sequential circuit test generation systems MNCN FSM - Logic benchmarks Logic Synthesis and optimization benchmarks Thanks in advance to everybody will help me. Alberto Fusco, EE student C/O pietro@microsys.itArticle: 2442
Summary of replies received to my earlier post, requesting
info. on migrating FPGA designs to ASICs.
The firms listed below have indicated a capability for this
type of work. I have not attempted to place them in any kind
of "order of merit"; they are listed in alphabetical order
only.
Personal contacts where given, are posted with the consent of
the persons named.
The point has been stressed to me repeatedly, that there is
_much_ more to a successful migration than simply shipping off
a netlist, and awaiting silicon. The big gotchas are of course
generating test vectors, and getting the timings right. Many of
the listed vendors can do this, however it is a costly business,
and will require very close working with the FPGA designers.
Needless to say, the final ASIC will be only as good as the
vectors used to test it.
In some cases, the test files used to simulate the FPGA
design can be used as a starting point for the ASIC test vectors,
but the match is not exact, since the goal is different. The
FPGA tests assumed a good chip, and sought to validate the
design. The ASIC vectors will be the opposite: the design is
assumed good, it is the embodiment in the chip that is being
tested.
AMI
Pocatello, Idaho
USA
Chrysalis Research Corp.
52 Domino Dr., Concord, MA 01742
USA
Phone - (508)371-9115
Fax - (508)371-9175
I.S.T.
EUROPOLE
4, place Robert Schuman
38024 GRENOBLE Cedex 1
FRANCE
Contact: Regis PELTIER
Field Applications Engineer
E-mail : rpeltier@ist.fr
Orbit Semiconductor, Inc.
1215 Bordeaux Drive
Sunnyvale, CA 94089
USA
Phone - (408)744-1800
Fax - (408)747-1263
South African Microelectronic Systems (Pty) Ltd
Technopark,
Stellenbosch,
SOUTH AFRICA
TEMIC Semiconductors (Matra Harris)
(No address: European)
Xilinx Inc.
2100 Logic Drive
San Jose, CA 95124
USA
Contact: Roman Iwanczuk
Technical Marketing Manager
Email: roman.iwanczuk@Xilinx.COM
--
Dave
PGP fingerprint = 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
Article: 2443In article <49d6mo$ju2@bmerhc5e.bnr.ca>, crm182c@bmers2da.bnr.ca (Hing-Fai Lee) wrote: >In article <ssikdar.21.00006806@best.com>, Som Sikdar <ssikdar@best.com> wrote: >> >>Is there any VHDL/Verilog source available in the public domain for byte-wise > >Parallel CRC computation was a favorite topic in Computer Design from the >late 60s to early 70s. Check it out in your local library. Good Luck. >Hing-Fai Please check an excellent aricle about generalized solutions to Parallel CRC computing in : IEEE Micro of Octobel 1990 : "Parallel CRC Generation" by Guido Albertengo & Riccardo Sisto, pages 63-71. Some understanding of Z transforms is required. But, it gives you a generic solution Alex Koegel DSPC IsraelArticle: 2444
<EMPTY> -- _________ _________ _________ _________ _________ _________ _ ---_.__Y__ |#######| |EMail: | | jouri@ iibankm .msk.su | |#######| / | |_|_|_|_) -oo---oo-~-oo---oo-~-oo---oo-~-oo---oo-~-oo---oo-~-oo---oo-~-oo--()()()()\Article: 2445
Alex Koegel (alexk@dspis.co.il) wrote: : In article <49d6mo$ju2@bmerhc5e.bnr.ca>, : crm182c@bmers2da.bnr.ca (Hing-Fai Lee) wrote: : >In article <ssikdar.21.00006806@best.com>, Som Sikdar <ssikdar@best.com> : wrote: : >> : >>Is there any VHDL/Verilog source available in the public domain for : byte-wise There's a very good description in a book by John McNamara on Data communications --Alan Arnaud ECLA Inc. Xilinx Certfied arnaud@ecla.com 1-800-928-1236Article: 2446
These are the horror stories I've seen/heard: Altera: same problem on locking down pins in 7000 series part. In fact, the problem surfaced when an output that was unused, was removed from the netlist. Altera refused to route the design, even though it worked fine with the extra output. Xilinx: severe shortage of routing in 4013 parts; I've heard this is a problem in all the 4xxx parts, but have no personal experience. New things to take note of: - Altera's 8k and 10k parts are SRAM based & you can do your own routing, so they are basically identical to Xilinx 4xxx series in that respect. - Xilinx may have added extra routing in newer parts; don't know The really important tool in any large FPGA is a good floorplanner; if you don't have that, then even if the design fits, it will take a lot longer to P&R, than with a floorplanner. In the worst case, no floorplanner => uncompleted routing. Has anyone tried out the ORCA tools, for comparison to Xilinx and Altera? Erik Jessen Com-Solutions, Inc. (619) 942-9790 The views expressed here are purely my own.Article: 2447
Hi, I'm responsible for the exercises in a VHDL course, in the exercises we use Mentor Graphics QuickVHDL as simulator and Autologic for synthesis. Here my problems start. I have tried to synthesize with our Altera library as target technology and it worked to a point where Mentor core dump (some where in the netlist processor SW, NP). I've seen some information that new Autologic will crash if it use the Altera-1.5 package. Is this true, and if so are there any one that can help me to get another Altera library (or any other FPGA library) for our Autologic platform for free. PLEAS HELP ME... ------------------------------------------------------------------- Mattias O'Nils Mid Sweden University Department of Information Technology 851 70 Sundsvall SWEDEN Phone: +46 60 18 87 80 Fax: +46 60 18 88 30 E-mail: Mattias.ONils@nts.mh.se WWW: http://www.nts.mh.se/~mattiasArticle: 2448
jeanpaul@stack.urc.tue.nl (Jean-Paul Smeets) writes: >The choice is between Xilinx or Altera. If anybody has experience with >either the devices or the software environment, I would like to know >both positive and negative aspects of both. >I had some experience with the Xilinx 3100 family and Xilinx Abel some >2 years ago, but that was not very positive. I tried to design a VESA >local bus interface, but could not get the desired timing. There >seemed to be a large difference between the specs and the actual >obtainable results. The week point seemed to be the interconnect which >limited the maximum speed and the gate usage to about 65%. Also fixing >pin locations often resulted in non routable designs. The design I'm currently working on uses Altera FLEX 8000's (8636A-4 to be exact), and I've found almost the exact same limitations, though it's been easier for me to meet timing (Most of my logic is running at 20MHz or less, with only a few critical parts running at 40MHz). The first time I compiled the AHDL file, it fit at about 80% logic cell utilization. After that, I locked the pins down, and immediately found that the part would no longer route after minor changes. In fact, if I took the exact same AHDL file I used to lock the pinout and tried recompiling, it still wouldn't route. Even freezing logic cell assignments didn't help (it just seemed to confuse Max+Plus II even more). After a few panicky days (the board was well into the PCB design stage at this point and the schedule was critical), I was able to strip enough logic out of the part to get the utilization down to about 65%. At that point it started routing again, though it still fails occasionally. Even with 80% of LCELL's used, the routing utilization was only about 60% in most places. This leads me to believe that Altera's interconnect scheme isn't very efficient. I've also run into several other weaknesses in the FLEX 8K architecture which have been very painful for my design. >Are the new parts (4000 and 5000) better or do they still suffer from >similar weakness? The XC5000 is supposed to have some sort of new routing structure in the I/O ring to reduce pinout problems. Don't know much about it, though. >I have no experience whatsoever with Altera, but due to my previous >negative experience with Xilinx I'm slightly biased to Altera. I'm in just the opposite state of mind. Maybe Xilinx and Altera both suck equally, but we just haven't been burned by the other architecture yet :-) :-). Right now I'm having bad luck with Altera, while at the same time there are a couple of Xilinx guys in my group who swear by them and always seem to have good luck with them. Thus Xilinx is looking more attractive to me. The trick seems to be to carefully floorplan the design before locking the pinouts. The Xilinx routing scheme seems to respond well to floorplanning (according to these guys). -Paul -- Paul Secinaro (pss1@christa.unh.edu) Synthetic Vision and Pattern Analysis Laboratory UNH Dept. of Electrical and Computer EngineeringArticle: 2449
In article <4a20b9$o6l@saturn.ball.com> Joe Troxel <jtroxel@ball.com> writes: > > I'm having a bit of a problem using Altera's Verilog output as input > to a Verilog XL clone simulator. > > The Altera design leaves both the CLRN and PRN inputs to a DFF > floating and the Verilog output file correctly shows both of these > inputs tied to VCC in the DFF primitive instantiation. The DFF > UDP also contains an initial statement to initialize Q to zero > at time zero. > > Unfortunately, when I simulate this circuit, Q is X initially > and remains so until sometime later when the first clock edge appears. > > Since my simulator is an XL clone, I thought that perhaps others had > run across this problem. Any help would be appreciated. > > Joe. > Joe: You've hit upon a very common misconception. The initial value on the UDP output does not propagate to the rest of the circuit at time 0, since it is not a true "event." The right way to think of the initial statement in a UDP is that it initializes the _state_ of the primitive, not the output. The UDP output does not propagate until an actual output change occurs (i.e. at the first clock edge). Hope this helps. -- Wm. Scott Cranston | | 270 Billerica Rd Member of Consulting Staff | This space | Chelmsford, MA 01824 Project Leader, Verilog-XL | for rent | e-mail: cranston@cadence.com Cadence Design Systems, Inc | | PH: (508) 446 6217
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