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Specifically it's about how to specify the function to implement in the FGEN instance. this I have as the cell definition early in the file: [...] (cell fgen (cellType generic) (view fgen (viewType netlist) (interface (parameter FUNCTION (string "")) (port A (direction INPUT)) (port B (direction INPUT)) (port C (direction INPUT)) (port D (direction INPUT)) (port G (direction OUTPUT)) ) ) ) [...] later I have: [...] (instance C_fgen (viewRef fgen (cellRef fgen (libraryRef &_36_ATMEL_FPGA_47_cells))) (parameterAssign FUNCTION (string "A*B+C*D")) ) [...] cadences edif2fig program chokes on the `string' token >>ERROR (token="(STRING") at line 282 in file: c:\Atmel\examples\at40k\ptest\ptest.edf >>Syntax error found in input file Am I using `parameter' and `parameterAssign' correctly? If not, what are their semantics? Should I use `property' instead? ???

The Xilinx packaging documentation for the VQ44/VQG44 package (document PK0= 12, v1.2, dataed 2004-06-18) doesn't contain a recommended PCB footprint. I= n attempting to find such a footprint, Google turned up what appears to be = a copy of a Xilinx web page, apparently no longer available from the Xilinx= web site: http://glacier.lbl.gov/gtp/DOM/dataSheets/Xilinx_pkg_info.htm Does Xilinx actually still have this information in an current publication?= In the description of the package footprint in my library I'd like to be a= ble to cite a current Xilinx document.

On Tuesday, February 23, 2016 at 3:38:17 PM UTC+3, Daniel Kho wrote: > Xilinx's configuration files aren't really that human-unreadable. I meant that it contains huge amount of parameters and sometimes it's unclear what they mean.

I've analysed the axi_pcie.vhd module in the original Xilinx IP core, and I= have found, that: * The msi_vector_num is delayed together with the intx_msi_request. * The delayed msi_vector_num is read when the rising edge of=20 the delayed intx_msi_request is detected. Therefore,=20 the msi_vector_num value is important only in that cycle, in which the intx_msi_request is set to 1. * After the the delayed msi_vector_num is read, the state machine changes its state to INTR_HS. In that state it ignores further=20 changes of intx_msi_request and msi_vector_num.=20 The machine leaves that state only, when sig_blk_interrupt_rdy is asserted. However, it is important, that intx_msi_request=20 goes low before INTR_HS state is left (it is OK to set it high only for one cycle). * As delayed signals msi_vector_num and intx_msi_request are used, it is safe to set the new value of mis_vector_num and to assert=20 intx_msi_reuqest in the same cycle in which the intx_msi_grant was set to '1'. However, the above scheme of interrupt handling rises one more question. How masking of interrupts is handled? In case of legacy interrupts, it is easy. When my device requires service, = it keeps the IRQ line asserted. If the interrupt is masked, the host CPU will not be interrupted. Of course= the device may be serviced in another way (e.g., via polling). So it may h= appen that even though interrupt was masked, the irq line may get deasserte= d. When the interrupt gets unmasked, the interrupt will be generated only if t= he irq line is still asserted. Now, in the MSI handling scheme implemented in the AXI MM 2 PCIe, it is unc= lear how the masking is handled. The user IP core should assert intx_msi_request for one clock cycle, and wa= it until intx_msi_grant is asserted (also for one cycle). What happens if the interrupt is masked? Will the intx_msi_grant be never a= sserted? So the core will wait forever and other MSI interrupts can't be po= sted - obviously bad solution. If the core asserts intx_msi_granted, even if the interrupt is masked, then= of course next MSI interrupts may be posted, but what will be the state of= the current interrupt? Will it be remembered as active, and the appropriate ISR will be executed b= y the host CPU, when the interrupt is unmasked? However, what if the device is serviced by polling, and it does not require= servicing any more? One of main advantages of MSI(X) interrupts is that I don't need to check t= he status of the device at the beginig of my ISR to ensure that my device r= equires servicing. With that behavior I still have to do it! OK. So what if the masked interrupt is confirmed (by intx_msi_granted) but = silently dropped. In that case it is even worse, because my IP core assumes= that the interrupt was successfully posted and ISR will be executed, which= will never happen. So if that solution is implemented, my IP core should r= esend the interrupt periodically until it is finally serviced. So we get an= other crazy situation, where the peripheral must poll the PCIe host. I hope that I've mistaken in the above analysis. If not, it seems that hand= ling of MSI interrupts is somehow broken... I'll be glad if someone explains how it is really handled. Thank you in advance, Best regards, Wojtek

Eric Smith wrote: > The Xilinx packaging documentation for the VQ44/VQG44 package (document > PK012, v1.2, dataed 2004-06-18) doesn't contain a recommended PCB > footprint. In attempting to find such a footprint, Google turned up what > appears to be a copy of a Xilinx web page, apparently no longer available > from the Xilinx web site: > > http://glacier.lbl.gov/gtp/DOM/dataSheets/Xilinx_pkg_info.htm > > Does Xilinx actually still have this information in an current > publication? In the description of the package footprint in my library I'd > like to be able to cite a current Xilinx document. I just made up my own footprint, a 2-minute job in Protel99 to make from scratch, or 30 seconds to tweak the pad widths, etc. from an existing JEDEC footprint. I usually make the stock pads narrower to resist bridging. Always make sure you know whether pin 1 is in the corner or center of a row. I've been tripped up by that before. Jon

Hi, I have found the following document: https://pcisig.com/sites/default/files/specification_documents/msi-x_ecn.pdf It states (page 189): "Per-vector masking is managed through a Mask and Pending bit pair per MSI vector or MSI-X Table entry. An MSI vector is masked when its associated Mask bit is set. An MSI-X vector is masked when its associated MSI-X Table entry Mask bit or the MSI-X Function Mask bit is set. While a vector is masked, the function is prohibited from sending the associated message, and the function must set the associated Pending bit whenever the function would otherwise send the message. When software unmasks a vector whose associated Pending bit is set, the function must schedule sending the associated message, and clear the Pending bit as soon as the message has been sent." So it seems, that in case of masked MSI(X) interrupt, once triggered it can't be revoked. So if my driver switches to the polling mode for performance reasons (like in NAPI), it must be prepared for receiving an MSI(X) interrupt as soon, as it gets unmasked, even though the device does not require servicing (It was serviced in the polling mode, before unmasking the interrupt). So reading the device status at the begining of ISR may be required like in the legacy mode... Am I right? Regards, Wojtek

I'd like to know if I can implement them with single bit full adders and single bit mult cells only, or if I need additional primitives. (trying to guess the semantics from the logic ops in their simulation modules just makes my head hurt)

On 02/29/2016 05:38 PM, Johann Klammer wrote: > I'd like to know if I can implement them with single bit full adders > and single bit mult cells only, or if I need additional primitives. > > (trying to guess the semantics from the logic ops in their simulation > modules just makes my head hurt) > > and what's those $lcu things (in techmap.v)

Nevermind... seems they want a (property...) in the instantiation...

VHDL testbenches very often need better structuring. We should strive for overview, modifiability, extendibility, maintainability and re-use. We are now posting 3 very easy to understand articles on LinkedIn on how you can achieve this, and of course also increase efficiency and quality significantly. (Using Free, Open source code only) Please check out: https://www.linkedin.com/pulse/advanced-vhdl-verification-made-simple-anyone-espen-tallaksen?trk=prof-post

On Tuesday, February 23, 2016 at 4:16:51 AM UTC-8, Daniel Kho wrote: > On Tuesday, 23 February 2016 14:40:15 UTC+8, rickman wrote: > > On 2/21/2016 7:14 PM, Weng Tianxiang wrote: > > > On Sunday, February 21, 2016 at 1:58:03 PM UTC-8, Jan Marjanovi=C4=8D= wrote: > > >> On Sunday, February 21, 2016 at 8:47:38 PM UTC+1, Weng Tianxiang wro= te: > > >>> Hi, > > >>> > > >>> I need a full code example on how to use a floating multiplier on F= PGA for VHDL-2008. What is the document name from XILINX? > > >>> > > >>> Jim's slides on floating multiplier are good, but not full and outd= ated.. It was published on 2007. > > >>> > > >>> http://www.synthworks.com/papers/vhdl_fixedfloat_lewis_bishop_date_= 2007..pdf > > >>> > > >>> Thank you. > > >>> > > >>> > > >>> Weng > > >> > > >> I am not an expert for VHDL, but I would be really surprised if the = tools will be able to synthesize this data type. This VHDL package is meant= to be used for simulation. > > >> > > >> Xilinx has an IP which does various operations on floating point: ht= tp://www.xilinx.com/products/intellectual-property/floating_pt.html. I woul= d also suggest checking out Vivado HLS since (at least IMHO) gives nice pro= ductivity boost when writing floating-point signal processing modules. > > > > > > Hi Jan, > > > > > > very good, what you provided is what I want. But can you give more in= fo about Vivado HLS? A pdf document link for Vivado HLS? > >=20 > > You should be contacting the synthesis and FPGA vendors. > >=20 > > --=20 > >=20 > > Rick >=20 > Xilinx Vivado synthesis supports VHDL-2008, by enabling a Tcl command: > set_param project.enableVHDL2008 1 >=20 > After entering this command, the Project Settings dialogue box will show = a checkbox "Use VHDL 2008". Check this to VHDL-2008 support. >=20 > Then you can set individual files to use the "VHDL 2008" file type. >=20 > However, be warned that there is currently a problem with getting the IEE= E floating point package (float_pkg) to work with this option enabled. Howe= ver, previous versions of Vivado, I mean those that have not yet supported = VHDL-2008, do actually support the float_pkg library (weird I know). >=20 > I have filed a case with Xilinx previously, but I'm not sure of its curre= nt status. I believe they are working on this. >=20 > If you want to use float_pkg, you need to NOT use the "VHDL 2008" option = for now. With this, you can use the "*" multiplication symbol to do floatin= g-point multiplications. >=20 > Refer to Chapter 5 (pgs. 177 onwards) of the Vivado Design Suite User Gui= de (v2015.3). > http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_3/ug901= -vivado-synthesis.pdf >=20 > -daniel Hi Danial, What you provided is what I want. Thank you, Weng

Hi, I have a constant N = 27, how to define a counter whose width is big enough to hold integer 27? Or how to get a constant = log N? Where "log" is a logarithm with base 2. Thank you. Weng

Weng Tianxiang wrote: > Hi, > > I have a constant N = 27, how to define a counter whose width is big enough to hold integer 27? > > Or how to get a constant = log N? Where "log" is a logarithm with base 2. > > Thank you. > > Weng The function you want is the ceiling of log base 2. In Verilog this is $clog2(). If you don't have a similar function it's quite easy to make, since it's generally accomplished by shifting the input value right until it becomes zero and counting the shifts required to get there. -- Gabor

On Friday, March 4, 2016 at 5:14:32 AM UTC-8, Weng Tianxiang wrote: > On Tuesday, February 23, 2016 at 4:16:51 AM UTC-8, Daniel Kho wrote: > > On Tuesday, 23 February 2016 14:40:15 UTC+8, rickman wrote: > > > On 2/21/2016 7:14 PM, Weng Tianxiang wrote: > > > > On Sunday, February 21, 2016 at 1:58:03 PM UTC-8, Jan Marjanovi=C4= =8D wrote: > > > >> On Sunday, February 21, 2016 at 8:47:38 PM UTC+1, Weng Tianxiang w= rote: > > > >>> Hi, > > > >>> > > > >>> I need a full code example on how to use a floating multiplier on= FPGA for VHDL-2008. What is the document name from XILINX? > > > >>> > > > >>> Jim's slides on floating multiplier are good, but not full and ou= tdated.. It was published on 2007. > > > >>> > > > >>> http://www.synthworks.com/papers/vhdl_fixedfloat_lewis_bishop_dat= e_2007..pdf > > > >>> > > > >>> Thank you. > > > >>> > > > >>> > > > >>> Weng > > > >> > > > >> I am not an expert for VHDL, but I would be really surprised if th= e tools will be able to synthesize this data type. This VHDL package is mea= nt to be used for simulation. > > > >> > > > >> Xilinx has an IP which does various operations on floating point: = http://www.xilinx.com/products/intellectual-property/floating_pt.html. I wo= uld also suggest checking out Vivado HLS since (at least IMHO) gives nice p= roductivity boost when writing floating-point signal processing modules. > > > > > > > > Hi Jan, > > > > > > > > very good, what you provided is what I want. But can you give more = info about Vivado HLS? A pdf document link for Vivado HLS? > > >=20 > > > You should be contacting the synthesis and FPGA vendors. > > >=20 > > > --=20 > > >=20 > > > Rick > >=20 > > Xilinx Vivado synthesis supports VHDL-2008, by enabling a Tcl command: > > set_param project.enableVHDL2008 1 > >=20 > > After entering this command, the Project Settings dialogue box will sho= w a checkbox "Use VHDL 2008". Check this to VHDL-2008 support. > >=20 > > Then you can set individual files to use the "VHDL 2008" file type. > >=20 > > However, be warned that there is currently a problem with getting the I= EEE floating point package (float_pkg) to work with this option enabled. Ho= wever, previous versions of Vivado, I mean those that have not yet supporte= d VHDL-2008, do actually support the float_pkg library (weird I know). > >=20 > > I have filed a case with Xilinx previously, but I'm not sure of its cur= rent status. I believe they are working on this. > >=20 > > If you want to use float_pkg, you need to NOT use the "VHDL 2008" optio= n for now. With this, you can use the "*" multiplication symbol to do float= ing-point multiplications. > >=20 > > Refer to Chapter 5 (pgs. 177 onwards) of the Vivado Design Suite User G= uide (v2015.3). > > http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_3/ug9= 01-vivado-synthesis.pdf > >=20 > > -daniel >=20 > Hi Danial, >=20 > What you provided is what I want. >=20 > Thank you, >=20 > Weng Hi Danial, I have read a Xilinx paper "Floating-Point Operator v7.1 LogiCORE IP Produc= t Guide", PG060 November 18, 2015, now another similar one "Vivado Design S= uite User Guide", UG901 (v2015.3) September 30, 2015. Can you describe the differences between them, especially which one must be= read and which one can be skipped? Thank you. Weng

On Friday, March 4, 2016 at 5:34:42 AM UTC-8, Gabor wrote: > Weng Tianxiang wrote: > > Hi, > > > > I have a constant N = 27, how to define a counter whose width is big enough to hold integer 27? > > > > Or how to get a constant = log N? Where "log" is a logarithm with base 2. > > > > Thank you. > > > > Weng > > The function you want is the ceiling of log base 2. In Verilog > this is $clog2(). If you don't have a similar function it's quite > easy to make, since it's generally accomplished by shifting the > input value right until it becomes zero and counting the shifts > required to get there. > > -- > Gabor Hi Gabor, I want to use the (log N) to be the width of a counter: signal Count : unsigned((log N)-1 downto 0); -- it can hold a known largest number N Thank you. Weng

On Friday, March 4, 2016 at 1:20:19 PM UTC-5, Weng Tianxiang wrote: > > I want to use the (log N) to be the width of a counter: > > signal Count : unsigned((log N)-1 downto 0); -- it can hold a known largest number N > What exactly is the issue? ieee.math_real defines a log2 function that can be used to define the upper bound. Actually what you want is ceil(log2(N)) Kevin

On 3/4/2016 1:20 PM, Weng Tianxiang wrote: > On Friday, March 4, 2016 at 5:34:42 AM UTC-8, Gabor wrote: >> Weng Tianxiang wrote: >>> Hi, >>> >>> I have a constant N = 27, how to define a counter whose width is big enough to hold integer 27? >>> >>> Or how to get a constant = log N? Where "log" is a logarithm with base 2. >>> >>> Thank you. >>> >>> Weng >> >> The function you want is the ceiling of log base 2. In Verilog >> this is $clog2(). If you don't have a similar function it's quite >> easy to make, since it's generally accomplished by shifting the >> input value right until it becomes zero and counting the shifts >> required to get there. >> >> -- >> Gabor > > Hi Gabor, > > I want to use the (log N) to be the width of a counter: > > signal Count : unsigned((log N)-1 downto 0); -- it can hold a known largest number N I don't think you need a ceiling function. I think you need a floor function and add 1. log2(8) = 3.0, log2(9) = 3.17, both need 4 bits to represent them in binary. A ceiling function will return 3 for 8 and 4 for 9. So it would be signal Count : unsigned(flog2(N) downto 0); Writing flog2(N) should be trivial. -- Rick

On 3/4/2016 3:08 PM, KJ wrote: > On Friday, March 4, 2016 at 1:20:19 PM UTC-5, Weng Tianxiang wrote: >> >> I want to use the (log N) to be the width of a counter: >> >> signal Count : unsigned((log N)-1 downto 0); -- it can hold a known largest number N >> > > What exactly is the issue? ieee.math_real defines a log2 function that can be used to define the upper bound. Actually what you want is > ceil(log2(N)) Isn't it a floor function that is required? Floor and add one. No? -- Rick

In article <nbcq1j$i1q$1@dont-email.me>, rickman <gnuarm@gmail.com> wrote: >On 3/4/2016 1:20 PM, Weng Tianxiang wrote: >> On Friday, March 4, 2016 at 5:34:42 AM UTC-8, Gabor wrote: >>> Weng Tianxiang wrote: >>>> Hi, >>>> >>>> I have a constant N = 27, how to define a counter whose width is big enough to hold integer 27? >>>> >>>> Or how to get a constant = log N? Where "log" is a logarithm with base 2. >>>> >>>> Thank you. >>>> >>>> Weng >>> >>> The function you want is the ceiling of log base 2. In Verilog >>> this is $clog2(). If you don't have a similar function it's quite >>> easy to make, since it's generally accomplished by shifting the >>> input value right until it becomes zero and counting the shifts >>> required to get there. >>> >>> -- >>> Gabor >> >> Hi Gabor, >> >> I want to use the (log N) to be the width of a counter: >> >> signal Count : unsigned((log N)-1 downto 0); -- it can hold a known largest number N > >I don't think you need a ceiling function. I think you need a floor >function and add 1. log2(8) = 3.0, log2(9) = 3.17, both need 4 bits to >represent them in binary. A ceiling function will return 3 for 8 and 4 >for 9. So it would be ceiling(log2(8+1)) = 4; What's the trouble? Regards, Mark

On 3/4/2016 5:03 PM, Mark Curry wrote: > In article <nbcq1j$i1q$1@dont-email.me>, rickman <gnuarm@gmail.com> wrote: >> On 3/4/2016 1:20 PM, Weng Tianxiang wrote: >>> On Friday, March 4, 2016 at 5:34:42 AM UTC-8, Gabor wrote: >>>> Weng Tianxiang wrote: >>>>> Hi, >>>>> >>>>> I have a constant N = 27, how to define a counter whose width is big enough to hold integer 27? >>>>> >>>>> Or how to get a constant = log N? Where "log" is a logarithm with base 2. >>>>> >>>>> Thank you. >>>>> >>>>> Weng >>>> >>>> The function you want is the ceiling of log base 2. In Verilog >>>> this is $clog2(). If you don't have a similar function it's quite >>>> easy to make, since it's generally accomplished by shifting the >>>> input value right until it becomes zero and counting the shifts >>>> required to get there. >>>> >>>> -- >>>> Gabor >>> >>> Hi Gabor, >>> >>> I want to use the (log N) to be the width of a counter: >>> >>> signal Count : unsigned((log N)-1 downto 0); -- it can hold a known largest number N >> >> I don't think you need a ceiling function. I think you need a floor >> function and add 1. log2(8) = 3.0, log2(9) = 3.17, both need 4 bits to >> represent them in binary. A ceiling function will return 3 for 8 and 4 >> for 9. So it would be > > ceiling(log2(8+1)) = 4; > > What's the trouble? This can work if you add the 1 first, but the number you want is 3. So you have to subtract 1 from this result. Which is simpler? Personally I prefer the simpler approach of flog2(N) rather than clog2(N+1)-1 to get where this needs to go. flog2 is a very simple function to write. If you use floating point routines for log2 and ceiling you need to then convert to integer. Are there integer functions for these routines or do you need to write them? I guess that wouldn't make sense since log2 either returns a floating point number or does some form of truncation or rounding. -- Rick

On Friday, March 4, 2016 at 2:27:55 PM UTC-8, rickman wrote: > On 3/4/2016 5:03 PM, Mark Curry wrote: > > In article <nbcq1j$i1q$1@dont-email.me>, rickman <gnuarm@gmail.com> wrote: > >> On 3/4/2016 1:20 PM, Weng Tianxiang wrote: > >>> On Friday, March 4, 2016 at 5:34:42 AM UTC-8, Gabor wrote: > >>>> Weng Tianxiang wrote: > >>>>> Hi, > >>>>> > >>>>> I have a constant N = 27, how to define a counter whose width is big enough to hold integer 27? > >>>>> > >>>>> Or how to get a constant = log N? Where "log" is a logarithm with base 2. > >>>>> > >>>>> Thank you. > >>>>> > >>>>> Weng > >>>> > >>>> The function you want is the ceiling of log base 2. In Verilog > >>>> this is $clog2(). If you don't have a similar function it's quite > >>>> easy to make, since it's generally accomplished by shifting the > >>>> input value right until it becomes zero and counting the shifts > >>>> required to get there. > >>>> > >>>> -- > >>>> Gabor > >>> > >>> Hi Gabor, > >>> > >>> I want to use the (log N) to be the width of a counter: > >>> > >>> signal Count : unsigned((log N)-1 downto 0); -- it can hold a known largest number N > >> > >> I don't think you need a ceiling function. I think you need a floor > >> function and add 1. log2(8) = 3.0, log2(9) = 3.17, both need 4 bits to > >> represent them in binary. A ceiling function will return 3 for 8 and 4 > >> for 9. So it would be > > > > ceiling(log2(8+1)) = 4; > > > > What's the trouble? > > This can work if you add the 1 first, but the number you want is 3. So > you have to subtract 1 from this result. Which is simpler? > > Personally I prefer the simpler approach of flog2(N) rather than > clog2(N+1)-1 to get where this needs to go. flog2 is a very simple > function to write. If you use floating point routines for log2 and > ceiling you need to then convert to integer. Are there integer > functions for these routines or do you need to write them? I guess that > wouldn't make sense since log2 either returns a floating point number or > does some form of truncation or rounding. > > -- > > Rick Hi Gabor, KJ, Rich and Mark, After your posts, I realized that a user-defined function's returned integer value can be used as boundary limit!!! Before the post I didn't know it. So I decided to accept Gabor's method to write an integer function log2(integer N) in my design so that it can be repeatedly used later for my life. Thank you. Weng Here is the code: -- = floor of log2(); log2(27) = 5. function log2(integer: N) return integer is variable K : integer; variable M : integer; -- = M mod 2 begin K := 0; M := N; loop1: while M /= 0 loop M := M mod 2; -- it cannot use M := M srl 2, because N is an integer K := K+1; end loop; return K; end log2; -- to be debugged

On 3/4/2016 8:01 PM, Weng Tianxiang wrote: > On Friday, March 4, 2016 at 2:27:55 PM UTC-8, rickman wrote: >> On 3/4/2016 5:03 PM, Mark Curry wrote: >>> In article <nbcq1j$i1q$1@dont-email.me>, rickman <gnuarm@gmail.com> wrote: >>>> On 3/4/2016 1:20 PM, Weng Tianxiang wrote: >>>>> On Friday, March 4, 2016 at 5:34:42 AM UTC-8, Gabor wrote: >>>>>> Weng Tianxiang wrote: >>>>>>> Hi, >>>>>>> >>>>>>> I have a constant N = 27, how to define a counter whose width is big enough to hold integer 27? >>>>>>> >>>>>>> Or how to get a constant = log N? Where "log" is a logarithm with base 2. >>>>>>> >>>>>>> Thank you. >>>>>>> >>>>>>> Weng >>>>>> >>>>>> The function you want is the ceiling of log base 2. In Verilog >>>>>> this is $clog2(). If you don't have a similar function it's quite >>>>>> easy to make, since it's generally accomplished by shifting the >>>>>> input value right until it becomes zero and counting the shifts >>>>>> required to get there. >>>>>> >>>>>> -- >>>>>> Gabor >>>>> >>>>> Hi Gabor, >>>>> >>>>> I want to use the (log N) to be the width of a counter: >>>>> >>>>> signal Count : unsigned((log N)-1 downto 0); -- it can hold a known largest number N >>>> >>>> I don't think you need a ceiling function. I think you need a floor >>>> function and add 1. log2(8) = 3.0, log2(9) = 3.17, both need 4 bits to >>>> represent them in binary. A ceiling function will return 3 for 8 and 4 >>>> for 9. So it would be >>> >>> ceiling(log2(8+1)) = 4; >>> >>> What's the trouble? >> >> This can work if you add the 1 first, but the number you want is 3. So >> you have to subtract 1 from this result. Which is simpler? >> >> Personally I prefer the simpler approach of flog2(N) rather than >> clog2(N+1)-1 to get where this needs to go. flog2 is a very simple >> function to write. If you use floating point routines for log2 and >> ceiling you need to then convert to integer. Are there integer >> functions for these routines or do you need to write them? I guess that >> wouldn't make sense since log2 either returns a floating point number or >> does some form of truncation or rounding. >> >> -- >> >> Rick > > Hi Gabor, KJ, Rich and Mark, > > After your posts, I realized that a user-defined function's returned integer value can be used as boundary limit!!! Before the post I didn't know it. > > So I decided to accept Gabor's method to write an integer function log2(integer N) in my design so that it can be repeatedly used later for my life. > > Thank you. > > Weng > > Here is the code: > > -- = floor of log2(); log2(27) = 5. > > function log2(integer: N) return integer is > variable K : integer; > variable M : integer; -- = M mod 2 > begin > K := 0; > M := N; > loop1: while M /= 0 loop > M := M mod 2; -- it cannot use M := M srl 2, because N is an integer > K := K+1; > end loop; > > return K; > end log2; > > -- to be debugged I can't recall the last time I wrote even a simple program that was 100% correct the first time. I think when you debug your program it will need to be M := M / 2; You might want to make your comment, "it cannot use M := M srl 1, because N is an integer" -- Rick

On 3/5/2016 12:23 AM, rickman wrote: > On 3/4/2016 8:01 PM, Weng Tianxiang wrote: >> On Friday, March 4, 2016 at 2:27:55 PM UTC-8, rickman wrote: >>> On 3/4/2016 5:03 PM, Mark Curry wrote: >>>> In article <nbcq1j$i1q$1@dont-email.me>, rickman <gnuarm@gmail.com> >>>> wrote: >>>>> On 3/4/2016 1:20 PM, Weng Tianxiang wrote: >>>>>> On Friday, March 4, 2016 at 5:34:42 AM UTC-8, Gabor wrote: >>>>>>> Weng Tianxiang wrote: >>>>>>>> Hi, >>>>>>>> >>>>>>>> I have a constant N = 27, how to define a counter whose width is >>>>>>>> big enough to hold integer 27? >>>>>>>> >>>>>>>> Or how to get a constant = log N? Where "log" is a logarithm >>>>>>>> with base 2. >>>>>>>> >>>>>>>> Thank you. >>>>>>>> >>>>>>>> Weng >>>>>>> >>>>>>> The function you want is the ceiling of log base 2. In Verilog >>>>>>> this is $clog2(). If you don't have a similar function it's quite >>>>>>> easy to make, since it's generally accomplished by shifting the >>>>>>> input value right until it becomes zero and counting the shifts >>>>>>> required to get there. >>>>>>> >>>>>>> -- >>>>>>> Gabor >>>>>> >>>>>> Hi Gabor, >>>>>> >>>>>> I want to use the (log N) to be the width of a counter: >>>>>> >>>>>> signal Count : unsigned((log N)-1 downto 0); -- it can hold a >>>>>> known largest number N >>>>> >>>>> I don't think you need a ceiling function. I think you need a floor >>>>> function and add 1. log2(8) = 3.0, log2(9) = 3.17, both need 4 >>>>> bits to >>>>> represent them in binary. A ceiling function will return 3 for 8 >>>>> and 4 >>>>> for 9. So it would be >>>> >>>> ceiling(log2(8+1)) = 4; >>>> >>>> What's the trouble? >>> >>> This can work if you add the 1 first, but the number you want is 3. So >>> you have to subtract 1 from this result. Which is simpler? >>> >>> Personally I prefer the simpler approach of flog2(N) rather than >>> clog2(N+1)-1 to get where this needs to go. flog2 is a very simple >>> function to write. If you use floating point routines for log2 and >>> ceiling you need to then convert to integer. Are there integer >>> functions for these routines or do you need to write them? I guess that >>> wouldn't make sense since log2 either returns a floating point number or >>> does some form of truncation or rounding. >>> >>> -- >>> >>> Rick >> >> Hi Gabor, KJ, Rich and Mark, >> >> After your posts, I realized that a user-defined function's returned >> integer value can be used as boundary limit!!! Before the post I >> didn't know it. >> >> So I decided to accept Gabor's method to write an integer function >> log2(integer N) in my design so that it can be repeatedly used later >> for my life. >> >> Thank you. >> >> Weng >> >> Here is the code: >> >> -- = floor of log2(); log2(27) = 5. >> >> function log2(integer: N) return integer is >> variable K : integer; >> variable M : integer; -- = M mod 2 >> begin >> K := 0; >> M := N; >> loop1: while M /= 0 loop >> M := M mod 2; -- it cannot use M := M srl 2, because N is an >> integer >> K := K+1; >> end loop; >> >> return K; >> end log2; >> >> -- to be debugged > > I can't recall the last time I wrote even a simple program that was 100% > correct the first time. I think when you debug your program it will > need to be M := M / 2; > > You might want to make your comment, "it cannot use M := M srl 1, > because N is an integer" Oh yeah, you also need to change "while M /= 0" to "while M > 1". Otherwise you will get a return value of 1 for 1, 2 for 2, 3 for 4, 4 for 8, etc, which are all 1 more than the correct value and not optimal for your use. -- Rick

On Friday, 4 March 2016 21:42:29 UTC+8, Weng Tianxiang wrote: > On Friday, March 4, 2016 at 5:14:32 AM UTC-8, Weng Tianxiang wrote: > > On Tuesday, February 23, 2016 at 4:16:51 AM UTC-8, Daniel Kho wrote: > > > On Tuesday, 23 February 2016 14:40:15 UTC+8, rickman wrote: > > > > On 2/21/2016 7:14 PM, Weng Tianxiang wrote: > > > > > On Sunday, February 21, 2016 at 1:58:03 PM UTC-8, Jan Marjanovi= =C4=8D wrote: > > > > >> On Sunday, February 21, 2016 at 8:47:38 PM UTC+1, Weng Tianxiang= wrote: > > > > >>> Hi, > > > > >>> > > > > >>> I need a full code example on how to use a floating multiplier = on FPGA for VHDL-2008. What is the document name from XILINX? > > > > >>> > > > > >>> Jim's slides on floating multiplier are good, but not full and = outdated.. It was published on 2007. > > > > >>> > > > > >>> http://www.synthworks.com/papers/vhdl_fixedfloat_lewis_bishop_d= ate_2007..pdf > > > > >>> > > > > >>> Thank you. > > > > >>> > > > > >>> > > > > >>> Weng > > > > >> > > > > >> I am not an expert for VHDL, but I would be really surprised if = the tools will be able to synthesize this data type. This VHDL package is m= eant to be used for simulation. > > > > >> > > > > >> Xilinx has an IP which does various operations on floating point= : http://www.xilinx.com/products/intellectual-property/floating_pt.html. I = would also suggest checking out Vivado HLS since (at least IMHO) gives nice= productivity boost when writing floating-point signal processing modules. > > > > > > > > > > Hi Jan, > > > > > > > > > > very good, what you provided is what I want. But can you give mor= e info about Vivado HLS? A pdf document link for Vivado HLS? > > > >=20 > > > > You should be contacting the synthesis and FPGA vendors. > > > >=20 > > > > --=20 > > > >=20 > > > > Rick > > >=20 > > > Xilinx Vivado synthesis supports VHDL-2008, by enabling a Tcl command= : > > > set_param project.enableVHDL2008 1 > > >=20 > > > After entering this command, the Project Settings dialogue box will s= how a checkbox "Use VHDL 2008". Check this to VHDL-2008 support. > > >=20 > > > Then you can set individual files to use the "VHDL 2008" file type. > > >=20 > > > However, be warned that there is currently a problem with getting the= IEEE floating point package (float_pkg) to work with this option enabled. = However, previous versions of Vivado, I mean those that have not yet suppor= ted VHDL-2008, do actually support the float_pkg library (weird I know). > > >=20 > > > I have filed a case with Xilinx previously, but I'm not sure of its c= urrent status. I believe they are working on this. > > >=20 > > > If you want to use float_pkg, you need to NOT use the "VHDL 2008" opt= ion for now. With this, you can use the "*" multiplication symbol to do flo= ating-point multiplications. > > >=20 > > > Refer to Chapter 5 (pgs. 177 onwards) of the Vivado Design Suite User= Guide (v2015.3). > > > http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_3/u= g901-vivado-synthesis.pdf > > >=20 > > > -daniel > >=20 > > Hi Danial, > >=20 > > What you provided is what I want. > >=20 > > Thank you, > >=20 > > Weng >=20 > Hi Danial, >=20 > I have read a Xilinx paper "Floating-Point Operator v7.1 LogiCORE IP Prod= uct Guide", PG060 November 18, 2015, now another similar one "Vivado Design= Suite User Guide", UG901 (v2015.3) September 30, 2015. >=20 > Can you describe the differences between them, especially which one must = be read and which one can be skipped? >=20 > Thank you. >=20 > Weng I haven't read the PG060 Floating-Point Operator product guide, as I don't = have a need to read it. I only read user guides on IP Cores (such as the Lo= giCore IP products) only when I have a need to use those IPs. As far as floating-point or fixed-point arithmetic is concerned, I'd rather= stick with the IEEE float_pkg and fixed_pkg standardised functions. This m= eans, if a tool supports this standard, then all you need is to use these f= unctions as if they were standard IEEE functions. Use them normally in your= behavioural VHDL code. This means that I don't use the Floating-Point LogiCORE IP directly, howeve= r, XST may infer these IPs from the behavioural VHDL. LogiCore (or any third-party) IP cores usually will require you to instanti= ate those IPs in your VHDL, and makes your code more structural than behavi= oural. For floating/fixed-point arithmetic, I find it easier and better to = write the equations in behavioural VHDL, using the standard IEEE functions. - dan

On Saturday, 5 March 2016 04:08:17 UTC+8, KJ wrote: > On Friday, March 4, 2016 at 1:20:19 PM UTC-5, Weng Tianxiang wrote: > > > > I want to use the (log N) to be the width of a counter: > > > > signal Count : unsigned((log N)-1 downto 0); -- it can hold a known largest number N > > > > What exactly is the issue? ieee.math_real defines a log2 function that can be used to define the upper bound. Actually what you want is > ceil(log2(N)) > > Kevin Yes, KJ is right. In code, this would look like (I use this very often in synthesizable code): signal cnt: u_unsigned(positive(ceil(log2(real(N))))-1 downto 0);

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