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Perhaps we should consider tactics that some other newsgroups do and give technical sounding answers that people like aboob will hand in without bothering to think that are obviously false to anyone who's loosened up the spine a bit on their text book. rk ========================== Ray Andraka wrote: > When you post your homework problems, you should put the post the figure too. > Perhaps you ought to listen a little better in class and read your class notes > or text. > > annoob wrote: > > > I am a college student who is interested in computer architecture. However, > > I have some question about the Carry-Select Adder. > > > > Question 1: What is the carry-select adder in data path? > > Question 2: How we design an adder that uses MUXes and 1-Bit address that > > can run as fast as O(log n)? > > > > Thank you in advance for your help > > > > ANNOOB > > annoob@email.msn.com > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randrakaArticle: 20526
murray@pa.dec.com (Hal Murray) writes: > > Where to start looking? We suspect an erroneus flag in the FIFO, so > > that an extra packet delimiter is inserted in output FIFO. > > How about ripping the guts out of your FPGA design so you > can focus on the external timings? Do you think external timing can produce this symmetric cases? Nothing is impossibel, sure, but it doesn't strike me as the most likely cause. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 20527
On Sun, 13 Feb 2000 07:40:07 GMT, Peter Alfke <palfke@earthlink.net> wrote: | | |John Larkin wrote:Hi, | |> |> we've done a few systems with one or two Xilinx fpga's which are |> loaded at powerup time by a CPU, generally an MC68332. We use a single |> eprom which holds the uP program and the config data for all the |> FPGAs. We use both fpga's in slave serial mode. The CPU needs N + 2 |> parallel port pins to program N fpga's: shared serial data DIN, shared |> clock CCLK, and one 'program' pin per chip. Works fine, and we can |> ship a customer a single eprom chip to upgrade his uP code and the |> fpga's. A 4013XL or an XCS20 Spartan configures in half a second |> maybe. |> |> John | |I suppose this works, but it is very peculiar. |It seems to be optimized for individual reprogramming at arbitrary times. | No, it was optimized for simplicity and reliability, but that would work too. |The more conventional method would daisy-chain the two FPGAs: |interconnecting CCLKs, but have the first chip's Dout feed the next |chip's Din, as describes in many places in the Xilinx data book. We felt that troubleshooting would be easier (especially for our test department, who like to replace chips as a first-order diagnostic technique) if chip loading was independent. The uP software is more modular this way, too. |Configuration speed, in this application, is determined by the |microprocessor. From the FPGA's point of view, you can run CCLK at 10 |MHz, which configures two daisy-chained XC4013XLs ( each 393 632 bits ) |in less than 80 ms. At slower CCLK rates it takes proportionally longer. We're software bit-pumping here, through a parallel port. | |I recommend reading pages 14-30 through 45 of the Xikinx 1999 data book. We did this work a couple of years ago, so we didn't have the 1999 book. Frankly, what we did have in the way of documentation was very badly written and quite confusing, both the databooks and appnotes. We spent a *lot* of hours getting everything to work. I hope things are better now. | |Peter Alfke, Xilinx Applications | | | JohnArticle: 20528
Hi - I don't know how many of you use the Xilinx M2.1 floorplanner. If you do, I have a question for you. Yesterday I used the floorplanner to place portions of a schematic-based XCS30XL design, and managed to go from a design that failed route after 1-1/2 hours (didn't complete route and didn't meet timing on the routed nets) to a design that routed and met all timing constraints in 40 minutes. So, I'm happy with the results, but was puzzled by the fact that the Xilinx tools moved some of the cells that I'd placed. Any RPMs that I placed stayed put, but cells that I'd moved individually into the placement window were sometimes in new places after routing. You could see that the place and route tools had kept the cells more or less where I'd placed them, but moved some cells around. Is this expected behavior when using the floorplanner? If so, what's to keep I/O pin assignments from moving? Thanks, Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 20529
Hi, It might be worth adding here, regarding John's reference to "N+2 port pins needed" to program N FPGA's, that many of these pins can be reused for I/O after programming is complete. THe limiting case is 1 pin for many FPGA's, as described below. For example, I make a data acquisition unit that contains a CPU with 8-bit bus (AD0-7,-WR,-RD, ALE, etc) but that is always attached to a PC parallel port. The unit also has a CPLD(Xilinx XC95108) for the PC Interface, and two FPGA's (XCS10 and XCS10XL) for communication with other instruments. There is no ROM chip on board; the CPU uses block ROM in one of the FPGA's to boot. This allows the unit to exhibit completeley different functionalities merely by downloading different FPGA configurations and CPU programs, the latter being bit-banged to RAM after FPGA configuration. On power-up, the CPLD tristates the CPU bus, then configures the two FPGA's using a single dedicated PROGRAM pin, with the CCLK being sent over the -WR bus line, the Din's over AD0 and AD1, Douts read back over AD2 and AD3, and the -LDC pins attached to AD4 and AD5. So, the two FPGAs are loaded via serial mode, but concurrently. The FPGA with the smaller bitstream gets sent 1's while the other is finishing up. After configuration, I get to use the Dins, Douts, and -LDCs as the data bus connections to the FPGAs. Total pin cost is 1 pin, the dedicated PROGRAM pin from the CPLD. Hope this adds to the comp.arch.fpga "signal" and not to the "noise", Ian McLaren McLaren Research Mountain View, CA In article <fi2mOJWK8G9x1WyYrTjryqcwwuTl@4ax.com>, John Larkin <jjlarkin@highlandSnipSniptechnology.com> wrote: > On Fri, 11 Feb 2000 15:41:36 GMT, elynum@my-deja.com wrote: > > |How would I go about programming 2 xilinx fpga's on a single board? > |Would I need 2 separate EEPROM chips(ATMEl) or just one? How would > |I go about doing it with a microprocessor 8051 or 860? What would I > |need to do this? > | > | > |Sent via Deja.com http://www.deja.com/ > |Before you buy. > > Hi, > > we've done a few systems with one or two Xilinx fpga's which are > loaded at powerup time by a CPU, generally an MC68332. We use a single > eprom which holds the uP program and the config data for all the > FPGAs. We use both fpga's in slave serial mode. The CPU needs N + 2 > parallel port pins to program N fpga's: shared serial data DIN, shared > clock CCLK, and one 'program' pin per chip. Works fine, and we can > ship a customer a single eprom chip to upgrade his uP code and the > fpga's. A 4013XL or an XCS20 Spartan configures in half a second > maybe. > > John > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20530
John Larkin wrote: > <snip>We did this work a couple of years ago, so we didn't have the 1999 > book. Frankly, what we did have in the way of documentation was very > badly written and quite confusing, both the databooks and appnotes. We > spent a *lot* of hours getting everything to work. I hope things are > better now. > Ouch, that hurts, since I was the one writing most of this stuff. Anyhow, I am a grown boy and can stand criticism. But, to turn this into something positive: I would like to hear from users who find Xilinx FPGA hardware documentation difficult to understand or confusing. We can fix that ! Peter Alfke, Xilinx Applications e-mail: peter@xilinx.comArticle: 20531
Hi all, I have used logiblox to create a simple 32-bit adder and have succesfully analyzed it using vhdlan. But, when I used vhdldbx to do the functional simulation, it failed badly. I got error msg somethhing like unable to write or file is write protected. Can some tell me the proper way to do functional simulation? Thank you a lot! Regards Teik-MingArticle: 20532
On Mon, 14 Feb 2000 00:26:06 GMT, Peter Alfke <palfke@earthlink.net> wrote: > > >John Larkin wrote: > >> <snip>We did this work a couple of years ago, so we didn't have the 1999 >> book. Frankly, what we did have in the way of documentation was very >> badly written and quite confusing, both the databooks and appnotes. We >> spent a *lot* of hours getting everything to work. I hope things are >> better now. >> > >Ouch, that hurts, since I was the one writing most of this stuff. >Anyhow, I am a grown boy and can stand criticism. >But, to turn this into something positive: >I would like to hear from users who find Xilinx FPGA hardware documentation >difficult to understand or confusing. >We can fix that ! > >Peter Alfke, Xilinx Applications >e-mail: peter@xilinx.com Peter, Tom McLaughlin's Feb 10 thread also includes some complaints about config documentation. I think a few clear, simple, and focussed (ie, not too general and not covering multiple devices) appnotes would save Xilinx's customers literally tens - maybe hundreds - of thousands of hours of misery. This stuff shouldn't even be in the databook, because it's too terse there and just makes trouble. The uP: Xilinx config process turned out to be really clean and simple... once we figured it out! We had to write a few of our own rom-build utilities, which, in my opinion, Xilinx should have furnished. JohnArticle: 20533
Could anyone give me an idea if the following would be possible to do with one of the many programable logic device I see mentioned here? VMS hashes user passwords using a polynomial over Zp. p = 2^64-59 and the polynomial looks like this: f(x) = x ^16777213 + A * x ^16777153 + B * x ^3 + C * x^2 + D * x + E (mod p) On say a 600Mhz PIII I can evaluate 0.4 million values of this polynomial / sec. Noting that 2 is a primitive root mod p we can make a search of the whole space much faster by calculating like this: f(0), f(1), f(2), f(4), ... f(2^r),..., f(2^(p-2) We can use each term calculated for f(2^r) to calculate the terms for f(2^(r+1)) just by multiplying by the constants 2^16777213, 2^16777153, 8,4,2 and 1 (mod p). So to search then entire 64 bit space of the problem involves doing / point: 2 x 64 bit multiplies mod p where the multiplier is a constant with no special structure and 3 small constant multiplies (that can even be converted to additions) followed by 5 additions (all mod p). Once again on a 600Mhz PIII I can do something like 4 million points / sec. Is this the kind of problem thats easily done with an FPGA etc? I would need to be able to fit many of these on a single device to divide the problem space up. What current devices are available that would be best suited to such a task? Are they affordable by someone who just wants to play about like this? Thanks. Neill.Article: 20534
On Sun, 13 Feb 2000 08:24:37, TS Kutty <sthelapu@ececs.uc.edu> wrote: > This is a multi-part message in MIME format. > Hi, > Thanks for reply. > The code that I am using is of the blank architecture. I am attaching > the code that I am using. It would be great if you give some pointers > regarding the mistakes that I am commitingin the code PLEASE! Do not post attachments (binaries, MIME junk, or any HTML) to the USENET text only groups (which all of the comp.* hierarchy is). This is really rotten protocol and will cause grief to many. Please, just don't do it! ---- KeithArticle: 20535
Hi, Is there any way to use the LUT by VHDL code, that is to write a VHDL code "without using the FPGA vendor specific library" that I can know in advance that it will be synthesized to LUT or is it just the synthesizer problem? I need this feature because I want to test some techniques I learned about LUT usage Thanks Jamil Khatib OpenIP Organization http://www.openip.org OpenIPCore Project http://www.openip.Article: 20536
Hi - We have some QuickLogic FPGA programmer heads and base for sale. There is a head for 100 & 144 QFPs, a head for 208 QFPs, and a base unit. These parts are all working, in like-new condition, and recent versions. Equipment located in the San Francisco area. For more information please have a look at our web pages: http://www.gearboxtp.com/for_sale/ql_100144.html http://www.gearboxtp.com/for_sale/ql_208.html http://www.gearboxtp.com/for_sale/ql_base.html thanks - - Jesse Newcomb jesse@GearboxTP.comArticle: 20537
Hi,
I had posted some difficulties regarding the wildforce synthesis
using synopsys, and Xilinx, tools. Has anyone used these tools to
synthesize designs onto the Wildforce board, before? Or should I use
through synplicity tools instead of synopsys??
T.S. Kutty
--
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Article: 20538Hi - We have an HP logic analyzer for sale. This is a 16500-B, with 2 555 logic cards and a 1 Gsa/s 2-ch scope card installed. Please see our page at http://www.gearboxtp.com/for_sale/HP_16500B.html for more information. thanks - - Jesse Newcomb Director of Engineering Gearbox Technical Products San Francisco 650-991-1005Article: 20539
Ray, Thanks for your comments. I know that the FPGA core market is limited and is dominated by big vendors. But would I be right in saying that this market is growing, as the gate/price ratio is increasing (slowly) and with their reconfigurable nature & the time-to-market FPGAs win over ASICs ? To add to it the 'fabrication-from-foundary' cost factor attached to ASICs disappears in FPGAs so that individuals can think of designing complete working systems (an impossible taks when concidering ASICs). I see scenarios where ONLY FPGA's qualify in terms their reconfigurable nature - which are increasing by the day ! Taking all the pros & cons and reasoning from the above points ( I'm still not sure if they're right ! ), would it be a wise decision to concentrate on the business ??? In article <38A6E467.E85DCE58@ids.net>, Ray Andraka <randraka@ids.net> wrote: > Good luck. From what I've seen, people are not willing to pay much for > FPGA based cores. Seems the silicon vendors have set the price > expectations for cores well below the cost to develop, maintain and > support such cores. Optimized FPGA cores are more difficult to design > than comparable cores in ASICs, yet the market price for FPGA cores is > orders of magnitude less than similar ASIC cores. > > fpgaer@my-deja.com wrote: > > > Hi, > > > > wld. appreciate if anyone cld. share their views on launching a co. > > which delivers custom-made FPGA cores ? Wld. the effort be worth in > > terms of time ( & money ) ...... specifically, is there a demanding > > market for FPGA cores ??? > > > > Any comments wld. be highly appreciated !!! > > > > Thanks in advance........ > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20540
-- Don Golding
-- Angelus Research Corp.
-- dgolding@angelusresearch.com
--
-- Public domain Forth Processor design
--
-- I am a newbe at VHDL(5 classes so far) so it is not complete and there
are errors
-- in the code. I am looking for help on this project, so if you are
interested please
-- contact me. The VHDL source code in after this comment section.
--
-- This code represents my current thoughts on designing a Forth Processor
in VHDL.
-- Please review it and email me with your input on either Forth design
issues or
-- VHDL design issues.
--
-- The goal is to build a generic Forth processor that can be included in
VHDL designs.
-- If it could fit into a Xilinx 4005 or 4010 it would be ideal!
-- Forth is really a virtual microprocessor implemented on other various
processors
-- from 68HC11 to VAX machines and supercomputers. You will currently find
Forth used
-- as the driver for PCI hardware in high end Macintosh's and Sun
Workstations.
--
-- This is an attempt to create a real Forth Processor on an FPGA or ASIC
using VHDL.
-- Previous real Forth Microprocessors include: Harris RTX2000, SHABOOM,
F21,etc.
-- The current attempts F21, etc. are trying to make 500mips screamers.
-- There are also people like Dr. Ting using the Schematic editor to create
Forth
-- processors. I wonder how a Schematic designed Forth processor will
compare to a VHDL
-- based design in speed and the number of gates used.
-- I think a straight forward simple design will have considerable
applications
-- when you need a processor included in your FPGA/ASIC design.
-- FPGA operate at 200mhz, I don't know how fast this design will be, but
it's speed
-- should be limited to the external RAM speed when memory access is
required.
-- Internal register to register operations should be 50-200mhz range.
--
-- The preliminary specifications are:
--
-- 16 bit data bus (to save space, could be 8 bit but it would take more
statements)
-- 16 bit address bus
-- by editing the code in the Entity declariations, you implement 32, 64, ?
designs
--
-- Return Stack levels=16
-- Data Stack levels=16 (could be smaller, 4 items could be ok)
-- Output port A is 8 lines
-- Output port B is 8 lines
-- Motorola SPI compatible port (SPI_In,SPI_Out,SPI_Ck,SS/)
--
-- By editing the code in the Entity declariations, you can add serial
ports, parallel
-- ports, adc's or just about anything you can imagine.
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Proc is
port (
DataBus: inout STD_LOGIC_VECTOR (15 downto 0);
OutPortA: out STD_LOGIC_VECTOR (7 downto 0);
OutPortB: out STD_LOGIC_VECTOR (7 downto 0);
OutputA: out STD_LOGIC_LOGIC;
OutputB: out STD_LOGIC_LOGIC;
AddressBus: out STD_LOGIC_VECTOR (15 downto 0);
Reset: in STD_LOGIC;
SPI_In: in STD_LOGIC;
SPI_Out: out STD_LOGIC;
SS: in STD_LOGIC;
SPI_Ck: in STD_LOGIC;
clock: in STD_LOGIC;
rd: out STD_LOGIC;
);
end Proc;
architecture Proc_arch of Proc is
--define op codes
type op_code is(swap, drop, rot, store, cstore, fetch, cfetch,
do, floop, fbegin, funtil, again, plus, minus
times, divide, r@, r>, >r);
-- check these for correct sizes
type data_word is array(15 downto 0) of STD_ULOGIC; --16 bit wide
type Return_stack is array (15 downto 0) of data_word; --16 bits wide, 16
deep
type Data_stack is array (15 downto 0) of data_word; --16 bits wide, 16
deep
type memory_size is range (15 downto 0); --64K max?
constant stack_depth: integer:=16; --16 items max
variable rp of stack_depth; -- return stack pointer
variable dp of stack_depth; -- data stack pointer
variable mp of memory_size; -- memory pointer
variable temp of data_word; -- reg:Temp
variable error of data_word; -- reg:Error code
constant write:bit:=0;
constant read:bit:=1;
constant dstack_overflow:integer:=1; --Errorcodes are defined here
constant dstack_underflow:integer:=2;
constant rstack_overflow:integer:=3;
constant rstack_underflow:integer:=4;
procedure push_dp_stack is
-- dp points the the next stack element not the current one after
operation is completed.
begin
if dp = stack_depth then
error<=dstack_overflow;
else dp <= dp+1;
end if
end push_dp_stack;
procedure pop_dp_stack is
-- dp points the the next stack element not the current one after
operation is completed.
begin
if dp = 0 then
error<=dstack_underflow;
else dp <= dp-1;
end if
end pop_dp_stack;
procedure push_rp_stack is
-- dp points the the next stack element not the current one after
operation is completed.
begin
if rp = 16 then
error<=rstack_overflow;
else rp <= rp+1;
end if
end push_rp_stack;
procedure pop_rp_stack is
-- dp points the the next stack element not the current one after
operation is completed.
begin
if rp = 0 then
error<=rstack_underflow;
else rp <= rp-1;
end if
end pop_rp_stack;
synch: process(clock)
begin
if clock'event and clock='1' then
clock<= not clock; -- need a delay here?
end if;
end process;
-- does this code have to be a process? Would it execute faster if it
weren't?
code: process(clock,reset,mp)
begin
if reset ='0' then
mp:='0';
rp:='0';
dp:='0';
else --how do I code NEXT...inner interpreter...something like this?
rd<=read; --set read/write line to read
addressBus<=mp; --output address
data_stack(dp)<=databus; --read data and place on stack
push_dp_stack;
--data_stack(dp) points to next available location, can use as temp
variable
--before using push_dp_stack or pop_dp_stack procedures.
--each stack are really 16 registers! Stack operations should be real
fast!
case data_stack(dp) is
when swap => --swap top two numbers on data stack
temp <= data_stack(rp);
data_stack(dp) <= data_stack(dp+1);
data_stack(dp+1) <= temp;
mp <= mp+1;
when >r => --move top of data stack to return stack
return_stack(rp) <= data_stack(rp-1);
pop_data_stack;
push_return_stack;
mp <= mp+1;
when r> => --move top of return stack to data stack
data_stack(dp) <= return_stack(rp-1);
pop_return_stack;
push_data_stack;
mp <= mp+1;
when r@ => --move top of return stack to data stack
data_stack(dp) <= return_stack(rp-1);
push_data_stack;
mp <= mp+1;
when drop => --drop top number from data stack
pop_dp_stack;
mp <= mp+1;
when rot => --rotate 3rd numbr to 1st on data stack
temp <= stack(dp);
data_stack(dp) <= data_stack(dp+3);
data_stack(dp+2) <= data_stack(dp+1);
data_stack(dp+1) <= temp;
mp <= mp+1;
when store => -- store 16 bit value to memory
rd<=write;
DataBus <= data_stack(dp);
pop_data_stack;
rd<=read; -- probably need a delay here
mp <= mp+1;
when fetch => -- get 16 bit value from memory
rd<=read;
data_stack(dp) <= dataBus;
push_data_stack;
mp <= mp+1;
when cfetch => -- get 8 bit value from memory
when cstore => -- store 8 bit value to memory
-- loop functions-since looping functions have code within them, it seams
they should be
-- in their own process calling this code process when the loop is not
finished.
when do => -- start of loop, interations and lowest number on
stack
when floop => -- end of loop
when fbegin => -- begin endless loop
when funtil => -- terminate loop if true
when again => -- endless loop
when fexit => -- exit begin/again loop
-- end loop defs
when plus => --add two 16 bit numbers
data_stack(dp-1) <= data_stack(dp) + data_stack(dp+1);
pop_data_stack;
mp <= mp+1;
when minus => --subtract two 16 bit numbers
data_stack(dp-1) <= data_stack(dp+1) - data_stack(dp);
pop_data_stack;
mp <= mp+1;
when times => --multiply two 16 bit numbers
data_stack(dp-1) <= data_stack(dp+1) * data_stack(dp);
pop_data_stack;
mp <= mp+1;
when divide => --divide two 16 bit numbers
data_stack(dp-1) <= data_stack(dp+1) / data_stack(dp);
pop_data_stack;
mp <= mp+1;
end case
end if
end Proc_arch;
Article: 20541Hi, I have used the WildOne (a smaller version of WildForce) board with Synplify and Modelsim without any problems. I am not sure what is causing your problems with Synopsys (is it FPGA express?) The WildOne board (and most likely the WildForce board) is provided with a project template for Synplfify. Have you checked for any project template or synthesis script for Synopsys? Anyway, look at the project templates for Synplify, should be name cpe0.prj or pex.prj. These are ascii files. Look at this files to determine if you have loaded all VHDL files correctly. / Jonas Thor On Mon, 14 Feb 2000 02:27:37 -0500, TS Kutty <sthelapu@ececs.uc.edu> wrote: >Hi, > I had posted some difficulties regarding the wildforce synthesis >using synopsys, and Xilinx, tools. Has anyone used these tools to >synthesize designs onto the Wildforce board, before? Or should I use >through synplicity tools instead of synopsys?? > >T.S. KuttyArticle: 20542
Hi, Currently I'm migrating/implementing schematic entered designs I created for the Xilinx XC4000 series. I'm now implementing these on Virtex devices. However, I'm facing a problem with VCC & GND nets. My designs are heirachical and most sheets contain instances of VCC & GND components. However, when I map these designs to the Virtex architecture (using Foundation v1.5) I'm getting extremely high CLB slice requirements due to extensive instances of VCC and GND. It appears that for each sheet containing a VCC or GND component, when the sheet (or macro created from it) is implemented, the VCC and GND components are implemented exclusively to the particular instance of the sheet. On viewing the design imlementation using EPIC, it is evident that many CLB slices are used exclusively to output a logic '0' or '1' for GND or VCC respectively. My question is why is it doing this? When previously using Foundation v1.4 to implement the same designs on the XC4000 series, I did not come across this problem. As you could guess, I anticipated similar CLB counts for implementing the designs on the Virtex architecture, but was considerably shocked to view the difference in cell counts. Is there any way that I can consolidate the VCC and GND nets to reduce the CLB count? I am aware that if I do this, I may encounter a considerably longer PWR/GND routing delay. But I am willing to make this tradeoff. I've searched through DejaNews and queried Xilinx support (with no response) but have not yet found any answers. Can anyone provide any suggestion here? Thanks in advance. Mathew.Article: 20543
Hi,
We are attempting to implement a CIC Interpolation Filter,
following Hogenauerīs recipe. In a flex10k device.
The parameters are : Bin = 12; Bout = 12; R = 4; M = 1 and N = 4.
So, the minimum register width for each stage is : 13, 14, 15, 15,
15, 16, 16, 18.
We used 2īs complement addition rules, i.e.,all numbers unsigned,
simple binary addition, and carries past the sign are bit ignored.
We did the properly sign extension from one stage to another.
But, the overall frequency response is not the expected, it didnīt
work.
Looking at freq. resp. at each stage, we found the desired shape
till the first ( N+1 )Interpolator stage. From this point, as we add
more stages ( N+2,..., 2N) the things get worst. The outputs saturates,
we think, and we see nothing useful.
Is this problem familiar to someone? Any hint?
Thanks in Advance,
Flávio
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Article: 20544My point is that there seems to be very little money in doing commercial cores for FPGAs. The silicon vendors have set the price point expectations so low (free in many cases) that I suspect you will find little if any return on your investment especially after you factor in the cost of marketing and support. fpgaer@my-deja.com wrote: > Ray, > > Thanks for your comments. > > I know that the FPGA core market is limited and is dominated by big > vendors. But would I be right in saying that this market is growing, > as the gate/price ratio is increasing (slowly) and with their > reconfigurable nature & the time-to-market FPGAs win over ASICs ? > To add to it the 'fabrication-from-foundary' cost factor attached to > ASICs disappears in FPGAs so that individuals can think of designing > complete working systems (an impossible taks when concidering ASICs). > I see scenarios where ONLY FPGA's qualify in terms their reconfigurable > nature - which are increasing by the day ! > > Taking all the pros & cons and reasoning from the above points ( I'm > still not sure if they're right ! ), would it be a wise decision to > concentrate on the business ??? > > In article <38A6E467.E85DCE58@ids.net>, > Ray Andraka <randraka@ids.net> wrote: > > Good luck. From what I've seen, people are not willing to pay much > for > > FPGA based cores. Seems the silicon vendors have set the price > > expectations for cores well below the cost to develop, maintain and > > support such cores. Optimized FPGA cores are more difficult to design > > than comparable cores in ASICs, yet the market price for FPGA cores is > > orders of magnitude less than similar ASIC cores. > > > > fpgaer@my-deja.com wrote: > > > > > Hi, > > > > > > wld. appreciate if anyone cld. share their views on launching a co. > > > which delivers custom-made FPGA cores ? Wld. the effort be worth in > > > terms of time ( & money ) ...... specifically, is there a demanding > > > market for FPGA cores ??? > > > > > > Any comments wld. be highly appreciated !!! > > > > > > Thanks in advance........ > > > > > > Sent via Deja.com http://www.deja.com/ > > > Before you buy. > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20545
normally, you would instantiate the LUTs from the vendor's library. I think you might be able to do it by addressing small roms. ie: constant lut_table:bit_array:=( <lut contents> ); ... begin lut_output<=lut_table(to_integer(lut_address)); I believe synplicity will infer this as a LUT ROM, which is what you would be looking for. Jamil Khatib wrote: > Hi, > > Is there any way to use the LUT by VHDL code, that is to write a VHDL > code "without using the FPGA vendor specific library" that I can know in > advance that it will be > synthesized to LUT or is it just the synthesizer problem? I need this > feature because I want to test some techniques I learned about LUT usage > > Thanks > Jamil Khatib > OpenIP Organization http://www.openip.org > OpenIPCore Project http://www.openip. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20546
You need to use signed arithmetic. The input and all subsequent stages should be sign extended to the width of the adders. Also, keep in mind there is a gain through the filter, so you need to either limit the input bits or extend the output width to accommodate the gain. You might try not truncating first to get it working then prune the adders. At least then you'll be able to determine if the pruning is causing the problem. flavioas@my-deja.com wrote: > Hi, > > We are attempting to implement a CIC Interpolation Filter, > following Hogenauerīs recipe. In a flex10k device. > The parameters are : Bin = 12; Bout = 12; R = 4; M = 1 and N = 4. > So, the minimum register width for each stage is : 13, 14, 15, 15, > 15, 16, 16, 18. > We used 2īs complement addition rules, i.e.,all numbers unsigned, > simple binary addition, and carries past the sign are bit ignored. > We did the properly sign extension from one stage to another. > But, the overall frequency response is not the expected, it didnīt > work. > Looking at freq. resp. at each stage, we found the desired shape > till the first ( N+1 )Interpolator stage. From this point, as we add > more stages ( N+2,..., 2N) the things get worst. The outputs saturates, > we think, and we see nothing useful. > Is this problem familiar to someone? Any hint? > > Thanks in Advance, > > Flávio > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20547
Mathew Wojko wrote: > Is there any way that I can consolidate the VCC and GND nets to reduce > the CLB count? I am aware that if I do this, I may encounter a considerably > longer PWR/GND routing delay. But I am willing to make this tradeoff. > I've searched through DejaNews and queried Xilinx support (with no response) > but have not yet found any answers. > > Can anyone provide any suggestion here? > > Thanks in advance. > > Mathew. I ran across this recently and found that I could make the VCC and GND nets global. Then if you only use a single VCC source instance, you will only get a single driver for a single net. I am using Viewlogic. If you are using the Foundation tools with the Aldec tools, I am not sure how you would do this. Do they support global nets? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 20548
Hi all, VIRTEX-E target. My design produces 12 parrallel outputs at once 4 are in the left edge, 4 are in the middle and 4 are in the right at decreasing rate. I have to use only one off-chip bank ram, hoping to succeed to design the required address generator.... i am just wondering what's the appropriate way to route the different outputs, i mean more precisely how many delays i have to apply to the left, middle , and the right outputs which will feed my address- generator i am applying timing constraint only, (no placement constraint) do you think that i have to use the floorplanner, for example, and so orient by my-self the placement any help will be much appreciated regards Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20549
Does anybody know of a shareware/freeware/fairly cheap DRC package for structural Verilog? Pt
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