Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
The info in www.edif.org is not free. -- Jose (a_k_y@hotmail.com) Sébastien Buschini <sbusch@club-internet.fr> escribió en el mensaje de noticias 38A1F09C.E3BCF54A@club-internet.fr... > > > Jose a écrit: > > > Hi, I would like to obtain more info about EDIF especification. > > Thanks. > > > > -- > > Jose (a_k_y@hotmail.com) > > Did you try http://www.edif.org ? >Article: 20426
David, many thanks for sharing your views on this - I had read the EET article earlier & your comments do add on to it. > Making money in the IP business is difficult and not for the > faint of heart. There is an article in the latest EETIMES > that says it better than I could. My experience with IP > backs up what this article says. The link to it is: > > http://www.eetimes.com/story/design/OEG20000203S0051 > > Hope that helps! > > David Kessner > davidk@free-ip.com http://www.free-ip.com/ > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20427
On Wed, 9 Feb 2000 15:33:05 -0700, "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> wrote: >I've got a fairly simple all-VHDL Spartan design (easily fits into an >XCS20XL-4 using 119 of the 400 CLBs) with an annoying "problem." Tools are >FPGA Express v3.3 and F2.1i SP4. It takes in an 80 MHz clock and uses that >clock for some of the logic, and also divides it by two to generate a 40 MHz >clock which drives the rest of the logic. > >The tools are smart: FPGA Express inferred a BUFGLS for the 80 MHz clock and >another one for the 40 MHz clock. I confirmed this by looking at the design >in the FPGA Editor. I set up period constraints for the 80 MHz and the 40 >MHz logic. P+R was fine and the timing analyzer tells me that I meet all of >my constraints with margin to spare. > >But there's a warning: "Timing:33:Clock nets using non-dedicated resources >were found in this design. Clock skew on these resources will not be >automatically adress during path analysis. To create a timing report that >analyzes clock skew for these paths, run trce with the '-skew' option." > >OK, I did and I still meet timing. My question: > >How do I (easily) find what/where these alleged non-dedicated resources are? I did this exact same thing just a few hours ago. I scanned the edif file for all clocks, and sure enough, they were all appropriately connected to signals driven by bufg. It turned out to be that the input of one particular bufg was connected to the output of an ibuf, rather than directly to the pad. (We explicitly define things like bufgs in our code here, and sometimes mistakes like this happen.) Regards, Allan.Article: 20428
Hi all
I want to use latches on an address bus (the data book says it can be
done).
I keep getting this warning (one per latch):
Dpm : Warning: FlipFlop/Latch "(name of the latch)" is not set/reset by
"/rst"
I have two processes in the same architecture, one for the latch and
another one for the FFs. Both are reset by the same signal (as are all
the others FFs in my design)
I can't see what's wrong in my VHDL
Code sample:
PROCESS (rst, isa_a, ale_i) -- address latch
BEGIN
IF rst = '1' THEN
addr <= (OTHERS => '0');
ELSIF ale_i = '0' THEN
addr <= isa_a;
END IF;
END PROCESS;
PROCESS (sys_clk, rst) -- i/o sync
BEGIN
IF rst = '1' THEN
d_in <= (OTHERS => '0');
isa_irq <= '0';
m16_i <= '0';
ELSIF (sys_clk='1' AND sys_clk'EVENT) THEN
d_in <= isa_d;
isa_irq <= irq;
IF rd = '0' THEN
m16_i <= m16;
END IF;
END IF;
END PROCESS;
Nicolas MATRINGE DotCom S.A.
Conception electronique 16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11 92400 COURBEVOIE
Fax 00 33 1 46 67 51 01 FRANCE
Article: 20429
Hi folks,
I'd appreciate some more information about the following part:
GM76C8128CLLFW55 (maybe 128k8 low power, async. SRAM, 525-mil SOP32
package, 5V supply, 55ns access time).
Our problem is, that we simply can't buy 1 Mbit (128kx8), 55 ns SRAM
parts. The logistic department mentioned that they could maybe get these
Goldstar SRAMs for the tripple of the usual price in about 3 weeks.
Since LG (Goldstar) was overtaken by Hyundai last year, I can't find any
data sheet of this RAM.
So could someone, please post me a data sheet or a description of this
part?
Or could someone tell me, whether this Goldstar SRAM is more or less
compatible with the following parts?
Toshiba:
TC551001CF-55, TC551001CF-55L
Samsung:
KM681000CLG-5L, K6T1008C2C-GL55
KM681000CLG-5LL, K6T1008C2C-GB55
KM681000ELG-5, K6T1008C2E-GL55
KM681000ELG-5L, K6T1008C2E-GB55
Hyundai:
HY628100AG-55, HY628100ALG-55
HY628100ALLG-55
Hitachi:
HM628128DLP-5. HM628128DLP-5SL. HM628128DLP-5UL
Thanks for any help in advance,
Botond
--
Botond Kardos - at Innomed Medical Inc. in Hungary
eMail: Kardos.Botond@hu.innomed.NOSPAM
phone/fax: (0036 1) 351-2934
fax: (0036 1) 321-1075
To get my real address just put the domain
name in reverse order and remove 'nospam'.
x@1.2.3 -> x@2.1
Article: 20430We are using VHDL Primer by J. Bhasker in my class. I recomend taking a college class to get started in using VHDL. There is just too much to VHDL to successfully learn it by just reading a book. Don GoldingArticle: 20431
Hi, Does anyone know of any tools that can convert "raw-data" files to .hex or .mif files for memory initialization in Altera's tools? -NikolayArticle: 20432
Hi,
Marc Reinert wrote:
> Has anybody experience with (or information about) implementing a
> Viterbi Decoder into a Xilinx FPGA?
>
> I'm going to develop a decoder to decode a variable convolutional code
> (rate 1/2 or 1/3, Number of states min. 128 / better 256 or 512). I will
> use a soft decision input (4 Bit quantisation). Optionally the decoder
> shall compute a Soft Decision Output (SOVA). Very important is the
> possibility of a high thourghput (>20 MBit/s).
>
> I'm going to use Xilinx tools (VHDL in Foundation Express 2.1) and
> Xilinx FPGA('s) (for example XC4062 XLA).
>
> I'm thankful for any information about Viterbi Decoding on programable
> logic or for elements of VDHL-Code that implement parts of the decoder
> like Add-Compare-Select-Unit, fast memory-management etc. .
>
> Maybe anybody can help me! Thank U!
>
You may take a look at the following link:
Viterbi encoder/decoder for the (22,8,6) block code:
http://www-ee.eng.hawaii.edu/~pramod/ee628/viterbi.html
--
Edwin
Article: 20433John Janusson <jjanusson@nospami-o.com> wrote in message news:sYCn4.6641$wR.645558@news.flash.net... > I would recommend Xilinx Foundation because it includes Synopsys FPGA > Express, which I think most would agree is a better HDL synthesizer than > Altera's... You also get a state machine entry program, which might make it > easier for beginners... Alas, neither come with a good VHDL simulator> Xilinx should be shipping a free version of ModelSim with the Foundation package - it's restricted to 500 lines of code but that might be ok for students - I assume the 500 line limit refers to the testbench file, not the source + libraries + testbench. Anyone know any different? Mark Harvey.Article: 20434
> But there's a warning: "Timing:33:Clock nets using non-dedicated resources > were found in this design. Clock skew on these resources will not be > automatically adress during path analysis. To create a timing report that > analyzes clock skew for these paths, run trce with the '-skew' option." > > OK, I did and I still meet timing. My question: > > How do I (easily) find what/where these alleged non-dedicated resources are? I assume that this means you have some DFFs being clocked by signals which don't come from the output of global buffers. You could try checking the sensitivity lists of your VHDL processes to see which signals are being used as clocks, or check the XNF/EDIF netlist. Mark Harvey.Article: 20435
Hi Phil,
What fpga's did you use with this program ?
roman
Phil Endecott wrote:
> Hi All,
>
> A while ago I asked about downloading Xilinx bitfiles from Linux and got
> some useful pointers from this group. I took Larry Doolittle's port of
> the XESS download program as a starting point, but found various
> problems. First, XESS and Xilinx have chosen different pin allocations
> for their download cables (I am using the Xilinx Parallel Cable III to
> download to a VCC prototyping board). Second, the XESS code contains
> lots of stuff specific to their board for initialising memory and so
> on. So I've reimplemented it, an in the process have achieved a
> substantial speedup. The code is included below in case it is useful to
> anyone else.
>
> Regards,
>
> --Phil Endecott.
>
> // Program to download a Xilinx bitfile over a "Parallel cable III"
> // from Linux.
> // Author: Phil Endecott phil_endecott@spamcop.net
> // This code is in the public domain.
> // You use this code at your own risk. No warranty.
> // Algorithm based in part on Larry Doolittle's port of the XESS
> // software.
>
> #include <stdio.h>
> #include <assert.h>
> #include <asm/io.h>
> #include <sys/types.h>
> #include <unistd.h>
> #include <sys/perm.h>
> #include <stdlib.h>
>
> const unsigned short base_address=0x378;
> //const unsigned short data_reg_address=base_address;
> #define data_reg_address base_address
>
> const unsigned char data_reg_default=0x14; // 00011000
> const unsigned char din_value=0x01;
> const unsigned char cclk_value=0x02;
> const unsigned char nprog_value=0x04;
>
> const unsigned char bitstream_field_type=0x65;
>
> static inline void set_pport_data_reg(unsigned char d)
> {
> outb(d,data_reg_address);
> }
>
> static inline void send_bit(unsigned int d)
> {
> set_pport_data_reg(data_reg_default|(d?din_value:0));
> set_pport_data_reg(data_reg_default|(d?din_value:0)|cclk_value);
> }
>
> static inline void send_byte(unsigned char d)
> {
> send_bit(d&0x80);
> send_bit(d&0x40);
> send_bit(d&0x20);
> send_bit(d&0x10);
> send_bit(d&0x08);
> send_bit(d&0x04);
> send_bit(d&0x02);
> send_bit(d&0x01);
> }
>
> static FILE* bitfile;
>
> static void check_eof(void)
> {
> assert(!feof(bitfile));
> }
>
> static unsigned short get_short(void)
> {
> unsigned char byte0, byte1;
> fread(&byte0,1,1,bitfile);
> check_eof();
> fread(&byte1,1,1,bitfile);
> return (byte0<<8)|byte1;
> }
>
> static unsigned long get_long(void)
> {
> unsigned char byte0, byte1, byte2, byte3;
> fread(&byte0,1,1,bitfile);
> fread(&byte1,1,1,bitfile);
> fread(&byte2,1,1,bitfile);
> check_eof();
> fread(&byte3,1,1,bitfile);
> return (byte0<<24)|(byte1<<16)|(byte2<<8)|byte3;
> }
>
> static void skip(int howmuch)
> {
> assert(fseek(bitfile,howmuch,SEEK_CUR)==0);
> }
>
> static void scan_for_field(unsigned char scan_field_type)
> {
> unsigned char field_type;
> int fieldlength;
>
> while(1){
> check_eof();
> fread(&field_type,1,1,bitfile);
> if(field_type==scan_field_type){
> return;
> }
> fieldlength=get_short();
> skip(fieldlength);
> }
> }
>
> static void configure_from_bitfile(void)
> {
> int fieldlength;
> int i;
> char* data;
>
> fieldlength=get_short();
> skip(fieldlength);
>
> fieldlength=get_short();
> assert(fieldlength==1);
>
> scan_for_field(bitstream_field_type);
> fieldlength=get_long();
>
> data=malloc(fieldlength);
> assert(data);
> assert(fread(data,1,fieldlength,bitfile)==fieldlength);
> for(i=0;i<fieldlength;i++){
> send_byte(data[i]);
> if((i%1000)==0){
> fprintf(stderr,"*");
> }
> }
>
> for(i=0;i<4;i++){
> send_bit(0);
> }
> fprintf(stderr,"\n");
> }
>
> static void prog_pulse(void)
> {
> set_pport_data_reg(data_reg_default&~nprog_value);
> set_pport_data_reg(data_reg_default);
> }
>
> int main(int argc,char** argv)
> {
> char* bitfile_name;
>
> // This program needs root priveledges in order to call ioperm, so
> // install it setuid root. It gives up rootness after calling
> // ioperm.
>
> assert(geteuid()==0);
> assert(ioperm(base_address,8,1)==0);
> assert(seteuid(getuid())==0);
> assert(geteuid()!=0);
>
> assert(argc==2);
> bitfile_name=argv[1];
> bitfile=fopen(bitfile_name,"r");
> assert(bitfile);
>
> prog_pulse();
> configure_from_bitfile();
>
> fclose(bitfile);
> exit(0);
> }
Article: 20436Hi friends, I 'am looking for the links about partitioning. I mean under this word, which part of FPGA (ASIC) must be done as hardware (CORE) and which as software, the different optimization criteria and other aspects of this. May be I will make my Ph.D. with this theme. That why I want to show, what is made to this moment in this topic. Links and ideas would be greatly appreciated. (If you want mail me use: bonio.lopezXY@gmx.ch_remove_XY) with best regards, bonio Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20437
Hi, There's a lot of talk on IP for FPGAs - ( tons of articles can be found on this at EET, EDTN, Optimagic....etc. sites). The reconfigurable-silicon concept does look very powerful & attractive ! The question is " What level of functional complexity can exactly be achieved on the currently available FPGAs ? " The designs that I've come across so far are ,at best, complex independent functional blocks ie; FIR/IIR filters, Veterbi codecs....etc. I've yet to come across a full fledged system level design on an FPGA - something like (say) a design where a FPGA can be instantly reconfigured to be a MP3 codec in one mode and a soft modem in another. Another ex. I cld. quote is a FPGA behaving as one of the wireless air interface standards ie; GSM/TDMA/CDMA ( in other words - a S/W radio ) depending on the core downloaded on it (an ASIC from Motorola exactly does this ! ) What I'm trying to get at is that all this seems to be theoritically possible but I haven't seen any working design yet ! Even the ref. examples at the Xilinx site are mostly glue-logic designs. SO, can the examples quoted above be realised on a FPGA ( assuming that the required no. of gates are available ) ? If not (since it's possible theoritically) what cld. be the primary reason for this ? Any comments wld. be appreciated ! Thanks........Anurag Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20438
Whilst browsing the Altera mega_lpm library I noticed a symbol called "pcpu". It appears to be a CPU of some sort, but there is no documentation for it. Has anyone got any more info? Leon -- Leon Heller, G1HSM Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20439
Hi,
I am using the following code to XOR two bytes. I am able to simulate it
using Active HDL(3.1) and seems to work, but when I use Warp I get the
following error while compiling :
C:\warp\bin\WARP.EXE -q -e10 -w100 -o2 -yga -fO -fP -v10 -dC371 -pCY7C371-14
3JC -b byte_xor.vhd
VHDL parser (C:\warp\bin\vhdlfe.exe V4 IR x95)
Setting library 'work' to directory 'lc371'
----------------------------------------
Compiling 'byte_xor.vhd' in 'C:\WARP\EXAMPLES\Pradeep'.
VHDL parser (C:\warp\bin\vhdlfe.exe V4 IR x95)
Library 'work' => directory 'lc371'
Linking 'C:\warp\lib\common\work\cypress.vif'.
byte_xor.vhd (line 8, col 30): (E56) Expected FUNCTION, but got IS
Error occurred within 'PROCESS' at line 8, column 16 in byte_xor.vhd.
byte_xor.vhd (line 8, col 30): (E10) Syntax error at/before reserved symbol
'is'.
----------------------------------------
WARP done.
Here's my code :
-----------------------
entity bytexor is
port (xin1,xin2 : in bit_vector(0 to 7);
xout : out bit_vector(0 to 7));
end entity bytexor;
architecture behave of bytexor is
begin
compute:process(xin1,xin2) is
begin
for index in 0 to 7 loop
xout(index)<= xin1(index) xor xin2(index);
end loop;
end process compute;
end architecture behave;
------------------------------------------------
I'd be glad if someone could help me out.
Thanks,
Pradeep Rao
Article: 20440We have been using Lattice CPLD's (ispLSI1024, ispLSI2064, etc.) in the past with Synopsis software and are dissatisfied with the performance of both. Our designs are generally quite simple (glue logic and registers). Does anyone have a recommendation either for or against Altera (MAX7000 family) using MAXBaseline or MAXPlus, and Cypress (Ultra 37000 family) using Warp 5.2? Any known hardware or software prolems? Thanks in advance. Mary FrantzArticle: 20441
Hi using Xilinx foundation2.1i. (xc9536 vq44-15)
Writing a VHDL program and recive an error
message:
The net'/ver1/klar' has more than one driver.
All of our variables are STD_LOGIC.
Thankful for help.
Björn Lindegren, Christian Jerkeborg
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
entity fyren1 is
port (CLK: in STD_LOGIC;
OSC: in STD_LOGIC;
RESET: in STD_LOGIC;
KLAR: inout STD_LOGIC;
START: inout STD_LOGIC);
end;
architecture fyren1_arch of fyren1 is
-- SYMBOLIC ENCODED state machine: COUNT
type COUNT_type is (KLART, OSC0, OSC1, OSCSTART);
signal COUNT: COUNT_type;
-- SYMBOLIC ENCODED state machine: FEMTON
type FEMTON_type is (S1, S2);
signal FEMTON: FEMTON_type;
begin
--concurrent signal assignments
COUNT_machine: process (CLK)
--machine variables declarations
variable COUNTER: INTEGER range 0 to 100;
begin
if CLK'event and CLK = '1' then
if START='1' then
COUNT <= OSCSTART;
COUNTER:=0;
KLAR<='0';
else
case COUNT is
when KLART =>
KLAR<='1';
if COUNTER<=3 then
COUNT <= OSC0;
KLAR<='0';
end if;
when OSC0 =>
COUNTER:=COUNTER+1;
if OSC='1' then
COUNT <= OSC1;
KLAR<='0';
elsif COUNTER=3 then
COUNT <= KLART;
end if;
when OSC1 =>
if OSC='0' then
COUNT <= OSC0;
KLAR<='0';
end if;
when OSCSTART =>
KLAR<='0';
if OSC='1' then
COUNT <= OSC1;
KLAR<='0';
end if;
when others =>
null;
end case;
end if;
end if;
end process;
FEMTON_machine: process (CLK)
begin
if CLK'event and CLK = '1' then
if RESET='1' then
FEMTON <= S1;
KLAR<='0';
START<='1';
START<='0';
else
case FEMTON is
when S1 =>
START<='0';
if KLAR<='1' then
FEMTON <= S2;
KLAR<='0';
START<='1';
end if;
when S2 =>
START<='0';
if KLAR<='1' then
FEMTON <= S1;
KLAR<='0';
START<='1';
end if;
when others =>
null;
end case;
end if;
end if;
end process;
end fyren1_arch;
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20442
Hi using Xilinx foundation2.1i. (xc9536 vq44-15)
Writing a VHDL program and recive an error
message:
The net'/ver1/klar' has more than one driver.
All of our variables are STD_LOGIC.
Thankful for help.
Björn Lindegren, Christian Jerkeborg
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
entity fyren1 is
port (CLK: in STD_LOGIC;
OSC: in STD_LOGIC;
RESET: in STD_LOGIC;
KLAR: inout STD_LOGIC;
START: inout STD_LOGIC);
end;
architecture fyren1_arch of fyren1 is
-- SYMBOLIC ENCODED state machine: COUNT
type COUNT_type is (KLART, OSC0, OSC1, OSCSTART);
signal COUNT: COUNT_type;
-- SYMBOLIC ENCODED state machine: FEMTON
type FEMTON_type is (S1, S2);
signal FEMTON: FEMTON_type;
begin
--concurrent signal assignments
COUNT_machine: process (CLK)
--machine variables declarations
variable COUNTER: INTEGER range 0 to 100;
begin
if CLK'event and CLK = '1' then
if START='1' then
COUNT <= OSCSTART;
COUNTER:=0;
KLAR<='0';
else
case COUNT is
when KLART =>
KLAR<='1';
if COUNTER<=3 then
COUNT <= OSC0;
KLAR<='0';
end if;
when OSC0 =>
COUNTER:=COUNTER+1;
if OSC='1' then
COUNT <= OSC1;
KLAR<='0';
elsif COUNTER=3 then
COUNT <= KLART;
end if;
when OSC1 =>
if OSC='0' then
COUNT <= OSC0;
KLAR<='0';
end if;
when OSCSTART =>
KLAR<='0';
if OSC='1' then
COUNT <= OSC1;
KLAR<='0';
end if;
when others =>
null;
end case;
end if;
end if;
end process;
FEMTON_machine: process (CLK)
begin
if CLK'event and CLK = '1' then
if RESET='1' then
FEMTON <= S1;
KLAR<='0';
START<='1';
START<='0';
else
case FEMTON is
when S1 =>
START<='0';
if KLAR<='1' then
FEMTON <= S2;
KLAR<='0';
START<='1';
end if;
when S2 =>
START<='0';
if KLAR<='1' then
FEMTON <= S1;
KLAR<='0';
START<='1';
end if;
when others =>
null;
end case;
end if;
end if;
end process;
end fyren1_arch;
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20443I think ( am not quite sure ) that the software tries to tell you that you have two clock domains that are not perfectly aligned. The 40 MHz clock edges are inevitably delayed from the 80 MHz clock edges. This can cause all sorts of ugly hold-time problems and race conditions, if data communicates from the 80 MHz to the 40 MHz clock domain. (No problem in the other direction). If you really know what you are doing, this is no problem. If (heaven forbid) you were ( subjunctive case! ) naive, this might not work e.g. at low temperature. Safe solution: run everything at 80 MHz and distribute a 40 MHz clock enable to the appropriate flip-flops. Then your whole design is totally synchronous. Peter Alfke, Xilinx Applications ====================================== Andy Peters wrote: > I've got a fairly simple all-VHDL Spartan design (easily fits into an > XCS20XL-4 using 119 of the 400 CLBs) with an annoying "problem." Tools are > FPGA Express v3.3 and F2.1i SP4. It takes in an 80 MHz clock and uses that > clock for some of the logic, and also divides it by two to generate a 40 MHz > clock which drives the rest of the logic. > > The tools are smart: FPGA Express inferred a BUFGLS for the 80 MHz clock and > another one for the 40 MHz clock. I confirmed this by looking at the design > in the FPGA Editor. I set up period constraints for the 80 MHz and the 40 > MHz logic. P+R was fine and the timing analyzer tells me that I meet all of > my constraints with margin to spare. > > But there's a warning: "Timing:33:Clock nets using non-dedicated resources > were found in this design. Clock skew on these resources will not be > automatically adress during path analysis. To create a timing report that > analyzes clock skew for these paths, run trce with the '-skew' option." > > OK, I did and I still meet timing. My question: > > How do I (easily) find what/where these alleged non-dedicated resources are? > > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "Money is property; it is not speech." > -- Justice John Paul StevensArticle: 20444
You could try the sci.electronics.components newsgroup - they have lots of traffic on this sort of topic. -- Tom Burgess -- Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.ca Office: (250) 490-4360 Switch Board: (250) 493-2277 Fax: (250) 493-7767Article: 20445
Don Golding wrote in message ...
>We are using VHDL Primer by J. Bhasker in my class. I recomend taking a
>college class to get started in using VHDL. There is just too much to VHDL
>to successfully learn it by just reading a book.
I recommend doing a chip-design project in VHDL. There is just too much to
VHDL to successfully learn it by taking a college course.
note: your first design will be embarrassing. your third might be pretty
good, tho'.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20446
Peter Alfke wrote in message <38A2FA54.F8AF795D@xilinx.com>...
>I think ( am not quite sure ) that the software tries to tell you that you
have
>
>two clock domains that are not perfectly aligned. The 40 MHz clock edges
are
>inevitably delayed from the 80 MHz clock edges. This can cause all sorts of
>ugly hold-time problems and race conditions, if data communicates from
>the 80 MHz to the 40 MHz clock domain. (No problem in the other direction).
Oh! I see - that's an interesting point. Clearly, there's skew between the
80 and 40 MHz domains - there's the clock-to-out delay of the flop that's
doing the dividing, the routing from that flop to the BUFGLS, plus the delay
through the BUFGLS. Makes sense. And I should have thought of it.
The signals that go between the 80 and 40 MHz domains are simply flags that
get set or reset. These flags are used as clock enables (like, "turn
counter 3 on or off").
>If you really know what you are doing, this is no problem. If (heaven
forbid)
>you were ( subjunctive case! ) naive, this might not work e.g. at low
>temperature.
I *think* I know what I'm doing! :)
>Safe solution: run everything at 80 MHz and distribute a 40 MHz clock
enable to
>the appropriate flip-flops.
>Then your whole design is totally synchronous.
I've already done that - I just wanted to understand the warning.
thanks much--
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20447
bjorn_lindegren@my-deja.com wrote in message
<87utdp$k24$1@nnrp1.deja.com>...
>Hi using Xilinx foundation2.1i. (xc9536 vq44-15)
>
>Writing a VHDL program and recive an error
>message:
>The net'/ver1/klar' has more than one driver.
>
>All of our variables are STD_LOGIC.
>
[snip code]
You drive the signal klar from more than one process.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 20448Check out the following solution record: http://support.xilinx.com/support/techsup/journals/timing/solution2586/virtex_clkdll_timing.html If you put a period statement on the input clock to the DLL, the tools will create new period constraints for all the output clocks. It does not constraint between clock boundaries. This must be done by creating groups for each clock then doing a from to statement between clock domains. There are skew problems between clk0 and the 2x clock. KateArticle: 20449
If you want to minimize skew uncertainty due to non-dedicated routing, you might want to look into constraining the divide flip-flop and BUFGLS to be close together in the same corner of the die. I don't know if the tools are smart enough to do this for you (yet). You could take a look with EditLCA and see. It would be preferable to find a timing constraint which achieves the same result (there probably is one - if you can find and decipher the documentation). This also applies to Peter's suggestion of distributing a 40 MHz CE, in which case you have to worry about meeting CE setup times back in the 80 MHz domain. It looks like derived clocks will be much easier to deal with in the Virtex/Spartan 2 family. Andy Peters wrote: > <snipped> > Oh! I see - that's an interesting point. Clearly, there's skew between the > 80 and 40 MHz domains - there's the clock-to-out delay of the flop that's > doing the dividing, the routing from that flop to the BUFGLS, plus the delay > through the BUFGLS. Makes sense. And I should have thought of it. > regards, Tom Burgess -- Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.ca Office: (250) 490-4360 Switch Board: (250) 493-2277 Fax: (250) 493-7767
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z