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Does anyone know of an available piece of code which will handle simple bitmap manipulation and memory management. Basically it has to receive bit maps and place them into a memory store shared with raster address logic for video display--no fancy processing. Read write modify basically. Could anyone point me in the right direction. thanks in advance.Article: 6126
I already posted the following announcement, but it didn't seem to appear, so here goes again... (Sorry if this is repetitive, but something seems to be wrong with the news server lately.) I would like to announce a new algorithm for division that retires 2-3 bits per iteration,yet is much simpler than Radix-4 SRT because it uses no lookup table. It only needs 2-bit comparisons plus a little simple logic. The article is in the proceedings of ICCD '96. The fastest implementation would be self-timed dynamic, but our algorithm is also suitable for FPGA implementation. Don Husby of the Fermi National Accelerator Lab has implemented a 16/8 bit version of it in ORCA, which can be found in pdf format at the following Web site: http://www-ese.fnal.gov/eseproj/trigger/div16p.pdf You are quite welcome to contact me if you are interested or have any questions. There are also some new developments and minor corrections. My email address is vkantabu@howland.isu.edu Vitit KantabutraArticle: 6127
I guess that I should have been more clear in my previous posting. The answer depends a lot on the FPGA family and the device. I've been most familiar with XC4013Es which is the device specified in the Xilinx LogiCORE PCI interface (see 'http://www.xilinx.com/products/logicore/pci_sol.htm'). From a quick calculation, you can easily meet the 200 ms spec. using an XC4013E in fast serial configuration mode. Here are the details based on worst-case values derived from the 1996 Xilinx Data Book (dated 7/96) starting on page 4-59. 1. The FPGA becomes active internally at about 3.5 volts. There is a built-in power-on delay that waits an additional 64 ms for power to all the devices on the board to become stable (it's only 16 ms if the FPGA is configuring in peripheral or slave mode). 2. After the power-on delay expires, the internal configuration memory is cleared. This requires ~1.3 us per data frame. The XC4013E has 932 data frames (Table 22, page 4-57). Because the data book says about (~) 1.3 us, I'll double the resulting sum to 2.4 ms. 3. An XC4000E device configured in master mode waits an additional 50 to 250 us before re-sampling the /INIT and configuration mode pins. I'll use the 250 us value or 0.25 ms. 4. The next step is to load the configuration data into the device. I'm going to assume that I am using the fast serial configuration mode (see "Setting CCLK Frequency" on page 4-56). If you use this mode plus a serial PROM that supports it (i.e. XC17128D or XC17256D), then the FPGA configures 8 times faster than if you use the standard serial mode. The first few bits are shifted in at the slow rate until the enable bit is encountered. Once enabled, the FPGA will shift its configuration data in at between 4 MHz to 10 MHz. Again, I'll use the worst-case value of 4 MHz corresponding to 0.25 us per bit. Looking again at Table 22 on page 4-57, I see that the XC4013E requires 247,960 program bits. Multiplying 247,960 time 0.25 us per bit, I get 62 ms. The first few bits are slower so lets round it to 70 ms. So from the time that Vcc > 3.5 volts to a configured XC4013E design should be: Power-On Delay (Step 1): 64 ms Clear Configuration Memory (Step 2): 2.4 ms Master Mode /INIT Delay (Step 3): 0.25 ms Load Configuration Data (Step 4): 70 ms ------------------------------------ --------- TOTAL 137 ms Even adding a 30% guardband above the worst-case values to cover the time your power supply takes to go between 0 and 3.5 volts, the total comes out to be 178 ms. This is below the 200 ms seen on your system. Some other caveats: Unless you are using the fast serial configuration mode, your configuration times could be up to 8 times longer. See page 4-56 on how to reduce your configuration times by setting the CCLK frequency. Larger devices have more data frames and more program bits and will take a correspondingly longer time to configure. For most embedded PCI applications, you have full control or can characterize your system power supply. Some systems may allow much longer than 200 ms. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Wen-King Su <wen-king@myri.com> wrote in article <5ir9su$6aq@neptune.myri.com>... | In a previous article "Steven K. Knapp" <optmagic@ix.netcom.com> writes: | : | ;The power-on and reset are two separate issues. From the limited number of | :systems that I've looked at, the power-on time is more than sufficiently | ;long for an FPGA to boot. The XC4000E family also has a faster boot time | :when you enable the proper option in MakeBits. At power-on, the FPGA is | ;configuring at the same time that the processor and peripheral chips are | :coming awake. | ; | :On a system reset (without power cycling), the FPGA is already configured | ;and can respond immediately. | | We have customers with systems that start to access the PCI bus less than | 200ms from power on. That was too soon for some of the FPGAs. |Article: 6128
In article <5ir9su$6aq@neptune.myri.com>, wen-king@myri.com (Wen-King Su) wrote: > We have customers with systems that start to access the PCI bus less than > 200ms from power on. That was too soon for some of the FPGAs. That should not be a problem if you plan for it. The Xilinx FPGAs that would be used have between 150,000 and 450,000 configuration bits. At an 8-MHz rate ( using the fast configuration mode ) even in master serial mode, the actual downloading takes only 20 to 60 ms, leaving enough time for th preceding power-up and clear. If you are in a real hurry, use slave serial, which reduces the power-up delay and also allows you to increase the clock rate to 10 MHz. And if that still is too slow, send me an e-mail and I can tell you more tricks. I am also a bit suspicious of any activity within 200 ms after power-up. How well-defined is power-up ? Peter Alfke, Xilinx ApplicationsArticle: 6129
Hello: I need some documentation on a Wallace Tree multiplier. If anyone could please email me a source for a reference, it would be great. Thanks, VenkatArticle: 6130
I am with Human Resources for the Small Internetworks Business Unit (formerly Grand Junction) at Cisco Systems. We develop switches, routers, and hubs that focus on small and medium-sized companies. Revenue-wise we are the fastest growing Business Unit at Cisco Systems with 30+% growth over the last five quarters. We are currently looking for senior and intermediate ASIC Engineers (digital) as well as senior and intermediate Systems Engineers (embedded CPU, FPGA) to join our team. We are located in San Jose, California. If you, or anyone you know is interested, please contact me or send me your resume. I will be happy to talk with you further about the positions. To send your resume: fax: 408-527-3831 or email: lshevock@cisco.com No agencies please -- To send your resume: fax: 527-0180 or email: lshevock@cisco.com No agencies pleaseArticle: 6131
(Note: this repost corrects the URL - I forgot the .html on the file) Two survey articles covering hardware, software, and applications of reconfigurable systems are now available. Their titles and abstracts are given below. The first was written by myself, while the second is a joint effort with Anant Agarwal at MIT. Both can be found at http://www.ece.nwu.edu/~hauck/publications.html , at the bottom of the page. These papers will be submitted for publication soon, and all comments are welcome. Scott Hauck hauck@ece.nwu.edu -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- The Roles of FPGAs in Reprogrammable Systems Scott Hauck Department of Electrical and Computer Engineering Northwestern University Evanston, IL 60208-3118 USA hauck@ece.nwu.edu Abstract FPGA-based reprogrammable systems are revolutionizing some forms of computation and digital logic. As a logic emulation system they provide orders of magnitude speedup over software simulation. As a custom-computing machine they achieve the highest performance implementation for many types of applications. As a multi-mode system they yield significant hardware savings and provide truly generic hardware. In this paper we discuss the promise and problems of reprogrammable systems. This includes an overview of the chip and system architectures of reprogrammable systems, as well as the applications of these systems. We also discuss the challenges and opportunities of future reprogrammable systems. -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Software Technologies for Reconfigurable Systems Scott Hauck Anant Agarwal Department of ECE Department of EECS Northwestern University Massachusetts Institute of Technology Evanston, IL 60208 USA Cambridge, MA 02139 USA hauck@ece.nwu.edu agarwal@lcs.mit.edu Abstract FPGA-based systems are a significant area of computing, providing a high-performance implementation substrate for many different applications. However, the key to harnessing their power for most domains is developing mapping tools for automatically transforming a circuit or algorithm into a configuration for the system. In this paper we review the current state-of-the-art in mapping tools for FPGA-based systems, including single-chip and multi-chip mapping algorithms for FPGAs, software support for reconfigurable computing, and tools for run-time reconfigurability. We also discuss the challenges for the future, pointing out where development is still needed to let reconfigurable systems achieve all of their promise. +-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+ | Scott A. Hauck, Assistant Professor | | Dept. of ECE Voice: (847) 467-1849 | | Northwestern University FAX: (847) 467-4144 | | 2145 Sheridan Road Email: hauck@ece.nwu.edu | | Evanston, IL 60208 WWW: http://www.ece.nwu.edu/~hauck | +-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+Article: 6132
In a previous article peter@xilinx.com (Peter Alfke) writes: : ;In article <5ir9su$6aq@neptune.myri.com>, wen-king@myri.com (Wen-King Su) wrote: : ; :> We have customers with systems that start to access the PCI bus less than ;> 200ms from power on. That was too soon for some of the FPGAs. : ;That should not be a problem if you plan for it. :The Xilinx FPGAs that would be used have between 150,000 and 450,000 ;configuration bits. At an 8-MHz rate ( using the fast configuration mode ) :even in master serial mode, the actual downloading takes only 20 to 60 ms, ;leaving enough time for th preceding power-up and clear. :If you are in a real hurry, use slave serial, which reduces the power-up ;delay and also allows you to increase the clock rate to 10 MHz. :And if that still is too slow, send me an e-mail and I can tell you more tricks. ; :I am also a bit suspicious of any activity within 200 ms after power-up. ;How well-defined is power-up ? I am aware of the fast mode, and we are making revised boards using fast mode. I didn't get the real point across, however. We realized there is no way to meet the PCI spec (1 ms), and we made a guess at what the real minimum delay should be and we designed for it. Naturally we choose to use the cheapest ROMs that meets the expected minimum delay. The guess was right except for one specific machine with one specific BIOS version. So now we are a little concerned that with faster CPUs we may find more and more systems with short delays, and eventually even fast mode wouldn't be fast enough for it.Article: 6133
IS EVERY ONE ELSE AS PISSED AS I AM ABOUT THIS continual SPAMMING OF THIS NEWS GROUP BY THE $#@%!%#$ AT CISCO ??? My response: significant email to postmaster , root at cisco. In article <lshevock-1404971525500001@dynaserv-noc1-250.cisco.com> lshevock@diablo.cisco.com (CISCO SYSTEMS) writes: >I am with Human Resources for the Small Internetworks Business Unit >To send your resume: >fax: 408-527-3831 or >email: lshevock@cisco.com >No agencies pleaseArticle: 6134
In article <5imsl2$49t@news.scruz.net>, stevedb <sdb@pctools.com> writes >You should take a look at a program called GDSPLOT from Artwork >Conversion - I think their web site is www.artwork.com. That's odd - I thought the president of Artwork Conversion WAS Steve DiBartolomeo - in which case I would have expected him to know his own web site. But there could be two Steve DiBartolomeo I suppose! Mike WArticle: 6135
There's a 'feature' on the parallel modes which means that you have to swap the bits in each byte to make the MSB bit 0 (presumably someone cocked up the internal shift register!). e.g. serial stream has byte 0x02 - this is fed to the device as 00000010. In parallel mode, the byte has to be 01000000 (0x40). This could be the cause of your problem, at the device would detect an invalid block checksum and flag an error condition. -- Regards AndyG ************************************************** *Any opinions expressed herein are entirely mine,* *unless expressly stated otherwise. * *(as if anybody else would admit to them.....) * **************************************************Article: 6136
In the Rev 2.1 PCI spec, page 134. Table 4-6. Min t-rst = 1ms. This means that the hardware reset is asserted for 1ms. See page 140, which gives the timing diagrams for power good, and reset. It gives a power good to reset de-asserted of 100ms. The FPGA will start configuration when its internal circuits determine power is good to it. The 1ms trst spec doesn't apply to the Xilinx configuration, it doesn't use the PCI reset, or the PCI clock. This is a part of the spec I have been fighting for years because, this is not when the configuration starts….remember, the system BIOS has to run a bunch of code before doing the PCI configuration cycles (ie power on self test, etc.). There should be a minimum time in the spec that the PCI cards have to be 'set them selves up' (say 200ms, or 500ms, or something, anything!). The BIOS doesn't immediately go out and do configuration upon reset being de-asserted! Austin Franklin ..darkroom@ix.netcom.com.Article: 6137
Hello everyone! Does anyone know about any benchmark that I can use for measuring the performance of an FPGA architecture? Maybe some common used circuits for testing the routing resources? Any information is appreciated. Thank you, SilviuArticle: 6138
Silviu wrote: >Does anyone know about any benchmark that I can use for measuring >the performance of an FPGA architecture? Maybe some common used >circuits for testing the routing resources? Any information is >appreciated. Yes, go to <http://www.prep.org> PREP, the programmable electronics performance corporation, is a non-profit benchmarking group for PLDs/FPGAs. There are two working groups, one for device performance & capacity measures, and a newer one for synthesis. You can look up the benchmark performance of many individual devices in representative circuits -- and which circuits were used if you'd like to make your own comparisons. It's quite possible that the devices you're considering have already been evaluated, which may save you some effort. Rhondalee Rohleder Pace Technologies (Scottsdale, AZ) -- R. Rohleder Pace_Research@compuserve.comArticle: 6139
Hi there,
Did anybody had any experience with designing an architecture for
the computation of the exponential function?
I would appreciate any kind of help.
regards,
--
,,,
(o o)
####=====oOO==(_)==OOO===========================================####
## ##
## Mourad ABERBOUR ##
## +---+ ##
## / \ / \ Laboratoire MASI / Equipe CAO-VLSI ##
## / / \ Universite Pierre et Marie Curie (Paris 6) ##
## +---+ \ \ Couloir 55-65 2eme etage ##
## \ \ +---+ 4, place Jussieu, 75252 Paris Cedex 05 ##
## \ / / Tel: (33) 01 44 27 71 24 ##
## \ / \ / ##
## +---+ mailto:mourad.aberbour@cao-vlsi.ibp.fr ##
## http://cao-vlsi.ibp.fR/users/mourad/ ##
## ##
####=============================================================####
Article: 6140This sounds like the classic big endian, little endian problem. Which bit is the MSB and which is the LSB? If you are downloading via a processor, there is a helpful utility on the Xilinx web site that converts your MCS-86 hex file into an easy-to-use data file. This file can then be included with your C or assembler source code. The utility allows you to format the result for your specific environment. You can also control the shift direction (you defind the MSB) and the byte ordering! You can find the utility at: 'http://www.xilinx.com/support/techsup/ftp/htm_index/utils_prom.htm'. The PC version is called 'makesrc.zip' while the SPARC version is called 'makesrc.tar.Z'. The archive file contain the 'makesrc' program, a simple example, and short, but very sufficient, text documentation. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Andy Gulliver <andy.gulliver@crossprod.co.uk> wrote in article <3353739F.5EF4@crossprod.co.uk>... | There's a 'feature' on the parallel modes which means that you have to | swap the bits in each byte to make the MSB bit 0 (presumably someone | cocked up the internal shift register!). | | e.g. serial stream has byte 0x02 - this is fed to the device as | 00000010. In parallel mode, the byte has to be 01000000 (0x40). | | This could be the cause of your problem, at the device would detect an | invalid block checksum and flag an error condition. | | -- | Regards | | AndyG | | ************************************************** | *Any opinions expressed herein are entirely mine,* | *unless expressly stated otherwise. * | *(as if anybody else would admit to them.....) * | ************************************************** |Article: 6141
>>>>> "Mourad" == Mourad Aberbour <aberbour@masi.ibp.fr> writes:
In article <3354BB7D.3C8A943C@masi.ibp.fr> Mourad Aberbour <aberbour@masi.ibp.fr> writes:
Yes, I recently implemented the exp design provided by
@book{koren93,
author = {Israel Koren},
title = {Computer arithmetic algorithms.},
publisher = {Prentice Hall},
year = 1993,
key = {QA76.9.C62K67 1993},
address = {Englewood Cliffs, N.J.},
}
on an Altera Flex 10K chip. It fit on one chip and works well
pipelined. See the above reference for the algorithm. The code was
implemented in AHDL. Has anyone done the Gamma function, or other
complex Math functions yet?
marc
Mourad> Hi there, Did anybody had any experience with designing an
Mourad> architecture for the computation of the exponential
Mourad> function? I would appreciate any kind of help.
--
/++++++++++++++++++++++++++++++++++++++/
Marc Bumble Computer Science and Engineering
University Office Phone: (814) 865-2841
Pond 214 Lab Phone: (814) 863-3627
Pond 111 Lab Phone (814) 863-4422
University Department Fax: (814) 865-3176
University Internet address: http://trantor.cse.psu.edu/~bumble/
University Office Address: 220 Pond Laboratory
Computer Science and Engineering
Pennsylvania State University
University Park, PA 16802
Article: 6142
Does anyone reading this newsgroup have any experience using Xilinx FPGA's
(4KE's) in SBUS applications ? (as used in SUN SPARCstations)
I've used a XC4013E and directly interfaced it to the SBUS, but am running
up against problems - i.e. can't get the workstation to boot. I've
disabled probing of the SBUS slot the board is in, to eliminate OpenBoot
problems.
From the SBUS specification it looks as if the Xilinx part meets the SBUS
specification using TTL I/O on the FPGA. I've checked for the obvious
things such as driving the SBUS when not selected, I can see that other
transers are occuring on the bus (i.e. activity on AS* and ACK[]*)
I'm in the process of obtaining a SBUS extender board so that I can attach
a logic analyzer to the SBUS to see what transactions are occuring. I
thought I'd try the newsgroup to see if anyone has had any experiences
with SBUS/4KE combinations.
Thanks,
Simon.
________________________________________________________________
#include <std/disclaimer.h>
Simon Pawlowski
Texas Instruments Inc.
email: simonp@ti.com
________________________________________________________________
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 6143Hi Simon I have seen Xilinx 4KE FPGAs used in SBUS applications so know this type of interfacing is possible. One design I saw had problems due to an IO pin glitching low as the FPGA became active after configuration. I'm not familiar with SBUS, but apparently this glitch was causing some form of reset on the bus and so causing the workstation all kinds of problems. (Presetting rather than reseting the flipflop driving the IO pin solved the problem) Sorry I can't be more specific, but if this sounds something like what you are seeing please contact me and I'll try to find out more from the designer involved. Regards Paul Hardy Simon Pawlowski wrote: > > Does anyone reading this newsgroup have any experience using Xilinx FPGA's > (4KE's) in SBUS applications ? (as used in SUN SPARCstations) >Article: 6144
> Does anyone reading this newsgroup have any experience using Xilinx FPGA's > (4KE's) in SBUS applications ? (as used in SUN SPARCstations) > > I've used a XC4013E and directly interfaced it to the SBUS, but am running > up against problems - i.e. can't get the workstation to boot. I've > disabled probing of the SBUS slot the board is in, to eliminate OpenBoot > problems. > > From the SBUS specification it looks as if the Xilinx part meets the SBUS > specification using TTL I/O on the FPGA. I've checked for the obvious > things such as driving the SBUS when not selected, I can see that other > transers are occuring on the bus (i.e. activity on AS* and ACK[]*) > > I'm in the process of obtaining a SBUS extender board so that I can attach > a logic analyzer to the SBUS to see what transactions are occuring. I > thought I'd try the newsgroup to see if anyone has had any experiences > with SBUS/4KE combinations. > > Thanks, > > Simon. I did an SBUS in a Xilinx many years ago. Worked fine. Have you used one of the dual purpose pins (eg. HDC, LDC) in an unfortunate manner? David HolmesArticle: 6145
Try Lattice Semiconductor. They have a STARTER CD with free ABEL andSchematic capture that will target all the CAL devices you require. It also targets their two smallest CPLDs. Best of all its free! They are at WWW.LATTICESEMI.COM -EdArticle: 6146
Hi, Has anyone used Lucent Technologies (or LII - Logic Innovations Inc) VHDL source code kit to implement a Target PCI solution in an FPGA? If so, do you have any comments, good or bad, about the solution. I would like some more independant information about the product before we commit to spending any money. Many Thanks, Dan -- ----------------------------------------------------------------------- Dan L. Symes, R&D Design Engineer Email: dan_symes@aus.hp.com Hewlett-Packard Australia Communications Measurement Division Australia (CMDA) 347 Burwood Hwy, Burwood East, Victoria 3151 Ph: +61 3 9210 5522 P.O. Box 211, Blackburn, Victoria 3130 Fax: +61 3 9210 5550 AustraliaArticle: 6147
david holmes wrote: > > I did an SBUS in a Xilinx many years ago. Worked fine. > Have you used one of the dual purpose pins (eg. HDC, LDC) in an unfortunate manner? > > David Holmes No, luckily that's not the problem. I had I/O pins to spare so could avoid using any configuration pins for user I/O. Once I got the SBUS extender and got a logic analyzer hooked up it became fairly obvious I had a couple of address lines shorting - turns out to be a board layout problem. (Why is it that the problems are never on the top or bottom layers, it's always one of the inner layers ?) Simon.Article: 6148
Keith Blei wrote: > > I'm wondering what will reduce compilation time more. Available > memory or Processor. Currently have 48 MB, NT 4, 100 Mhz Pentium. > Altera 10K50 and 10K70 design ( soon ). Both about 75% utilized. > Compilation currently takes around an hour. > > Considering, Pentium Pro 200 and 64 MB. > Anybody have any practical experience in this area? > TIA, > Keith Both available memory and processor speed will enhance your performance, however, from data I have seen, increasing the available memory has the most dramatic effect on Mr. Gate's operating system. I would suggest you first upgrade to 128MB of RAM. You should see a significant improvement. I forget the exact numbers so I can't quote them here, but a benchmark I saw was something like a P5-133 with 2X memory is equivalent to a P5-200 with 1X memory. I believe this was for a WinNT platform. Maybe someone else has seen data which is similar. Bottom line, memory has the most immediate effect. Regards...GrasonArticle: 6149
keithb@netventure.com (Keith Blei) wrote: >I'm wondering what will reduce compilation time more. Available >memory or Processor. Currently have 48 MB, NT 4, 100 Mhz Pentium. >Altera 10K50 and 10K70 design ( soon ). Both about 75% utilized. >Compilation currently takes around an hour. > >Considering, Pentium Pro 200 and 64 MB. >Anybody have any practical experience in this area? >TIA, >Keith Well the upgrade was worth it although configuring interrupts on Wintel machines is still a HUGE waste of time. Plug and Pray not withstanding. With 200 MHz, PPro and 96 MB of ram, Maxplus 7.2 takes 15 minutes to compile a design that used to take 40. 10K50GC403, 65 % utilized. The report file says 50 MB were used, though NT performance monitor claims 90 MB used of which maybe 19 MB is disk cache plus Kernel. Little if any swapping occurs during compilation. Thanks for the help. Keith
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