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On Apr 3, 4:21=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > Pipeline it, one stage per quotient bit. =A0In software terms, unroll > the divide loop with a register between each cycle. > > Not having actually tried to implement one recently, my thought > is for separate comparator and subtractor, possibly with a > separate pipeline stage for each. =A0 It will still take a lot > of cycles, but once the pipeline is full you get one result > per cycle. > > -- glen Great advice. You can also perform several stages of the division per clock cycle reducing a 16-bit division to 4 clock cycles, for instance. There are better ways to perform pipelined division but you'll need to consider this approach regardless. Another possibility is to multiply rather than add. If your variable isn't available until the clock cycle (right before) you need it, you'll have to decide how many significant bits are needed for a lookup or two to determine a close approximation of the reciprocal. If your variable is available a few clock cycles ahead of time, you can provide the reciprocal to high precision when it's needed. If your "variable" is provided by software, have software provide the reciprocal directly. Dedicated multipliers make reciprocal multiplication much simpler than division though, perhaps, a tiny bit less "precise" depending on your needs. To understand a faster way to divide compared to "determining whether you can subtract the divisor for each stage of the pipeline then subtracting from or passing the previous value" you can instead *always* subtract from a positive value and *always* add from a negative value, simply appending a little arithmetic to the signs from the intermediate stages to get the final result. Try doing some binary long division by hand with the two approaches and you may see how you can come up with the same results with better optimized hardware.Article: 146951
On Sun, 04 Apr 2010 00:33:59 +0430, PureSine <Green.Tech.Coder@gmail.com> wrote: >Hello, I need to do some DSP operations preferably with Spartan 3. I >need to divide output of a fast DDS by a variable but XST says it can >only implement a divider with constants of power of 2. >One way would be to recursively subtract divisor from dividend but that >needs many cycles which is not suitable for me. I prefer to do this >digitally within FPGA. Is there any digital solution preferably with >Spatan ? If the divisor is a constant, or a small set of constants, simply multiply by the reciprocal. - BrianArticle: 146952
John_H <newsgroup@johnhandwork.com> wrote: (snip) > Great advice. You can also perform several stages of the division per > clock cycle reducing a 16-bit division to 4 clock cycles, for > instance. There are better ways to perform pipelined division but > you'll need to consider this approach regardless. If the clock rate is fixed, and you don't need throughput, then yet. Most FPGAs have an FF for each LUT, so pipelining is free. (snip of multiply instead of divide) > To understand a faster way to divide compared to "determining whether > you can subtract the divisor for each stage of the pipeline then > subtracting from or passing the previous value" you can instead > *always* subtract from a positive value and *always* add from a > negative value, simply appending a little arithmetic to the signs from > the intermediate stages to get the final result. Try doing some > binary long division by hand with the two approaches and you may see > how you can come up with the same results with better optimized > hardware. I haven't thought of it in terms of current FPGA hardware. That works if you can easily switch between add and subtract based on the previous cycle. I forget which FPGAs do that and which don't. Look up non-restoring division in any computer arithmetic book. -- glenArticle: 146953
On Apr 3, 4:03=A0pm, PureSine <Green.Tech.Co...@gmail.com> wrote: > Hello, I need to do some DSP operations preferably with Spartan 3. I > need to divide output of a fast DDS by a variable but XST says it can > only implement a divider with constants of power of 2. > One way would be to recursively subtract divisor from dividend but that > needs many cycles which is not suitable for me. I prefer to do this > digitally within FPGA. Is there any digital solution preferably with > Spatan ? > Google for LPM_DIVIDE and 220model.vhd http://www.google.com/webhp?sourceid=3Dnavclient&ie=3DUTF-8#hl=3Den&safe=3D= off&q=3Dlpm_divide+220model.vhd&aq=3Df&aqi=3D&aql=3D&oq=3D&gs_rfai=3D&fp=3D= 43dd59e47af515fb One link for a source file is... http://himac02.nbi.dk:8888/cgi-bin/viewvc.cgi/fmdd_bc/lpm/220model.vhd?view= =3Dmarkup&root=3Dcvs&sortdir=3Ddown LPM functions, while promoted by Altera, are also synthesizable (once you get the source files) for any device, not just Altera. For documentation on how to use lpm_divide, the Altera docs will help. Lpm_Divide will perform a pipeline divide, no constraints on powers of 2 and can compute a new output on every clock cycle. Kevin JenningsArticle: 146954
On 4/3/2010 9:03 PM, PureSine wrote: > Hello, I need to do some DSP operations preferably with Spartan 3. I > need to divide output of a fast DDS by a variable but XST says it can > only implement a divider with constants of power of 2. > One way would be to recursively subtract divisor from dividend but that > needs many cycles which is not suitable for me. I prefer to do this > digitally within FPGA. Is there any digital solution preferably with > Spatan ? > > Thanks Do the division in the DDS. HTH, Syms.Article: 146955
On 4/4/2010 12:33 AM, PureSine wrote: Thanks all very much for elegant solutions. I surely remember all of them for different applications but for current application I guess simplest solution is to just alter DDS code and implement division inside it as Symon said. I just need to subtract subtraction(division) operand from addition operand(of DDS) and as add operand is always bigger I don't need any signed operation. Thanks all again.Article: 146956
On 4/4/2010 7:31 AM, PureSine wrote: Correction- I need signed operation anyway but still seems this solution is the most appropriate for my application. thanks all.Article: 146957
PureSine <Green.Tech.Coder@gmail.com> wrote: >Hello, I need to do some DSP operations preferably with Spartan 3. I >need to divide output of a fast DDS by a variable but XST says it can >only implement a divider with constants of power of 2. >One way would be to recursively subtract divisor from dividend but that >needs many cycles which is not suitable for me. I prefer to do this >digitally within FPGA. Is there any digital solution preferably with >Spatan ? You can use a multiplier and fixed point arithmetics. If you define 1 as 0x8000 then a multiplying by 0x3000 means dividing by 2.667. Ofcourse you'll need to divide the output of the multiplier by 0x8000 but that is a matter of wiring the output of the multiplier so it skips the first 15 bits. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 146958
I have tried to convert the following verilog code manually in to
VHDL in order to use it in my project which is written in vhdl. But I
am not able to get the same RTL results. Would you help me in
converting the next module or tell me how to instantiate vhdl into
verilog please?
thanks in advance
=======Verilog code=========
`timescale 1ns / 1ps
module ac97 (ready,
command_address, command_data, command_valid,
left_data, left_valid,
right_data, right_valid,
left_in_data, right_in_data,
ac97_sdata_out, ac97_sdata_in, ac97_synch, ac97_bit_clock, reset
);
output ready;
input [7:0] command_address;
input [15:0] command_data;
input command_valid;
input [19:0] left_data, right_data;
input left_valid, right_valid;
output [19:0] left_in_data, right_in_data;
input ac97_sdata_in;
input ac97_bit_clock, reset;
output ac97_sdata_out;
output ac97_synch;
reg ready;
reg ac97_sdata_out;
reg ac97_synch;
reg [7:0] bit_count;
reg [19:0] l_cmd_addr;
reg [19:0] l_cmd_data;
reg [19:0] l_left_data, l_right_data;
reg l_cmd_v, l_left_v, l_right_v;
reg [19:0] left_in_data, right_in_data;
always @(posedge ac97_bit_clock) begin
// Generate the sync signal
if (reset) begin
ready <= 1'b0;
// synthesis attribute init of ready is "0";
ac97_sdata_out <= 1'b0;
// synthesis attribute init of ac97_sdata_out is "0";
ac97_synch <= 1'b0;
// synthesis attribute init of ac97_synch is "0";
bit_count <= 8'h00;
// synthesis attribute init of bit_count is "0000";
l_cmd_v <= 1'b0;
// synthesis attribute init of l_cmd_v is "0";
l_left_v <= 1'b0;
// synthesis attribute init of l_left_v is "0";
l_right_v <= 1'b0;
// synthesis attribute init of l_right_v is "0";
end
else begin
if (bit_count == 255)
ac97_synch <= 1'b1;
if (bit_count == 15)
ac97_synch <= 1'b0;
// Generate the ready signal
if (bit_count == 128)
ready <= 1'b1;
if (bit_count == 2)
ready <= 1'b0;
// Latch user data at the end of each frame. This ensures that the
// first frame after reset will be empty.
if (bit_count == 255)
begin
l_cmd_addr <= {command_address, 12'h000};
l_cmd_data <= {command_data, 4'h0};
l_cmd_v <= command_valid;
l_left_data <= left_data;
l_left_v <= left_valid;
l_right_data <= right_data;
l_right_v <= right_valid;
end
if ((bit_count >= 0) && (bit_count <= 15))
// Slot 0: Tags
case (bit_count[3:0])
4'h0: ac97_sdata_out <= 1'b1; // Frame valid
4'h1: ac97_sdata_out <= l_cmd_v; // Command address valid
4'h2: ac97_sdata_out <= l_cmd_v; // Command data valid
4'h3: ac97_sdata_out <= l_left_v; // Left data valid
4'h4: ac97_sdata_out <= l_right_v; // Right data valid
default: ac97_sdata_out <= 1'b0;
endcase
else if ((bit_count >= 16) && (bit_count <= 35))
// Slot 1: Command address (8-bits, left justified)
ac97_sdata_out <= l_cmd_v ? l_cmd_addr[35-bit_count] : 1'b0;
else if ((bit_count >= 36) && (bit_count <= 55))
// Slot 2: Command data (16-bits, left justified)
ac97_sdata_out <= l_cmd_v ? l_cmd_data[55-bit_count] : 1'b0;
else if ((bit_count >= 56) && (bit_count <= 75))
begin
// Slot 3: Left channel
ac97_sdata_out <= l_left_v ? l_left_data[19] : 1'b0;
l_left_data <= { l_left_data[18:0], l_left_data[19] };
end
else if ((bit_count >= 76) && (bit_count <= 95))
// Slot 4: Right channel
ac97_sdata_out <= l_right_v ? l_right_data[95-bit_count] : 1'b0;
else
ac97_sdata_out <= 1'b0;
bit_count <= bit_count+1;
end
end // always @ (posedge ac97_bit_clock)
always @(negedge ac97_bit_clock) begin
if ((bit_count >= 57) && (bit_count <= 76))
// Slot 3: Left channel
left_in_data <= { left_in_data[18:0], ac97_sdata_in };
else if ((bit_count >= 77) && (bit_count <= 96))
// Slot 4: Right channel
right_in_data <= { right_in_data[18:0], ac97_sdata_in };
end
endmodule
Article: 146959On Sun, 4 Apr 2010 23:23:33 -0700 (PDT), solomon Alemu <soloalemu@gmail.com> wrote: > I have tried to convert the following verilog code manually in to >VHDL in order to use it in my project which is written in vhdl. But I >am not able to get the same RTL results. Would you help me in >converting the next module or tell me how to instantiate vhdl into >verilog please? The code you posted looks like clean synchronous RTL, and therefore it should be very easy to translate into VHDL. The one possible problem is your use of synthesis attributes - you will need to look at the tool documentation to see how to write them in VHDL - if they are really necessary, which I doubt. Could you indicate what you mean by "not able to get the same RTL results"? You can't expect tools to give exactly the same gate-level results from two different but functionally identical pieces of code, but that is presumably not a problem. Instantiation of Verilog into VHDL is usually OK but there are many tool-dependent details. The FPGA synthesis tools usually do it without a murmur - have you tried? - but simulation can be a little more troublesome. The most common problem is case sensitivity (Verilog is case-sensitive, VHDL is not) and keyword clashes. I don't think you have any keyword problems here, and the names are consistetly lower-case, so that should all be OK. PLease come back if you have any specific issues with the translation, but I'm not going to do it all for you:-) >=======Verilog code========= [snipped] -- Jonathan BromleyArticle: 146960
Impact generates a TDO VERIFY command with incorrect data. If your player verifies, it will stop and complain early into the file. I count the verify commands that appear in the file, and only really honor the first two (during key programming). That works for me. MarcArticle: 146961
On Apr 5, 2:23=A0am, solomon Alemu <soloal...@gmail.com> wrote: > =A0 I have tried to convert the following verilog code =A0manually in to > VHDL =A0in order to use it in my project which is written in vhdl. But I > am not able to get the same RTL results. Would you help me in > converting the next module or tell me how to instantiate vhdl into > verilog please? > > thanks in advance > > =3D=3D=3D=3D=3D=3D=3DVerilog code=3D=3D=3D=3D=3D=3D=3D=3D=3D [snip] Xilinx ISE has a tool called "View HDL instantiation template" which automatically produced this VHDL instantiation you can cut and paste in your top level: -- VHDL Instantiation Created from source file ac97.v -- 09:23:22 04/05/2010 -- -- Notes: -- 1) This instantiation template has been automatically generated using types -- std_logic and std_logic_vector for the ports of the instantiated module -- 2) To use this template to instantiate this entity, cut-and-paste and then edit COMPONENT ac97 PORT( command_address : IN std_logic_vector(7 downto 0); command_data : IN std_logic_vector(15 downto 0); command_valid : IN std_logic; left_data : IN std_logic_vector(19 downto 0); left_valid : IN std_logic; right_data : IN std_logic_vector(19 downto 0); right_valid : IN std_logic; ac97_sdata_in : IN std_logic; ac97_bit_clock : IN std_logic; reset : IN std_logic; ready : OUT std_logic; left_in_data : OUT std_logic_vector(19 downto 0); right_in_data : OUT std_logic_vector(19 downto 0); ac97_sdata_out : OUT std_logic; ac97_synch : OUT std_logic ); END COMPONENT; Inst_ac97: ac97 PORT MAP( ready =3D> , command_address =3D> , command_data =3D> , command_valid =3D> , left_data =3D> , left_valid =3D> , right_data =3D> , right_valid =3D> , left_in_data =3D> , right_in_data =3D> , ac97_sdata_out =3D> , ac97_sdata_in =3D> , ac97_synch =3D> , ac97_bit_clock =3D> , reset =3D> ); As you can see, it has a nasty habit of ignoring your original order of ports and placing inputs first, but it saves some time, especially if you're not fluent in Verilog. HTH, GaborArticle: 146962
All,
Thanks for all the responses, and i apologize for being ambiguous. What we
are looking for is a predefined version macro that can be used as shown
below
`ifdef ISE_VER_11
code one way
`else
code another way
`endif
or even better,
`if ISE_VER >= 8
...
Thanks and Regards,
Vikram.
>On Apr 1, 4:02=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>> On Apr 1, 3:45=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>>
>>
>>
>> > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>>
>> > (snip)
>>
>> > > XST is a VHDL and Verilog synthesizer and will synthesis any HDL
that
>> > > it is provided. =A0The term MACRO has its orgins in schematic
design.
>> > > What are you really looking for?
>>
>> > It sounds like he is looking for something similar to what
>> > the way the C preprocessor is used in C. =A0I believe that MACRO
>> > has been used a lot longer than computerized schematic design,
>> > back to the beginnings of assembly programming.
>>
>> > I believe that verilog has something similar to the C preprocessor,
>> > I am not so sure about VHDL.
>>
>> > -- glen
>>
>> I almost struck the comment about schematics in my reply and I
>> probably should have. =A0I was thinking that the original poster might
>> be referring to the old Xilinx LogiBlox schematic macros that would be
>> automatically expanded =A0by the Xilinx tools.
>>
>> Ed McGettigan
>> --
>> Xilinx Inc.
>
>I think I know what the original poster is asking after...
>
>I have found some things that "just don't" synthesize properly with
>ISE-11. By that I mean that there are NO errors or additional
>warnings, but the resulting chip is dead, where it wasn't dead with
>version 10.
>
>By having a synthesize-time flag, one could create two different
>codes, and "if-def" according to which version of XST is being used.
>
>eg:
>
>`ifdef L.70 // this is 11.5
>foo <=3D ~bar;
>`else
>foo <=3D !bar;
>`endif
>
>Then again, I'm only guessing about what the OP was asking after...
>
>RK
>
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 146963Hi, I have a question about the multi-function pins in Spartan-6 FPGA (XC6SLX9). I would like to know if I can use the D0-D15 and A0-A25 config pins as general purpose IO pins because I am using a serial PROM to program the FPGA and so will not use BPI mode. I have read about the pins and I just want to be sure of that. Also. another question, the GCLK pins : can they be used as output when needed for clocks (clock outputs) ? This is needed in my design. I need some clock outputs from the FPGA to some other modules. The GCLK pin description says they are Input if they are used as clocks. Aditi.Article: 146964
rickman <gnuarm@gmail.com> writes: > It is just the repetition of the message I think. First, I guess I > don't agree that it is something that needs to be addressed in this > way. Others have used this sort of sig too and after some several > hundreds or thousands of times of seeing it it becomes an annoyance. I don't understand. You read signatures? And get annoyed by them? Why? It should be entirely voluntary. I at least don't display them usually, why would I? It's the message that's important. It's like complaining about repetitive headers... Or is this something that Google Groups users do?Article: 146965
On Apr 5, 10:37=A0am, Aditi <aditi.gro...@gmail.com> wrote: > Hi, > > I have a question about the multi-function pins in Spartan-6 FPGA > (XC6SLX9). > I would like to know if I can use the D0-D15 and A0-A25 config pins as > general purpose IO pins > because I am using a serial PROM to program the FPGA and so will not > use BPI mode. > I have read about the pins and I just want to be sure of that. Yes, you can use those pins as you wish, > Also. another question, the GCLK pins : can they be used as output > when needed for clocks (clock outputs) ? A clock output is no different from any other output, so you can use any output pin you like. Note that you may want to use the DDR flop for output clock forwarding (it's in the data sheet somewhere). Also, you can use your clock output with an external feedback trace and a DCM to ensure that your clock arrives at the destination when you want it to. -aArticle: 146966
In article <hp87mm$s7m$1@naig.caltech.edu>, gah@ugcs.caltech.edu says... > >In comp.arch.fpga MitchAlsup <MitchAlsup@aol.com> wrote: >(snip) > >> It was not so much that I was concentratng on Linpack, We (shebanow >> and I) were trying to build a machine that could perform as if it were >> a vector machine on vectorizable codes (without vector instructions:: >> i.e. native 88100 instructions at 6 per cycle) and also perform well >> on GCC-like spaghetti codes. Linpack (Matrix 300) was simply the >> vector code expample. > >The 360/91 was also designed to perform well on non-vectorized code. >Well, on the code generated for other 360's. Among others is >loop mode where for a small enough loop it stops fetching >instructions from memory (they are in a special cache). >The goal was one instruction per cycle. (With 750ns core it >wasn't likely to do more than that.) > Must have got that idea from the CDC 6600. >The 360/91 even had to handle self-modifying code, including >instructions that might have already been fetched. The IBM >Fortran library for OS/360 did use some self-modifying code. >(No recursion in Fortran 66 so it wasn't so hard to do.) > SMC was not allowed in the CDC instruction stack (i.e. non-coherent cache). - TimArticle: 146967
Hi,
It would seem the Lattice Mico32 support forum has gone dead (no posts/
replies since early February), so I'm asking this here in the hope
there's an lm32 guru somewhere out there...
I've (successfully) ported the LatticeMico32 CPU core to the Altera
Cyclone II (terASIC DE1 platform, aka Cyclone II FPGA Starter Board).
Caching seems to work, as do the WISHBONE interfaces (both of them). Now
I have a few questions about how the thing works.
- When the core is reset with the cache enabled, it takes a few seconds
(at a 25Hz clock rate) for the CPU to start executing instructions.
Nothing happens on the address or data buses during this delay, and
there's nothing about it in the Lattice manuals. Is there a reset
debounce delay somewhere in the LM32 logic, or is this just the cache
being cleared on startup?
- The LM32 has separate instruction and data buses -- the "instruction"
bus is read-only (the Wishbone WE line is tied low and DATA_O is
ignored). If I was to write to the instruction space, am I right in
thinking that this write would be sent over the "data" bus?
- It appears there is a way to disable the Instruction WISHBONE bus
(undefine CFG_IWB_ENABLED), but disabling this causes compile errors in
lm32_instruction_unit.v ("object wb_data_f is not declared"). Is this
supposed to work or am I straying into "Dragons Lurketh Here" territory?
(I wanted to have the CPU push everything over one bus so I didn't need
any multi-master arbitration logic).
- Does anyone have any example code for a WISHBONE multi-master arbiter?
Two-masters-into-one-bus sort of thing? I've got address decoding
working, but my external RAM is single-port, and I get the feeling an
8MByte dual-port RAM might be "just a bit" expensive.
- Straying close to the realms of "off topic" a bit here... but does
anyone have an example "LED blink" type program and linker script to
produce a flat binary for the lm32 (ideally using GNU as / ld)?
I've got what appears to be a working gcc / binutils toolchain (NOT
Theobroma's ancient, buggy monstrosity they laughably call a "port"), but
no instructions on what to do next... How *do* you make gcc/as/ld spit
out a flat binary?
At this point I just want to get the thing blinking LEDs or something;
I've hand-assembled a "copy switch input to LEDs" test, but assembling
code by hand is getting boring (although I did do it -- once -- for a
6502 CPU board that had a monitor ROM but no onboard assembler or HEX
download function -- "when the only tool you have is a hammer") :)
Thanks,
--
Phil.
usenet09@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace 09 with the last two digits of the current year
Article: 146968>>On 26/03/2010 10:38, weldat wrote: >>> Hi every body; >>> i am working on xilinx EDK with MicroBlaze soft core processor. i am >using >>> Virtex 5 ML506 platform studio and my EDK is EDK 9.2 >>> on this processor i am downloading C code for Elliptic curve >diffie-hellman >>> key exchange and it is done but result is not displayed on the >>> hyperterminal so is there any body who can help me how to fix my >problem? >>> but the connetion of the RS232_uart is working properly i have checked >it >>> with simple C code. the baud rate is all ok >>> thank you in advance. >>> kind regards >>> weldat >> >>I have no idea about your system, but hyperterminal is notoriously >>unreliable and entirely unsuitable to embedded development. Try a >>decent terminal emulator first to eliminate that source of problem. >>Many people (including me) like Tera Term Pro, but there are hundreds of >>alternatives. but when i power ON the FPGA(xilinx virtex 5 ML506) welcome to xilinx virtex 5 is displayed on the hyperterminal.The problem is when i download the C code for the elliptic curve diffie hellman key exchange on the FPGA the LEDs are blinking showing that downloading is performed but the result of the code is not displayed on the hyperterminal.Even i have checked for simple C codes of secure hash algorithm(SHA)and it works and result is displyed on the hyperterminal. but till now i did not fix why it is not displaying result of the elliptic curve diffie hellman key exchange. thank you weldat --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146969
Hi, I have one problem to extract single bit from std_logic_vector, with use of HEX suffix. Ex: signal out : std_logic; signal in : std_logic_vector(7 downto 0); out <= in(x"03"); I use HEX for compatibility with C source ... When I check syntax with ISE I obtain an error, why ? Thanks. secureasmArticle: 146970
On Tue, 2010-04-06 at 02:09 -0700, Kappa wrote: > Hi, > > I have one problem to extract single bit from std_logic_vector, with > use of HEX suffix. > > Ex: > > signal out : std_logic; > signal in : std_logic_vector(7 downto 0); > > out <= in(x"03"); > > I use HEX for compatibility with C source ... > > When I check syntax with ISE I obtain an error, why ? > > Thanks. > > secureasm Because you did not use hex integer but bit_vector/std_logic_vector. Hexadecimal integer constant would be 16#03#. JanArticle: 146971
On Tue, 6 Apr 2010 02:09:45 -0700 (PDT), Kappa <secureasm@gmail.com> wrote: >Hi, > >I have one problem to extract single bit from std_logic_vector, with >use of HEX suffix. > >Ex: > >signal out : std_logic; >signal in : std_logic_vector(7 downto 0); > >out <= in(x"03"); > >I use HEX for compatibility with C source ... > >When I check syntax with ISE I obtain an error, why ? > Because the index of a std_logic_vector is an integer (or subtype of integer) but X"03" specifies a bit-vector. You can express your index in base-16, but the syntax is out <= in(16#03#); - BrianArticle: 146972
Thanks at all, > Because the index of a std_logic_vector is an integer (or subtype of > integer) but X"03" specifies a bit-vector. I are not expert in VHDL ... > You can express your index in base-16, but the syntax is > out <= in(16#03#); This work very well. secureasmArticle: 146973
> - When the core is reset with the cache enabled, it takes a few seconds
> (at a 25Hz clock rate) for the CPU to start executing instructions.
> Nothing happens on the address or data buses during this delay, and
> there's nothing about it in the Lattice manuals. Is there a reset
> debounce delay somewhere in the LM32 logic, or is this just the cache
> being cleared on startup?
It should take one cycle per cache line to initialise the cache - not
several seconds though.
> - The LM32 has separate instruction and data buses -- the "instruction"
> bus is read-only (the Wishbone WE line is tied low and DATA_O is
> ignored). If I was to write to the instruction space, am I right in
> thinking that this write would be sent over the "data" bus?
Yes
> - It appears there is a way to disable the Instruction WISHBONE bus
> (undefine CFG_IWB_ENABLED), but disabling this causes compile errors in
> lm32_instruction_unit.v ("object wb_data_f is not declared"). Is this
> supposed to work or am I straying into "Dragons Lurketh Here" territory?
> (I wanted to have the CPU push everything over one bus so I didn't need
> any multi-master arbitration logic).
At one point in time you could disable the wishbone interface and just
use an EBR for instruction memory. Maybe that is no longer supported.
> - Does anyone have any example code for a WISHBONE multi-master arbiter?
> Two-masters-into-one-bus sort of thing? I've got address decoding
> working, but my external RAM is single-port, and I get the feeling an
> 8MByte dual-port RAM might be "just a bit" expensive.
Can't you use the code that is generated by Mico32's MSB?
> - Straying close to the realms of "off topic" a bit here... but does
> anyone have an example "LED blink" type program and linker script to
> produce a flat binary for the lm32 (ideally using GNU as / ld)?
> I've got what appears to be a working gcc / binutils toolchain (NOT
> Theobroma's ancient, buggy monstrosity they laughably call a "port"), but
> no instructions on what to do next... How *do* you make gcc/as/ld spit
> out a flat binary?
Why do you want flat? Are you sure you just don't want to convert your
ELF file to a binary? If so, you can do lm32-elf-objcopy -O binary
file.elf file.bin
Cheers,
Jon
Article: 146974On Tue, 06 Apr 2010 12:45:58 -0700, Jon Beniston wrote: > It should take one cycle per cache line to initialise the cache - not > several seconds though. I did have it running on a very slow clock -- it was actually 12.5Hz (as in, 12.5 cycles per second) so I could watch what it was doing in real- time. > At one point in time you could disable the wishbone interface and just > use an EBR for instruction memory. Maybe that is no longer supported. Certainly looks that way to me. >> - Does anyone have any example code for a WISHBONE multi-master >> arbiter? Two-masters-into-one-bus sort of thing? I've got address >> decoding working, but my external RAM is single-port, and I get the >> feeling an 8MByte dual-port RAM might be "just a bit" expensive. > > Can't you use the code that is generated by Mico32's MSB? MSB seems to use a lot of IP cores that use Lattice-specific synthesizer features or IP cores. Hardly a good thing when you're trying to make it all work on Altera hardware. > Why do you want flat? I basically want a binary image I can program into the Flash chip. I've written a linker script which seems to do what I want (for small assembler programs at least). Making it play nice with C will be the next step, then I can look at porting a bootloader across (probably Qi, U-Boot is an unfortunate victim of creeping featurism). The idea was to have a fast SPI Flash chip, some SDRAM, and a small M4K boot-ROM on the FPGA. The SDRAM is mapped at 0x0000_0000, but reads to that area go through a multiplexer. On powerup (or a RESET), the Mico32 reads from the BootROM. That BootROM copies the firmware off the flash chip and into SDRAM, writes to a register (which switches off the BootROM) and does a soft-reset. At the moment, I'm looking for a decent WISHBONE-compliant SDRAM core... preferably one that isn't GPL'd. -- Phil. usenet09@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "09" with the last two digits of the current year.
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