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Messages from 146850

Article: 146850
Subject: MSI for BMD design
From: Usama <usama817@gmail.com>
Date: Tue, 30 Mar 2010 04:28:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
hi

i am working on BMD design and using xapp1052 to implement it. I need
to use multiple vectors for doing MSI to use it with my application.

Can anyone guide me how can i do it or refer to some material which
can help me doing it.

Regards

Usama

Article: 146851
Subject: MSI for BMD design
From: Usama <usama817@gmail.com>
Date: Tue, 30 Mar 2010 04:28:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
hi

i am working on BMD design and using xapp1052 to implement it. I need
to use multiple vectors for doing MSI to use it with my application.

Can anyone guide me how can i do it or refer to some material which
can help me doing it.

Regards

Usama

Article: 146852
Subject: Re: XST optimization
From: Jason Thibodeau <jason.p.thibodeau@gmail.com>
Date: Tue, 30 Mar 2010 08:04:21 -0400
Links: << >>  << T >>  << A >>
On 03/30/2010 04:13 AM, Alan Fitch wrote:
> On 29/03/2010 20:36, Jason Thibodeau wrote:
>
> e raison d'Ítre of HDL synthesizers is to produce an optimized
>>> design that matches the HDL input code. If the tools didn't do this
>>> then they no one would use or buy them.
>>>
>>> If the gate/net was optimized away then it wasn't needed. Either the
>>> input (registers and IO pads) equation cone had redundancies or there
>>> was a redundancy to the final output (registers or IO pads). The
>>> synthesizer will also move the equations around to optimize timing. A
>>> signal that you have coded to appear early in an multi-level logic
>>> cone may be pushed to later in the logic cone to improve the timing.
>>>
>>> If the synthesizer changed the logic then it would be a bug. Since
>>> you have said that this happens in two different tools it is very
>>> unlikely to be a bug.
>>>
>>> I think that you mentioned that you had OR'ed all of the outputs
>>> together to keep all of the logic from being trimmed. I would suggest
>>> instead that you register all of the outputs and then OR the registers
>>> outputs to keep the logic. Optimizing across the register boundaries
>>> is available in some synthesizers, but there is usually an option to
>>> enable/disable the feature.
>>>
>>> Ed McGettigan
>>> --
>>> Xilinx Inc.
>>>
>>
>> The logic that is being optimized out is a simple comparator. And gates
>> in roughly a tree structure, with a final or gate to feed it back into
>> the 'main' circuit.
>>
>> The or gate was not implemented to keep the tool from trimming the
>> logic, rather it was necessary for proper function of the circuit.
>>
>> What I'm working on, I need to be able to place these gates into
>> specific portions of the chip. This is why I cannot have them optimized
>> or absorbed into other CLB's.
>>
>> I'm really just trying to figure out if it is possible to place an
>> attribute before an instantiation so it will not be trimmed. I realize
>> what I want may not be a standard request, but I just want to make it
>> work.
>>
>> Thanks for all your help, everyone.
>>
>
> Hi Jason,
> I still don't really understand - but I suspect there may be a
> misunderstanding here. If you say the gates are "optimized out", to me
> that means, as Ed and others have said, that they are redundant - to put
> it bluntly, the tool is right and you are wrong :-;
>
> However I wonder if what you really mean is that the functionality of
> those gates has been merged in with other logic, and you want to keep it
> separate?
>
> If that is the case, then you need to put those gates in a separate
> component and tell the tool to preserve the hierarchy, and to keep that
> component using whatever magic spells are required by XST,
>
> regards
> Alan
>
>
Alan,

I believe you have nailed the problem right on the head. I do not 
believe that XST is blatantly removing the gates, but I did suspect the 
gates are being absorbed into other LUTs. This, of course, would not 
change teh functionality, but would affect my ability to place and route 
these specific gates. I think my next plan of action is to place all 
these gates into a separate component, as you suggest.

For the others, while you may disagree with my methods, I can guarantee 
this:

1. I have a benchmark which must remain in tact, except for the gates I 
am placing.
2. These gates are integral to my design, and their placement is more 
important than their existence.
3. I have revealed all I am allowed to reveal, this is why I have been 
so vague. Believe me, I'd love to give you all the code so you can see 
exactly what I am talking about, but others above me prevent this from 
happening.

I appreciate all the help, and the ideas you have suggested. I still 
have a lot to learn, and you all give me great area in which to research.
-- 
Jason Thibodeau

Article: 146853
Subject: Re: Which is the most beautiful and memorable hardware structure in a
From: Jonathan Bromley <spam@oxfordbromley.plus.com>
Date: Tue, 30 Mar 2010 05:45:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 30, 10:38=A0am, n...@cam.ac.uk wrote:

> Yes. =A0There were and are more bizarre ones, but they are Not Memorable
> (see Sellars and Yeatman).

Ooooh, I like that.  Always good to bring a bit of high culture
into the discussion.

It may be Memorable, hut was it a Good Thing?

_Sellar_ and Yeatman, I think you'll find (without the trailing 's').

Thanks for tickling a long-dormant and much cherished memory.
--
Jonathan Bromley

Article: 146854
Subject: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
From: Patrick Maupin <pmaupin@gmail.com>
Date: Tue, 30 Mar 2010 06:30:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 30, 6:14=A0am, Bill Valores <bill.valo...@gmail.com> wrote:
> Thank you for your answers.
>
> I take it that they're serious about having some 4000 taps. Also, I
> keep hearing (reading, actually) about the variable phase shifter
> taking a long time to acknowledge its commands. Make me wonder why,
> since all we're asking for is "what you did right now, just another
> tap".
>
> I wish someone revealed what really goes on there, and how they
> reached those peculiar equations. All this feels like witchcraft.
>
> I'm going to experiment a bit. The problem is that my experiments will
> be on a stepping 0 FPGA, while the target board will have a stepping 1
> high speed grade chip. With all this mystery, I wonder if that's going
> to make a difference (and they obviously did something with the DCM
> between the steppings).
>
> Bill.

$179.00 gets you a XC3S1200E on a Digilent Nexys2 board.  Add 30 bucks
or so for overnight shipping, and I don't know why you have to be on a
different stepping...

Regards,
Pat

Article: 146855
Subject: Re: desgin suspended
From: Gabor <gabor@alacron.com>
Date: Tue, 30 Mar 2010 06:50:14 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 29, 5:19=A0am, Symon <symon_bre...@hotmail.com> wrote:
> On 3/29/2010 6:28 AM, life.is.best wrote:
>
> > I bought evaluation board form one american company.
> > This boad was =A02 month delayed.
> > After I received it ,the contents is missing.
> > Oh my good!.
> > I'm extermly =A0disappointed.
>
> http://www.azlyrics.com/lyrics/neilyoung/pieceofcrap.html

While you're at it...

http://www.lyricsdomain.com/6/frank_zappa/flakes.html

Article: 146856
Subject: Re: upgrading to ISE 11.x
From: Gabor <gabor@alacron.com>
Date: Tue, 30 Mar 2010 06:57:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 29, 10:36=A0pm, Patrick Maupin <pmau...@gmail.com> wrote:
> On Mar 29, 9:30=A0am, colin <colin_toog...@yahoo.com> wrote:
>
> > I need to start using ISE 11.4 instead of 10.1
>
> > Copy a full project using explorer and open with 10.1, all paths are
> > relative and you have a "new project"
>
> > Copy a full project with explorer and open with 11.4 and you need to
> > upgrade the project.
>
> > Start editing stuff and then discover that the project upgrade used
> > absolute pathnames and I've been editing the original files.
>
> > Hello XILINX this is the real world calling........... is anyone
> > there?..........................
>
> That's just Xilinx's little way of gently reminding you that you
> really *should* be using verson control on your sources ;-)

Another reason to stay away from the latest and greatest parts
until the tools stabilize.  My approach so far with Xilinx
has been to skip all odd-numbered tool versions.  I've worked
with Foundation 2.x, 4.x, then ISE 6.x 8.x and now 10.x with
relatively little discomfort.  Looking at newsgroup traffic it
seem I missed a lot of "excitement" by skipping the odd versions :)

Article: 146857
Subject: Re: Xilinx Webpack v11.4 availability
From: "vragukumar" <vragukumar@n_o_s_p_a_m.n_o_s_p_a_m.signalogic.com>
Date: Tue, 30 Mar 2010 09:34:42 -0500
Links: << >>  << T >>  << A >>
Ed,

Thank you for your response. Could you please let me know where i can find
the Xilinx update tool ? Is it a utility that gets installed along with
Webpack v11.1 or does it need to be downloaded separately ?

Thanks and Regards,
Vikram.

>ISE 11.5 is a combination of ISE 11.1 + Updates, so the first step is
>to install ISE 11.1 and then to use the Xilinx Update tool  upgrade to
>11.5.
>
>I wish that this was easier, but unfortunately this is current
>installation flow for 11.x tools.
>
>Ed McGettigan
>--
>Xilinx Inc.
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 146858
Subject: Re: Xilinx Webpack v11.4 availability
From: "vragukumar" <vragukumar@n_o_s_p_a_m.n_o_s_p_a_m.signalogic.com>
Date: Tue, 30 Mar 2010 09:39:57 -0500
Links: << >>  << T >>  << A >>
Ed,

Thank you for your response. Could you please let me know where i can find
the Xilinx update tool ? Is it a utility that gets installed along with
Webpack v11.1 or does it need to be downloaded separately ?

Thanks and Regards,
Vikram.

>ISE 11.5 is a combination of ISE 11.1 + Updates, so the first step is
>to install ISE 11.1 and then to use the Xilinx Update tool  upgrade to
>11.5.
>
>I wish that this was easier, but unfortunately this is current
>installation flow for 11.x tools.
>
>Ed McGettigan
>--
>Xilinx Inc.
>	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 146859
Subject: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
From: Bill Valores <bill.valores@gmail.com>
Date: Tue, 30 Mar 2010 08:28:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
You definitely have a point there. With a board on my table (which I
obviously have everything set up with) I didn't even think in that
direction. Now it's my laziness and having a lot of handy
communication features with the current board vs. the risk that the
test won't be valid.

Plus the fact that the clock source will be the same on my board and
the one I'm targeting. I understand that clock jitter has been a
primary suspect where problems have arisen.

I guess I'll start with my board and see how stable this feels.

Thanks,
Bill

On Mar 30, 3:30=A0pm, Patrick Maupin <pmau...@gmail.com> wrote:
>
> $179.00 gets you a XC3S1200E on a Digilent Nexys2 board. =A0Add 30 bucks
> or so for overnight shipping, and I don't know why you have to be on a
> different stepping...
>
> Regards,
> Pat


Article: 146860
Subject: Re: Xilinx Webpack v11.4 availability
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Tue, 30 Mar 2010 08:32:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 30, 7:34=A0am, "vragukumar"
<vragukumar@n_o_s_p_a_m.n_o_s_p_a_m.signalogic.com> wrote:
> Ed,
>
> Thank you for your response. Could you please let me know where i can fin=
d
> the Xilinx update tool ? Is it a utility that gets installed along with
> Webpack v11.1 or does it need to be downloaded separately ?
>
> Thanks and Regards,
> Vikram.
>
> >ISE 11.5 is a combination of ISE 11.1 + Updates, so the first step is
> >to install ISE 11.1 and then to use the Xilinx Update tool =A0upgrade to
> >11.5.
>
> >I wish that this was easier, but unfortunately this is current
> >installation flow for 11.x tools.
>
> >Ed McGettigan
> >--
> >Xilinx Inc.
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

The Xilinx Update Tool will be installed along with software.  For
Windows it will be under
Start->Xilinx ISE Design Suite 11->Accessories->Check for Updates

Ed McGettigan
--
Xilinx Inc.

Article: 146861
Subject: Using Verilog Macros with Arguments
From: "gaurang4040" <gaurang.a.chitroda@n_o_s_p_a_m.gmail.com>
Date: Tue, 30 Mar 2010 10:47:40 -0500
Links: << >>  << T >>  << A >>
Hi all,

I want to used parameterized Verilog macros in my code.
It looks somewhat as shown below:

////////////////////////////////////////////////////////////
`define ACTIVE_EDGE posedge 
parameter ISO_SENSE=1;
        always @(`ACTIVE_EDGE isolation_ctrl) 
           if(isolation_ctrl==ISO_SENSE) 
              power_iso_flag=0;
////////////////////////////////////////////////////////////


I used "tick define" macro and parameter as I need my code to be somewhat
generic.

Now, I want to extend the same for the following case:
(1) isolation_ctrl can be a vector with width N and it will have
corresponding ISO_SENSE values. That is,

          logic [NO-1:0]  isolation_ctrl;
          bit    [NO-1:0]   ISO_SENCE;
(2) If ISO_SENCE[i] is 1, the macro `ACTIVE_EDGE should take value posedge.
Whereas, it should take negedge for ISO_SENCE[i]=0.

I tried to do so using generate and macro with argument as follows:


////////////////////////////////////////////////////////////
`define str1 posedge 
`define str2 negedge 
`define ACTIVE_ISO_EDGE(a) ( a ? `str1 : `str2 ) 
.. 
module abc ( ...); 
.. 
.. 
bit [3:0] sences='{1, 0, 0, 1}; 
.. 
.. 
generate 
genvar j; 

   for(i=0; i<NO_OF_DOMAINS; i++) 
   begin 
        always @( `ACTIVE_ISO_EDGE( sences[i]) isolation_ctrl[i] ) 
            if(isolation_ctrl[i]==ISO_SENSE[i]) 
                power_iso_flag[i]=0; 
    end 

endgenerate 
.. 
.. 
endmodule
////////////////////////////////////////////////////////////


However, it gives the following error:

Error-[SE] Syntax error 
Following verilog source has syntax error : 
"env/assertions.sv", 309 (expanding macro): token is 'posedge' 
always @(`ACTIVE_ISO_EDGE(ds[j]) isolation_ctrl_for_all_domains[j])


Can anyone please help me solve this? I am not getting the exact way in
which I can employ macros to make everything generic along with generate.
Hoping for some useful comments. :)


Thanks,
Gaurang

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 146862
Subject: Re: Which is the most beautiful and memorable hardware structure in a
From: timcaffrey@aol.com (Tim McCaffrey)
Date: Tue, 30 Mar 2010 16:52:54 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <hosgq9$h5m$1@smaug.linux.pwf.cam.ac.uk>, nmm1@cam.ac.uk says...
>
>In article 
<27ebdb37-e3ba-4559-be7d-d7f3b6613d77@30g2000yqi.googlegroups.com>,
>MitchAlsup  <MitchAlsup@aol.com> wrote:
>>The most memorable hardware structure is the vector indirect
>>addressing mode.
>
>Yes.  There were and are more bizarre ones, but they are Not Memorable
>(see Sellars and Yeatman).
>
>
>Regards,
>Nick Maclaren.

I'll see your vector indirect mode, and add segment descriptors!

(Really, is anything more compilcated than VALC?)
(Unisys Clearpath Libra (MCP) systems)
(aka. A series)

		- Tim


Article: 146863
Subject: Re: Xilinx Webpack v11.4 availability
From: "cfelton" <cfelton@n_o_s_p_a_m.n_o_s_p_a_m.ieee.org>
Date: Tue, 30 Mar 2010 12:13:00 -0500
Links: << >>  << T >>  << A >>
A0 =A0 =A0 =A0
>> Posted throughhttp://www.FPGARelated.com
>
>The Xilinx Update Tool will be installed along with software.  For
>Windows it will be under
>Start->Xilinx ISE Design Suite 11->Accessories->Check for Updates
>

I thought I read some where that this latest release was specific to a
Virtex6 bug.  And it was recommended not to update unless you need this
specific Virtex6 change.  Is this true?  I don't remember where I read this
but it seem to suggest that most should stay at 11.3?

chris	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 146864
Subject: Re: Which is the most beautiful and memorable hardware structure in
From: Jason Zheng <Xin.Zheng@jpl.nasa.gov>
Date: Tue, 30 Mar 2010 10:41:01 -0700
Links: << >>  << T >>  << A >>
On Sun, 28 Mar 2010 19:06:23 -0700 (PDT)
Weng Tianxiang <wtxwtx@gmail.com> wrote:

<snip>

> And it is strange enough that after PC was created, no big new
> structure in CPU has ever invented. MESI protocol? No. Changing 1 core
> to 2 core, or even 8 cores is considered as a big invention? No.

My favorite is the Translation Look-aside Buffers (TLB), of course
invented by the IBM engineers. You have to appreciate the way it sounds
(and its irrelevance to its true purpose).

Article: 146865
Subject: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
From: austin <austin@xilinx.com>
Date: Tue, 30 Mar 2010 10:56:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
Andrew,

1ns is a LOT of jitter (in my book, that is).  20% of the clock period
is also a lot of jitter (to me).

Depends on what you define as "a lot."

Austin


Article: 146866
Subject: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
From: Symon <symon_brewer@hotmail.com>
Date: Tue, 30 Mar 2010 19:03:28 +0100
Links: << >>  << T >>  << A >>
On 3/30/2010 6:56 PM, austin wrote:
> Andrew,
>
> 1ns is a LOT of jitter (in my book, that is).  20% of the clock period
> is also a lot of jitter (to me).
>
> Depends on what you define as "a lot."
>
> Austin
>
Whether it is a lot or not depends on the frequency of the jitter. What 
are we talking about here? Cycle-cycle jitter?

Syms.

Article: 146867
Subject: Re: Which is the most beautiful and memorable hardware structure in a
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Tue, 30 Mar 2010 11:19:30 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 30, 10:41=A0am, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:
> On Sun, 28 Mar 2010 19:06:23 -0700 (PDT)
>
> Weng Tianxiang <wtx...@gmail.com> wrote:
>
> <snip>
>
> > And it is strange enough that after PC was created, no big new
> > structure in CPU has ever invented. MESI protocol? No. Changing 1 core
> > to 2 core, or even 8 cores is considered as a big invention? No.
>
> My favorite is the Translation Look-aside Buffers (TLB), of course
> invented by the IBM engineers. You have to appreciate the way it sounds
> (and its irrelevance to its true purpose).

Haha, some people don't appreciate stack segment and stack pointer.

There two reasons I appreciate most:
1. It is very simple;
2. I handles all subroutine calls with prefect beauty for last 60
years.

3 years ago when I first read BW transform, I was in awe in such a way
that made me to excitement for a week.

But sadly I found that BW transform cannot get the high compression
rate even though we don't pay attention on the time the transform
needs.

I joined compression group and found there were few discussions on the
BW transform, the main reason is its not highest compression rate.

Weng

Article: 146868
Subject: Re: Which is the most beautiful and memorable hardware structure in a CPU?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 30 Mar 2010 19:46:47 +0000 (UTC)
Links: << >>  << T >>  << A >>
In comp.arch.fpga Jason Zheng <Xin.Zheng@jpl.nasa.gov> wrote:
(snip)
 
> My favorite is the Translation Look-aside Buffers (TLB), of course
> invented by the IBM engineers. You have to appreciate the way it sounds
> (and its irrelevance to its true purpose).

If you read the IBM description of virtual storage, you would 
first believe that it went to the segment and page tables for
each reference.  That would make everything three times slower,
so there is the TLB to speed thing up.  Always interesting to
me is that the IBM name stuck, unlike many IBM names.
(Data set, IPL, to name two.)

The TLB is carefully documented by IBM, including the PTLB
instruction.  (Purge TLB.)   On the other hand, IBM doesn't
document much about the data and/or instruction cache, leaving
that up to the implementations to get right.  Also, regarding
virtual storage, there is the STO (segment table origin) cache
that is also not documented by the architecture, but needed
to speed thing up in the case of multiple address spaces.

-- glen


Article: 146869
Subject: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
From: austin <austin@xilinx.com>
Date: Tue, 30 Mar 2010 13:25:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
Good Question!

I am presuming it is peak to peak jitter, but I may be incorrect...

I will go ask.

Austin

Article: 146870
Subject: Re: Xilinx Webpack v11.4 availability
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Tue, 30 Mar 2010 13:30:25 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 30, 10:13=A0am, "cfelton"
<cfelton@n_o_s_p_a_m.n_o_s_p_a_m.ieee.org> wrote:
> A0 =3DA0 =3DA0 =3DA0
>
> >> Posted throughhttp://www.FPGARelated.com
>
> >The Xilinx Update Tool will be installed along with software. =A0For
> >Windows it will be under
> >Start->Xilinx ISE Design Suite 11->Accessories->Check for Updates
>
> I thought I read some where that this latest release was specific to a
> Virtex6 bug. =A0And it was recommended not to update unless you need this
> specific Virtex6 change. =A0Is this true? =A0I don't remember where I rea=
d this
> but it seem to suggest that most should stay at 11.3?
>
> .chris =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

If you aren't using Spartan-6 or Virtex-6 then 11.4 would be the
latest version for the other families.

Ed McGettigan
--
Xilinx Inc.

Article: 146871
Subject: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
From: austin <austin@xilinx.com>
Date: Tue, 30 Mar 2010 13:41:48 -0700 (PDT)
Links: << >>  << T >>  << A >>
Peak to peak,

Austin

Article: 146872
Subject: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 30 Mar 2010 15:42:28 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 30, 1:56=A0pm, austin <aus...@xilinx.com> wrote:
> Andrew,
>
> 1ns is a LOT of jitter (in my book, that is). =A020% of the clock period
> is also a lot of jitter (to me).
>
> Depends on what you define as "a lot."
>
> Austin

In my communications days, 1ns of peak-to-peak jitter is tiny.  That
would almost qualify as jitter-free by some accounts.  Didn't you come
from that background, Austin?

If a PLL is used for jitter cleanup, the 0.15UI or 0.20UI levels for
the high frequency end of the jitter tolerance are common with lower
frequency values that start up a 20dB/decade slope as the frequency
goes lower corresponding to a required limit on the filter pole in the
PLL loop filter.  If you start using rates at 155Mb/s and below, 1ns
peak-to-peak jitter is the proverbial drop in the bucket.

The whole reason PLLs were so good at jitter cleanup is that the phase
comparator runs at a remarkably lower frequency allowing offsets
significantly greater than several unit intervals.  While silicon PLLs
are higher in frequency with higher phase comparator frequencies, they
shouldn't be *that* much higher.

Article: 146873
Subject: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
From: -jg <jim.granville@gmail.com>
Date: Tue, 30 Mar 2010 16:58:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 31, 10:42=A0am, John_H <newsgr...@johnhandwork.com> wrote:
>
> The whole reason PLLs were so good at jitter cleanup is that the phase
> comparator runs at a remarkably lower frequency allowing offsets
> significantly greater than several unit intervals. =A0While silicon PLLs
> are higher in frequency with higher phase comparator frequencies, they
> shouldn't be *that* much higher.

are you assuming a 'classic PLL' design ? - it is unlikely the FPGA
PLLs are classic in nature, but are more likely to have 'other tricks'
and shortcuts to integrate better in digital process.

-jg

Article: 146874
Subject: Re: desgin suspended
From: Symon <symon_brewer@hotmail.com>
Date: Wed, 31 Mar 2010 01:01:26 +0100
Links: << >>  << T >>  << A >>
On 3/30/2010 2:50 PM, Gabor wrote:
> On Mar 29, 5:19 am, Symon<symon_bre...@hotmail.com>  wrote:
>> On 3/29/2010 6:28 AM, life.is.best wrote:
>>
>>> I bought evaluation board form one american company.
>>> This boad was  2 month delayed.
>>> After I received it ,the contents is missing.
>>> Oh my good!.
>>> I'm extermly  disappointed.
>>
>> http://www.azlyrics.com/lyrics/neilyoung/pieceofcrap.html
>
> While you're at it...
>
> http://www.lyricsdomain.com/6/frank_zappa/flakes.html

The most beautiful and memorable thing in CAF is that you are regularly 
humbled!

"California's got the most of them!"

Of course, personally, would never go to such a debauched state. Ahem.

Cheers!



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