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On Wed, 17 Mar 2010 07:37:19 -0000 "HT-Lab" <hans64@ht-lab.com> wrote: > [snip] > > There might be some fixes in ISE 11.5 which was release yesterday. > From the website: > > "11.5 includes important updates and supports production devices for > the Virtex-6 and Spartan-6 families. However, several workarounds may > be required for Virtex-6 and some Spartan-6 customers using 11.5. > Please review Answer Record 32147 before you upgrade to 11.5. These > workarounds will be addressed in 12.1, scheduled for May 2010. > Designers targeting families other than Virtex-6 or Spartan-6 do not > need to install 11.5. To ensure that ISE Design Suite functions > properly, it is essential that all 11.5 updates are applied together." > There's an 11.5 now? But I just installed 11.4 a couple of months ago. And they're swearing up and down that 12.1 will be out in April. It's like this never-ending cycle of two steps forward, one step back, and one big jump 30 meters sideways with a double twist. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 146426
On Mar 10, 12:24=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Mar 10, 10:06=A0am, Andy <jonesa...@comcast.net> wrote: > > > On Mar 9, 12:15=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > I would strongly encourage you to change the RESET function from > > > asynchronous to synchronous. > > > On what basis do you make this recommendation, and what does this have > > to do with latches? > > > Andy > > Synchronous versus asynchronous resets have been discussed at length > in other threads. > > Asynchronous resets have their place in a designer's toolbox, however > they should be used sparingly. =A0Some reasons to use these are for > handshakes crossing clock domains, anticipated loss of clock and > asynchronous inputs to the synchronous domain. > > In a synchronous domain, such as the original state machine example, > the asynchronous functionality offers no additional benefit in FPGAs > as the area cost is identical for both. > > Asynchronously asserting and de-asserting a reset across multiple > registers may/will result in the registers being released before and > after a clock edge due to large net delay and skew on the reset net. > This will result in different parts of a design coming out of reset > across clock boundaries and being out of sync with each other. I know Altera's Quartus Timing Analyzer has recovery/removal analysis. > > Synchronous resets simplify timing analysis and timing closure without > having to worry about the consequences of the asynchronous functions > and how to correctly constrain them. I have not used Xilinx devices with Synchronous resets. I am curious is it ever possible that the clock may stop before the reset event and then subsequently the clock appears after the reset event passes thereby not initializing the logic? > > I often see problems with FPGA designs that are built with > asynchronous resets, but I have yet to see a problem with a FPGA > design that was traced to a synchronous reset. > > In an FPGA there is no downside to a synchronous reset, but there are > many pitfalls with an asynchronous reset. > > None of this has anything to do with a latch, which you also want to > avoid using in an FPGA. > > Ed McGettigan > -- > Xilinx Inc.Article: 146427
On Mar 16, 11:44=A0pm, Kim Enkovaara <kim.enkova...@iki.fi> wrote: > Weng Tianxiang wrote: > > I want to buy books on =A0CMOS digital circuit designs. Any advice on > > which is the best book on CMOS digital circuit design? > > At least "Nanometer CMOS ICs, From Basics to ASICs" written by Harry > Veendrick is quite nice overall book and is up to date with the > technology. The only problem with the book is the price, which is > quite high. > > --Kim Hi Kim, Thank you for your recommendation. The book contains materials of full procedures to make an ASIC in nanometer CMOS. I just want CMOS logic circuit in nanometer in 32um technology, for example, domino logic, time borrowing, how to expand an adder operation into 15 levels and something like that. I have ordered two books on Internet: 1. Principles of CMOS VLSI Design (Hardcover), second edition, 1999 ~ Neil H. E. Weste (Author), Kamran Eshraghian (Author) $0.01 + $3.99shipping 2. Logical Effort: Designing Fast CMOS Circuits (The Morgan Kaufmann Series in Computer Architecture and Design) by Ivan Sutherland, Robert F. Sproull, and David Harris (Paperback - Feb. 16, 1999) Buy new: $69.95 $62.95 7 new from $30.00 16 used from $24.25 I may buy another book "Principles of CMOS VLSI Design (Hardcover)", third edition, 2010, written by Neil H. E. Weste and David Harris when I finish reading the second edition. WengArticle: 146428
Re: bashing Xilinx software ... S6 was designed for cost (low) and power (low). We surveyed customers, and asked them what they wanted. And, we listened to them. Unfortunately, we have trained customers since the first Spartan device, that Spartan of the next node, could be used to replace a Virtex of the previous node... While that may have sometimes been true, S6 WAS NOT designed to cannibalize V5 sockets, and is designed to meet better price, and power points than Spartan 3, 3A, 3E. So, yes, the software will work very very hard to meet an unrealistic expectation of timing. And it might fail in the larger S6 parts to meet said unrealistic goals. That said, the software has actually improved with every release (in my opinion, as an actual user). Does the software have to improve further: yes, it does. You can always do a better job with software. But, I would always choose the latest software, and the latest hardware for any new project: all the attention is on it, the price curve will be the steepest (price will fall faster), and it will have the best support. Come on folks, this used to be a real forum, with useful information. Lately, this is like an old folks home, with everyone complaining about their ailments.... Did Xilinx, by creating their own user forums, completely kill c.a.f? If it goes on like this much longer, I will delete my link to it .... no one even bothers to email google to get rid of the spam here! (As a test, I emailed google, and they removed the spam I noted in the email to them -- the "report spam" button does nothing) AustinArticle: 146429
On Mar 17, 2:02=A0pm, austin <aus...@xilinx.com> wrote: > Re: bashing Xilinx software ... > > S6 was designed for cost (low) and power (low). > > We surveyed customers, and asked them what they wanted. > > And, we listened to them. > > Unfortunately, we have trained customers since the first Spartan > device, that Spartan of the next node, could be used to replace a > Virtex of the previous node... > > While that may have sometimes been true, S6 WAS NOT designed to > cannibalize V5 sockets, and is designed to meet better price, and > power points than Spartan 3, 3A, 3E. > > So, yes, the software will work very very hard to meet an unrealistic > expectation of timing. =A0And it might fail in the larger S6 parts to > meet said unrealistic goals. > > That said, the software has actually improved with every release (in > my opinion, as an actual user). > > Does the software have to improve further: =A0yes, it does. =A0You can > always do a better job with software. > > But, I would always choose the latest software, and the latest > hardware for any new project: =A0all the attention is on it, the price > curve will be the steepest (price will fall faster), and it will have > the best support. > > Come on folks, this used to be a real forum, with useful information. > > Lately, this is like an old folks home, with everyone complaining > about their ailments.... > > Did Xilinx, by creating their own user forums, completely kill c.a.f? > If it goes on like this much longer, I will delete my link to it .... > no one even bothers to email google to get rid of the spam here! (As a > test, I emailed google, and they removed the spam I noted in the email > to them -- the "report spam" button does nothing) > > Austin Right on, Austin ! Spartan is for low cost and low power, do not complain about the performance Virtex is for features and performance, do not complain about the price. Peter Alfke, from his "old folks home" (really my own living room)Article: 146430
Hi all, I am working on a new design and have chosen the Spartan 6 family FPGA for it. I was looking to see if there is a an on-chip PROM on any of the Spartan 6 FPGAs. I could not find about it in the datasheet. But if there is something that I am missing or if there is any other series of FPGAs with on-chip PROM, do let me know. Thank you, Aditi Akula.Article: 146431
On Mar 18, 10:02=A0am, austin <aus...@xilinx.com> wrote: > > But, I would always choose the latest software, and the latest > hardware for any new project: =A0all the attention is on it, the price > curve will be the steepest (price will fall faster), and it will have > the best support. Really ? That claim rather stretches credibility. Designers should prudently choose the latest STABLE software release, and the newest STOCKED products ( and even that assumes the claims of lower price really ARE absolute, and not marketing spin of lowest price per bit, or mm2, or Mhz, or whatever...) There are quite a few examples where the claims of "lowest-cost" are creative at best, and cannot be banked. (ie they fail any absolute test) Sounds like John would be only too happy to 'choose the latest STABLE software release' to me.... As for "S6 ... is designed to meet better price, and power points than Spartan 3, 3A, 3E.", right now, the smallest S6 showing is BGA324 $33.14 - you might like to re-check how many 'older' parts, have better price points! I'm looking at a product right now, that has been 'released' for ~18 months, and still the 'greenness' shows in the docs, and software. The final decision on if we can risk that, has not yet been made. The 'latest' usually carries an implementation cost. -jgArticle: 146432
On 3/16/2010 10:59 PM, Andrew Holme wrote: > Is AR#21774 the only official statement from Xilinx on this, or have I > missed something? > > I want to mess about with non-standard load impedances. > > How do they maintain the common mode voltage? Do they string a potential > divider between the outputs and servo the centre voltage to half-rail? > > Anyone know for sure? > > TIA > > Use the IBIS files. HTHArticle: 146433
On 3/17/2010 9:02 PM, austin wrote: > > Did Xilinx, by creating their own user forums, completely kill c.a.f? > If it goes on like this much longer, I will delete my link to it .... Oh no, don't do that!! RIP, Syms.Article: 146434
On Wed, 17 Mar 2010 15:38:31 -0700 (PDT), Peter Alfke <alfke@sbcglobal.net> wrote: >On Mar 17, 2:02 pm, austin <aus...@xilinx.com> wrote: >> Re: bashing Xilinx software ... >> >> S6 was designed for cost (low) and power (low). >> >> We surveyed customers, and asked them what they wanted. >> >> And, we listened to them. >> >> Unfortunately, we have trained customers since the first Spartan >> device, that Spartan of the next node, could be used to replace a >> Virtex of the previous node... >> >> While that may have sometimes been true, S6 WAS NOT designed to >> cannibalize V5 sockets, and is designed to meet better price, and >> power points than Spartan 3, 3A, 3E. >> >> So, yes, the software will work very very hard to meet an unrealistic >> expectation of timing. And it might fail in the larger S6 parts to >> meet said unrealistic goals. >> >> That said, the software has actually improved with every release (in >> my opinion, as an actual user). >> >> Does the software have to improve further: yes, it does. You can >> always do a better job with software. >> >> But, I would always choose the latest software, and the latest >> hardware for any new project: all the attention is on it, the price >> curve will be the steepest (price will fall faster), and it will have >> the best support. >> >> Come on folks, this used to be a real forum, with useful information. >> >> Lately, this is like an old folks home, with everyone complaining >> about their ailments.... >> >> Did Xilinx, by creating their own user forums, completely kill c.a.f? >> If it goes on like this much longer, I will delete my link to it .... >> no one even bothers to email google to get rid of the spam here! (As a >> test, I emailed google, and they removed the spam I noted in the email >> to them -- the "report spam" button does nothing) >> >> Austin > >Right on, Austin ! >Spartan is for low cost and low power, do not complain about the >performance Ain't I allowed to complain about the hard-core DRAM interface? We're trying to get it to work at 128 MHz, the very bottom of its specified speed range. JohnArticle: 146435
I received my new Nexys2 board today and fired it up. I already had a Basys and Nexys board so I wanted to see what this one had to offer. It is nice. Its larger so that the leds actually line up with the switches and you have room to actually plug in a canned oscillator. You may not need it because they upgraded the original resonator to a real oscillator. My basys board had unstable video with the resonator and needed a can. The Nexsys2 is ok. They doubled the number of external connections off the board and added a ps2, uart and vga interface. I took a basys design that I had and edited the padring,ucf and a couple of config files and it compiled and ran ok. It's nice having all those gates. John --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146436
austin wrote: > That said, the software has actually improved with every release (in > my opinion, as an actual user). The problem is that the competition (A) has moved faster. For example the timing engine of ISE is starting to show its age. There is no SDC support, which is much more flexible format than the UCF (and supported by many tools in the flow). Look into A timequest how the tool should work in terms of results analysis etc. (graphical representation of faults, slack histograms etc.) Also the major releases have been really broken sometimes, so every release is not improving the situation, on the contarary. ISE is not the best part of Xilinx offering. --KimArticle: 146437
On Mar 3, 12:22=A0am, Symon <symon_bre...@hotmail.com> wrote: > This lot seems to be revealing a bit more about their stuff. > and still more info http://www.eeproductcenter.com/pld-fpga/brief/showArticle.jhtml;jsessionid= =3DBPWGVULEVILDOQSNDLSCKHA?articleID=3D223800194 [" the chips will sample in third quarter and go into mass production in Q4 2010. "] ["A1EC02, A1EC03, A1EC04, and the A1EC06 with between 220,000 and 630,000 look-up tables per device. All four parts have 5.5-Mbytes of RAM, 920 parallel I/Os and 44 PLLs, Tabula said The A1EC06 has 1,280 multiplier-accumulator blocks. Designed for a range of applications, ABAX devices will initially target the telecom, enterprise, and wireless infrastructure markets and all the initial devices in the family include 48 serial transceivers operating at between 55-Mbit/s and 6.5-Gbit/s. "] A1EC04 is $150 per unit for orders of 2,000 units That's a lot of engineering... -jgArticle: 146438
"Aditi" <aditimis@gmail.com> wrote in message news:601b9265-dfee-4a09-a5de-f51c9cff80ae@v20g2000yqv.googlegroups.com... > Hi all, > I am working on a new design and have chosen the Spartan 6 family FPGA > for it. I was looking to see if there is a an on-chip PROM on any of > the Spartan 6 FPGAs. I could not find about it in the datasheet. But > if there is something that I am missing or if there is any other > series of FPGAs with on-chip PROM, do let me know. Are you looking for a 'program once and it will always be there' memory or just something that has defined contents after configuration? If the latter then define a ROM and there are ways of setting the content during configuration. I'm mostly Altera these days so am a but rusty on Xilinx ram configuration but it's simple enough. Someone who knows the details should be along shortly.... Nial.Article: 146439
On Mar 18, 12:10=A0pm, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > "Aditi" <aditi...@gmail.com> wrote in message > > news:601b9265-dfee-4a09-a5de-f51c9cff80ae@v20g2000yqv.googlegroups.com... > > > Hi all, > > I am working on a new design and have chosen the Spartan 6 family FPGA > > for it. I was looking to see if there is a an on-chip PROM on any of > > the Spartan 6 FPGAs. I could not find about it in the datasheet. But > > if there is something that I am missing or if there is any other > > series of FPGAs with on-chip PROM, do let me know. > > Are you looking for a 'program once and it will always be there' memory o= r > just something that has defined contents after configuration? > > If the latter then define a ROM and there are ways of setting the content > during configuration. > > I'm mostly Altera these days so am a but rusty on Xilinx ram configuratio= n > but it's simple enough. > > Someone who knows the details should be along shortly.... > > Nial. I think the OP wishes to see XC6SN (as non volatile) what isnt gonna happen, not soon at least AnttiArticle: 146440
Hello Andy, Thanks for your clues. :) Sorry for late appreciation,I have exams this week. anyway,i will try my best! Thanks, Summer --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146441
> >Anyone had any experiences with the GN4124? Or alternatively, with the >PEX8311 by PLX, which is the only other chip I've managed to find that >performs a similair task? The ultimate project goal is going to be a >PCIe card with an FPGA talking to a mini-ITX running Linux, and I'm >likely going to be the one doing the coding on all ends. Total project >run's only likely about 200, 250 pieces, so it's easier to spend BOM >money than it is to buy expensive IP or spend weeks and weeks of extra >coding. > >-- >Rob Gaddi, Highland Technology >Email address is currently out of order > I'm currently looking for a way around the PLX PEX8311 device's limitations so I wouldn't recommend using it. The PEX8311 is really a two die chip with a PEX81111 and a PCI9056. The PEX8111 does not support MSI interrupts (which I've been requested to add to our product) and none of PLX's PCI devices support MSI. Before you use the PEX8311 download the errata sheets on the 8311, the 8111, and the 9056; they all apply to the 8311. I've used the PCI9080, PCI9656, PCI9054, and PEX8311 on various boards. So long as an errata doesn't get in your way they're not bad chips. I'm looking at either trying to create my own PCI to local bus interface with an FPGA or using something like the GN4124 or the AAE-B04 (looks like it's made by Daitron). --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146442
Hi, I'm working with the xilinx xapp1052 Bus Master DMA model. The data received through DMA on the PCI-Express link is written to the fpga Block RAM. I have added my design to this, which reads data from this block ram and processes it. A Read DMA transfer is configured with a TLP size & TLP count and then the endpoint design waits to receive data from the host application. Now my problem is that everything works fine in simulation. But in actual hardware, the host application does not always send data in the configuration set. For example I set the DMA configuration to be TLP's with 23 double word payloads each, but what I receive at the endpoint is TLP's with data payloads of 16 double words. This disturbs the rest of the design which is expecting to receive data in a specific format.Is that normal? JkArticle: 146443
Hi Jk, if I understand you correctly you are performing a memory read from system memory? In this case what you are observing is perfectly normal. It is called the read completion boundary (RCB). The completer (here the root complex) can respond with multiple completions to a single request. The spec says a root complex may implement an RCB of 64 Byte (16 DW) or 128 Byte (32 DW). All other components (bridge, switch, endpoint) may only implement an RCB of 128. System software should set bit 3 in the Link Control register to indicate which RCB option your root complex implements. I hope Xilinx makes this status signal available to your hardware / state machines. I know Lattice does. You have two options: 1) Never issue a request which crosses an RCB boundary (16DW or 32DW). This way you will always get a single completion. You may well loose some bandwidth though. 2) Change your hardware to handle multiple completions. You are guaranteed these arrive in order of increasing address. Regards, Charles Jk schrieb: > Hi, > > I'm working with the xilinx xapp1052 Bus Master DMA model. The data > received through DMA on the PCI-Express link is written to the fpga > Block RAM. I have added my design to this, which reads data from this > block ram and processes it. > A Read DMA transfer is configured with a TLP size & TLP count and then > the endpoint design waits to receive data from the host application. > Now my problem is that everything works fine in simulation. But in > actual hardware, the host application does not always send data in the > configuration set. For example I set the DMA configuration to be TLP's > with 23 double word payloads each, but what I receive at the endpoint > is TLP's with data payloads of 16 double words. This disturbs the rest > of the design which is expecting to receive data in a specific > format.Is that normal? > > JkArticle: 146444
Hi all, seems that Xilinx has decided to have only one distributor... and NuHorizons seems out of business. Does anybody know the reason behind? I believed was a good idea to have have the opportunity to buy from 2 distributors.Article: 146445
On 16 Mar, 02:42, Te=F3filo Monteiro <te0of...@gmail.com> wrote: > Hi, > > I need an information. I need to have an FPGA Board and recive from a > adc working =A0between 20MHz and 100MHz, but i don't have any idea who > to do it because i don't know any site that sells this things > together! > > Thanks for the attention I have designed a board with 2x adc 200MSPS 8 bit. is that of any interest?Article: 146446
On Mar 18, 4:03=A0pm, Francesco <francescopoder...@googlemail.com> wrote: > Hi all, > seems that Xilinx has decided to have only one distributor... and > NuHorizons seems out of business. Does anybody know the reason behind? > I believed was a good idea to have have the opportunity to buy from 2 > distributors. nu is not out business yet, just not allowed to sell X products any more... funny, i just ordered last s3a stock from nu, well they only had 5 pcs of that device, but did feel good, to BUY all their stock for some item, but i am very disappointed about Nuh, they said shipping 75$ but then on bill it was 123$ and it takes about 10 days to arrive!! They did ship same day, but the UPS just takes forever... AnttiArticle: 146447
Andy "ever possible"? Yes. That's one reason why I prefer async resets for device initialization (but not for simply setting a counter back to zero during its normal course of operation, etc.) AndyArticle: 146448
On Mon, 15 Mar 2010 12:54:55 -0700 (PDT), Antti <antti.lukats@googlemail.com> wrote: |On Mar 15, 9:42 pm, james <bu...@bud.u> wrote: |> On Sun, 14 Mar 2010 22:00:45 -0700 (PDT), Antti |> |> <antti.luk...@googlemail.com> wrote: |> |> |On Mar 15, 5:30 am, james <bu...@bud.u> wrote: |> |> On Sun, 14 Mar 2010 07:37:17 -0700 (PDT), Antti |> |>|> <antti.luk...@googlemail.com> wrote: |> |> |> |> |> |On Mar 14, 4:14 pm, Sharath Raju <brshar...@gmail.com> wrote: |> |> |> I am trying to send data from the FPGA to the ethernet transeiver on |> |> |> the Nu Horizons Spartan 3A DSP board. |> |> |> There is an on-board Micrel KSZ8041NL transceiver, and Nu Horizons has |> |> |> provided a wrapper (.bit file) to talk to the transceiver. I have |> |> |> downloaded it to the board, but don't know how to use the wrapper as |> |> |> there is not much documentation, besides just the bit file. |> |> |> |> |> |> Can anyone help ? |> |> | |> |> |.bit as wrapper? |> |> |you are mistaken |> |> | |> |> |.bit files are pre made demos only so you can only use to try out the |> |> |factory demo |> |> |you cant use it own designs at all |> |> | |> |> |and as Nu horizons is no longer an Xilinx disti, i bet you get nil |> |> |xilinx support from nu |> |> | |> |> |antti |> |> | |> |> | |> |> | |> |> |++++++++++ |> |> |> |> 32% of annual sales gone! Man is that a shocker for Nu Horizons. |> |> |> |> So I wonder what the "new" direction is for Xilinx? |> |> |> |> james |> | |> |single disti |> | |> |Antti |> |> That either means themselves or Avnet who is currently their only |> distributor left. I wonder if that also means that Digikey is out |> also? |> |> james | |you see many spartan-6 devices at digikey ?? | |digikey is not disti, its place to get some stuff sometimes |i dont | |Antti I asked only because I am a hobby user. I don't order tens of thousands of devices. My buying habit is less than five at a time. And yes I do buy from either Nu Horizons or Digikey depending who has stock at the time. Digikey has two Spartan 6 variants listed in their catalog now. Right now none in stock. Currently I still use the Spartan 3E for my designs. jamesArticle: 146449
To John: Do you have a webcase filed? Whay is the number (I can look it up). To Kim: "Faster" is subjective: some say they are ahead in some areas, and some claim we are ahead in others. For example, Altera recently announced....(dramatic pause)...RECONFIGURABILITY!!! OH MY!! WOW!!! They have no tools that compare with planAhead(tm). They have no design platforms (pre-canned suites of IP, pcb's, and the support tools), and so on. The have virtually no signal integrity support (although they provide a list of consultants to hire to solve all the signal integrity issues that arise). Basically, we are in business, and have been in business. We are successful, growing all of our markets. And, big surprise, so is Altera! We each have room for improvement, and we each have strengths. Take your pick. It reminds me of the Intel/Motorola wars of the 80's: each had a 8 bit, and 16 bit microprocessor. Each had support, tools, boards, and so forth. Some were in love with Intel, and their "superior" complex instruction set. Others were delirious over the "orthogonal and elegant" Motorola architectures (6800 and 68000). Personally, I had to buy the cheapest solution (damn the tools, and all the rest). They both worked just fine. to jg: Oh, and lastly, yes, the smallest S6 is H U G E ! compared with Spartan 3 family...in effect I do not think there is a "low end" in the Spartan 6 family! The die would be so small as to not be build- able (all IO ring, nothing in the center). There is this "low end, low cost" market that everyone is agonizing over: how big is it? What do they need? What do they want? How low must the price be to sell, compete, and still be able to make a reasonable margin? Is it better to serve larger markets? I do not know the answers. Good thing we plan to offer the 3A ( 3AN) family for as long as folks keep ordering it, Austin
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