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On May 21, 7:57=A0am, "honio" <claudio@n_o_s_p_a_m.n_o_s_p_a_m.eech.org> wrote: > >Do you expect to get any empty status output without a read clock? > > >Jan > > Yes i wanted to have the empty flag assigned when i first write to the > fifo. > > The readclock is much slower than the writeclock! But i use the empty > signal on with the writeclock rate. > > Think i have to change fifo to a common clock. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com You need a read clock edge to change the Empty flag. You might use a faster read clock and control the read operation with read enable. Here is a deeper explanation: Empty is really only important for the read operation. The write side "does not care whether the FIFO is empty". The Empty rising edge is naturally caused by a read, but the falling (trailing) edge is obviously caused by a write, and would thus naturally be synchronous with the write clock. When read and write clocks are different and uncorrelated, this would insert an asynchronous falling edge into the read control logic, leading to unreliable operation and metastable problems. To prevent this, the falling edge of Empty is internally re-synchronized to the read clock. And therefore you need a read clock to initiate any change of the externally visible Empty flag. Asynchronous dual-clock FIFO design is tricky, that's why you were well-advised to use a "canned" solution that is proven to be reliable under all conditions. Just use a multiple of the intended read clock frequency, and control the read operation with an enable. Peter Alfke, formerly with Xilinx Applications, now retired.Article: 147751
On 21 May 2010 11:15:11 GMT, Philip Pemberton <usenet10@philpem.me.uk> wrote: >Hi guys, >I could really use some help from an SDRAM / FPGA guru here... > >I've got an SDRAM controller IP core -- specifically, the sdram_wb core >by Stephen Williams, available from the Git repository ><git://icarus.com/~steve-icarus/sdram_wb.git>. This core works fine on >the Altera DE1, with a 16-bit-wide 64Mbit (1M*16*4bank) PowerChip SDRAM, >P/N A2V64S40CTP. The FPGA is a Cyclone II 2C20, and all I had to do to >make the core work was add a PLL to shift the SDRAM clock by 2ns. >Unfortunately (for me), I hit the limits of what the DE1 could do -- I >got the SoC working, but ran out of space for the LCD controller >(framebuffer) and audio controller. So I've started playing with the >Enterpoint Drigmorn2 board, which uses a Xilinx Spartan3A XC3S700A FPGA, >and a 32Mbyte (2M*32*4bank) 32-bit-wide ISSI SDRAM chip, the IS42S32800B. What happens in simulation? Simulating SDRAM should be OK - use the simulation model for the nearest equivalent chip from Micron if you can't get one from ISSI. Simulating DDR devices gets messy because the vendors don't supply VHDL models, so you need a mixed-language capable sim, unless you're using Verilog. If it's as simple as clock phase timing you may get away with experiments on the hardware, using the DCM variable phase shift, but I would recommend simulation first. - BrianArticle: 147752
On Fri, 21 May 2010 19:48:42 +0100, Brian Drummond wrote: > What happens in simulation? I don't have a full simulation model of the CPU, SDRAM controller and so on. There is a testbench included with sdram_wb, but it uses a completely different chip (Micron MT48LC2M32B2, 512K*32*4banks) and I haven't managed to find a model of the ISSI SDRAM. Good ol' ISSI don't release Verilog models of their chips so I'm having to make do... :-/ The nearest I've found in Micron's portfolio is the MT48LC8M32B2, which matches for bank size but doesn't check the refresh timing. I've run the testbench with that model, and it passed all five test runs (it tests five times with different refresh timings). Do I need to set up any timing constraints in ISE for the SDRAM? If so, what do I need to set up? I've got a UCF that specifies the pin parameters (DRIGMORN2.UCF), but doesn't specify any timing requirements (not even the frequency of the input clock). The Xilinx documentation is as clear as mud on this, and I can't find any good application notes on the subject (but I found tons of DDR/DDR2 SDRAM appnotes)... -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 147753
Does anybody have any XC6V130T-2FFG1156CES's available? Even used on a boad would be acceptable. I don't think the non-ES parts have been released yet...Article: 147754
OK, this is nuts... With ISE Synthesizer set up like this: Optimisation Goal: AREA Optimisation Effort: NORMAL The core works fine (the timing is a little out, but not bad enough to pooch the whole thing). If I set it up like this: Optimisation Goal: SPEED Optimisation Effort: NORMAL Then the whole thing stops working -- it outright fails to read/write the SDRAM. I can access the SDRAM controller's cache (32 bytes of the current page), but accessing an out-of-page address returns garbage. If I do the same thing on Quartus? Well, the timing looks better in SPEED mode, but it still works fine on the DE1. What the *bleep* is going on? -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 147755
On May 21, 12:52=A0pm, Thomas Jones <mr.thomas.c.jo...@gmail.com> wrote: > Does anybody have any XC6V130T-2FFG1156CES's available? =A0Even used on > a board would be acceptable. =A0I don't think the non-ES parts have been > released yet... We have some in the 'ES' grade. They would be stuffed on this product: DN-DualV6-PCIe-4 <http://www.dinigroup.com/DN-DualV6-PCIe-4.php>Article: 147756
On May 21, 10:38=A0am, Gladys <yuhu...@gmail.com> wrote: > Hi, I have a Spartan 3E FPGA starter board of 100K gates. I just want > to do some basic image processing such as dead pixel correction(I just > use black&white images), there is only 8 bits color output and only a > Flash ROM embedded. I want to read RAW format file in which includ the > pixel information, after simple processing, display it on VGA monitor. > My question are: > 1 Would my FPGA board suffice for this purpose? > 2 If yes, with out extra RAM, how can I get image file into my FPGA? > Your help would be really appreciate! I don't think it is impossible but you might have to change the criteria. Instead of reading a file use a video image. Working with a image file would require at least one image buffer but with a video signal you do just in time processing to the image. Work with an image of specified resolution and make it something easily displayable on a VGA monitor. Another approach, take a look at the XESS (www.xess.com). They have a some low cost developer boards with Xilinx devices and the boards contain external memory. If you look at the example files area they already have a project that reads in an image and displays it. So, what is left is for you write your pixel processing algorithms and integrate them into the workflow for displaying the image.Article: 147757
The constraints you should have in the ucf are the input clock fequency, the pin constraints and the IO types you are using for those pins. If the design passes simulation and meets timing once you have run P&R then you should be ok. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147758
Philip Pemberton <usenet10@philpem.me.uk> wrote: >OK, this is nuts... > >With ISE Synthesizer set up like this: > Optimisation Goal: AREA > Optimisation Effort: NORMAL > >The core works fine (the timing is a little out, but not bad enough to >pooch the whole thing). If I set it up like this: > Optimisation Goal: SPEED > Optimisation Effort: NORMAL > >Then the whole thing stops working -- it outright fails to read/write the >SDRAM. I can access the SDRAM controller's cache (32 bytes of the current >page), but accessing an out-of-page address returns garbage. > >If I do the same thing on Quartus? Well, the timing looks better in SPEED >mode, but it still works fine on the DE1. > >What the *bleep* is going on? You probably have unconstrained paths which meet timing or not depending on the routing mode. It is crucial that all paths in an FPGA have timing constraints (including paths from the inputs to the flipflops and flipflops to the outputs). -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 147759
On 18 Maj, 13:51, "Eagle_mk4" <eagle_mk4@n_o_s_p_a_m.hotmail.com> wrote: > Hi, I=B4m using MIG v3.0 to generate the VHDL code for a DDR SDRAM > controller. I implement the design but I don=B4t know which is the > format(values) the inputs signal, as for example app_af_addr, app_mask_da= ta > and app_wdf_data. And where do I declare the signals? > > Thanks a lot in advance. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I'd like to help you but you need to be more precies. lutexArticle: 147760
Call me a sadist, but I tend to cruise through the license agreements and EULAs before installing software to make sure I'm not being victimized by using someone's application. I wanted to bring my S3E starter kit back up to prototype Xilinx-based algorithms while employed by a particularly Altera-friendly group. Loading ISE 12.1, I not only find lawyer-speak that's longer than Facebook privacy policy but see that: "Webtalk" is a required component to run Webpack. A quote from the second page of legalese: "Please note that WebTalk will collect and transmit certain data that may contain (or be correlated to reveal, primarily via the Authorization Codes data) personally identifiable information. By agreeing to this Agreement, you hereby give your consent (on behalf of Licensee and Users) for Xilinx to use and disclose this information anywhere in the world for the purposes and as described in this Agreement." Crud. Anyone know of the last Webpack I could get that doesn't transmit things like my constraints, devices, and authorization codes back to Xilinx? I just want to prototype some stuff and do NOT like my computer to leak information out into the world beyond my control. At the moment my form of control is to not install ISE. To not use Xilinx. Hey - at least it's not like Cadence who says that anything I send them - designs, etc - effectively becomes public domain. But it leaves a seriously bad taste in my mouth. - John_HArticle: 147761
On May 22, 7:50=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > Anyone know of the last Webpack I could get that doesn't transmit > things like my constraints, devices, and authorization codes back to > Xilinx? After some searching and poking around, it appears ISE 12.1 is the first to force Webtalk onto Webpack users. I finally found where to get Webpack 11.5 which - according to Xilinx info - allows Webtalk to be disabled on install. I'll see if I hit any "gotchas" along the way.Article: 147762
On May 21, 6:19=A0pm, Philip Pemberton <usene...@philpem.me.uk> wrote: > OK, this is nuts... > > With ISE Synthesizer set up like this: > =A0 Optimisation Goal: =A0 AREA > =A0 Optimisation Effort: NORMAL > > The core works fine (the timing is a little out, but not bad enough to > pooch the whole thing). If I set it up like this: > =A0 Optimisation Goal: =A0 SPEED > =A0 Optimisation Effort: NORMAL > > Then the whole thing stops working -- it outright fails to read/write the > SDRAM. I can access the SDRAM controller's cache (32 bytes of the current > page), but accessing an out-of-page address returns garbage. > > If I do the same thing on Quartus? Well, the timing looks better in SPEED > mode, but it still works fine on the DE1. > > What the *bleep* is going on? > > -- > Phil. > usene...@philpem.me.ukhttp://www.philpem.me.uk/ > If mail bounces, replace "10" with the last two digits of the current yea= r As others have mentioned, you probably have some unconstrained paths causing timing violations. If you think you have enough constraints, but still have this problem, try setting up the post place&route static timing report for Verbose and enter a good size number like 100 in the option "report unconstrained paths". Then if you find an unconstrained path that probably should be constrained you will know what to add to your constraints. As for SPEED vs. AREA, in Xilinx FPGA's you very often get the best overall timing results using AREA optimization rather than speed. This is probably because the route portion of your total path delay is large. This shows up in larger designs and larger parts especially since the worst case routing delays grow with the design size. Regards, GaborArticle: 147763
On May 18, 7:51=A0am, "Eagle_mk4" <eagle_mk4@n_o_s_p_a_m.hotmail.com> wrote: > Hi, I=B4m using MIG v3.0 to generate the VHDL code for a DDR SDRAM > controller. I implement the design but I don=B4t know which is the > format(values) the inputs signal, as for example app_af_addr, app_mask_da= ta > and app_wdf_data. And where do I declare the signals? > > Thanks a lot in advance. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com In your MIG-generated directory structure should be a copy of the user guide that explains the use of these signals. For earlier versions of MIG this was ug086.pdf. As I recall it is not very clear about certain things like which address bits convert to row column and bank, but it has a few timing diagrams that help you understand the basics of the interface. for add_af_addr the lowest address bits map to the column address, the next bits up are the row address and the most significant bits are bank. If it hasn't changed since MIG 2.3, the address has a fixed width of 31 bits, so you need to add up your column/row/bank sizes to see how many of these 31 bits are really used. app_wdf_data is the write data input and is twice the width of the external DDR interface so it runs at the main clock rate rather than twice the rate. To determine how many words of data you need to provide with each write command, divide the burst length by two. Also remember to start a burst on a burst boundary. For example for a burst length of 4 you would provide two words of data and the low two bits of add_af_addr would be 00. app_mask_data is ignored if you don't generate the core with byte masking enabled. If you need to use it, each bit of the mask corresponds to one byte of app_wdf_data. A one bit in the mask "masks out" the associated byte. If you want to write all bytes it should be zero. Take a look at the interface description in the user guide to see the sequence for pushing commands and data into the core. HTH, GaborArticle: 147764
I bought a few of these on ebay but I cant find Xilinx Xact software needed to design with these FPGAs Can someone point me in the right direction? Anyone have a copy I can buy? sincerely hungry studentArticle: 147765
Gabor <gabor@alacron.com> wrote: >On May 21, 6:19=A0pm, Philip Pemberton <usene...@philpem.me.uk> wrote: >> OK, this is nuts... >> >> With ISE Synthesizer set up like this: >> =A0 Optimisation Goal: =A0 AREA >> =A0 Optimisation Effort: NORMAL >> >> The core works fine (the timing is a little out, but not bad enough to >> pooch the whole thing). If I set it up like this: >> =A0 Optimisation Goal: =A0 SPEED >> =A0 Optimisation Effort: NORMAL >> >> Then the whole thing stops working -- it outright fails to read/write the >> SDRAM. I can access the SDRAM controller's cache (32 bytes of the current >> page), but accessing an out-of-page address returns garbage. >> >> If I do the same thing on Quartus? Well, the timing looks better in SPEED >> mode, but it still works fine on the DE1. >> >> What the *bleep* is going on? >> >> -- >As for SPEED vs. AREA, in Xilinx FPGA's you very often >get the best overall timing results using AREA optimization >rather than speed. This is probably because the route >portion of your total path delay is large. This shows up >in larger designs and larger parts especially since the >worst case routing delays grow with the design size. Actually this is a bit of black art. I also get good results by adjusting the 'pack factor' (IIRC) which puts related logic closer together. IMHO it takes some trial and error to find the optimum place & route settings for a design which gets close to the limits of the FPGA regarding speed and/or size. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 147766
On Sat, 22 May 2010 20:11:25 -0700, Gabor wrote: > As others have mentioned, you probably have some unconstrained paths > causing timing violations. [...] OK, I've just set up these constraints: #Created by Constraints Editor (xc3s700a-ft256-4) - 2010/05/21 NET "CLOCK" TNM_NET = CLOCK; TIMESPEC TS_CLOCK = PERIOD "CLOCK" 25 MHz HIGH 50%; #Created by Constraints Editor (xc3s700a-ft256-4) - 2010/05/23 INST "SDRAM_A<0>" TNM = sdram_outs; INST "SDRAM_A<1>" TNM = sdram_outs; INST "SDRAM_A<2>" TNM = sdram_outs; INST "SDRAM_A<3>" TNM = sdram_outs; INST "SDRAM_A<4>" TNM = sdram_outs; INST "SDRAM_A<5>" TNM = sdram_outs; INST "SDRAM_A<6>" TNM = sdram_outs; INST "SDRAM_A<7>" TNM = sdram_outs; INST "SDRAM_A<8>" TNM = sdram_outs; INST "SDRAM_A<9>" TNM = sdram_outs; INST "SDRAM_A<10>" TNM = sdram_outs; INST "SDRAM_A<11>" TNM = sdram_outs; INST "SDRAM_BA<0>" TNM = sdram_outs; INST "SDRAM_BA<1>" TNM = sdram_outs; INST "SDRAM_CAS_N" TNM = sdram_outs; INST "SDRAM_CKE" TNM = sdram_outs; INST "SDRAM_CLK" TNM = sdram_outs; INST "SDRAM_CS_N" TNM = sdram_outs; INST "SDRAM_DQ<0>" TNM = sdram_outs; INST "SDRAM_DQ<1>" TNM = sdram_outs; INST "SDRAM_DQ<2>" TNM = sdram_outs; INST "SDRAM_DQ<3>" TNM = sdram_outs; INST "SDRAM_DQ<4>" TNM = sdram_outs; INST "SDRAM_DQ<5>" TNM = sdram_outs; INST "SDRAM_DQ<6>" TNM = sdram_outs; INST "SDRAM_DQ<7>" TNM = sdram_outs; INST "SDRAM_DQ<8>" TNM = sdram_outs; INST "SDRAM_DQ<9>" TNM = sdram_outs; INST "SDRAM_DQ<10>" TNM = sdram_outs; INST "SDRAM_DQ<11>" TNM = sdram_outs; INST "SDRAM_DQ<12>" TNM = sdram_outs; INST "SDRAM_DQ<13>" TNM = sdram_outs; INST "SDRAM_DQ<14>" TNM = sdram_outs; INST "SDRAM_DQ<15>" TNM = sdram_outs; INST "SDRAM_DQ<16>" TNM = sdram_outs; INST "SDRAM_DQ<17>" TNM = sdram_outs; INST "SDRAM_DQ<18>" TNM = sdram_outs; INST "SDRAM_DQ<19>" TNM = sdram_outs; INST "SDRAM_DQ<20>" TNM = sdram_outs; INST "SDRAM_DQ<21>" TNM = sdram_outs; INST "SDRAM_DQ<22>" TNM = sdram_outs; INST "SDRAM_DQ<23>" TNM = sdram_outs; INST "SDRAM_DQ<24>" TNM = sdram_outs; INST "SDRAM_DQ<25>" TNM = sdram_outs; INST "SDRAM_DQ<26>" TNM = sdram_outs; INST "SDRAM_DQ<27>" TNM = sdram_outs; INST "SDRAM_DQ<28>" TNM = sdram_outs; INST "SDRAM_DQ<29>" TNM = sdram_outs; INST "SDRAM_DQ<30>" TNM = sdram_outs; INST "SDRAM_DQ<31>" TNM = sdram_outs; INST "SDRAM_DQM<0>" TNM = sdram_outs; INST "SDRAM_DQM<1>" TNM = sdram_outs; INST "SDRAM_DQM<2>" TNM = sdram_outs; INST "SDRAM_DQM<3>" TNM = sdram_outs; INST "SDRAM_RAS_N" TNM = sdram_outs; INST "SDRAM_WE_N" TNM = sdram_outs; #Created by Constraints Editor (xc3s700a-ft256-4) - 2010/05/23 TIMEGRP "sdram_outs" OFFSET = OUT 10 ns AFTER "CLOCK"; TIMEGRP "sdram_outs" OFFSET = IN 10 ns VALID 10 ns BEFORE "CLOCK"; Now I can build the core with OPTIMIZE=area or OPTIMIZE=speed, and it works fine. Question: do these timing constraints look sane? I figured since I'm using a 270-degree shifted version of a DCM'd version of the input clock, the timing settings should be around a quarter of Tclk_period (Clk period is 40ns for 25MHz, so that would be 10ns). CLOCK is the 25MHz crystal input, MCLK is the output from the first DCM (a *25, /25 "multiplier" that effectively acts as a buffer and duty cycle corrector). SDRAM_CLK is an output from the FPGA to the SDRAM, which is sourced from the CLK270 output of the second DCM. Thanks, -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 147767
On 23 May 2010 09:14:47 GMT, Philip Pemberton <usenet10@philpem.me.uk> wrote: >On Sat, 22 May 2010 20:11:25 -0700, Gabor wrote: > >> As others have mentioned, you probably have some unconstrained paths >> causing timing violations. [...] > >OK, I've just set up these constraints: >#Created by Constraints Editor (xc3s700a-ft256-4) - 2010/05/23 >TIMEGRP "sdram_outs" OFFSET = OUT 10 ns AFTER "CLOCK"; >TIMEGRP "sdram_outs" OFFSET = IN 10 ns VALID 10 ns BEFORE "CLOCK"; > >Now I can build the core with OPTIMIZE=area or OPTIMIZE=speed, and it >works fine. > >Question: do these timing constraints look sane? I figured since I'm >using a 270-degree shifted version of a DCM'd version of the input clock, >the timing settings should be around a quarter of Tclk_period (Clk period >is 40ns for 25MHz, so that would be 10ns). Given such a slow clock they look OK. But seeing that has prompted some memories (it's a few years since I set up constraints for SDR SDRAM). The key to getting good I/O timing is to ensure the tools place the I/O registers in the right place - the IOBs rather than the core logic. Then there is no routing involved, and the constraints really only act as a sanity check. (at 200MHz they may alert you to the wrong output standard) If some of your registers were in the IOBs and others weren't, the latter are subject to additional routes of random lengths, and here the constraints WILL help, by forcing PAR to keep these routes down. (and 10ns should be easily achievable). Look at the I/O report near the end of the Map Report (.mrp) file. For each I/O pin you will see a lot of information including the I/O standard, and the registers in the IOB for that pin. For an output pin (e.g. address) I want to see OFF or OUTFF in that list. For an I/O pin (data) I want to see IFF/INFF, OFF/OUTFF and ENBFF which tristates the pin. (Signal names seem to have changed with tool versions) Getting what you want can take some fiddling. For example, you may need to duplicate registers in your code; one to feed the pins and another to use the signal internally. Then you need to convince the synthesis tool to leave them alone; apply the "equivalent-register-removal = no" attribute to the appropriate regs. And check the .MRP file. Loop until done. A few tool versions ago, you also needed to replicate the tristate signal for each ENBFF, and ensure it was the right polarity (active low) but this may have been improved. Downside to all this is that while you have REALLY GOOD external timings, you have lengthened the internal routes by a few ns. So I keep heavy processing hidden behind a second register where that is likely to be a problem. At 25MHz, feel free to ignore all the above, but it may help to see some of what's going on beneath the hood. - BrianArticle: 147768
On Sat, 22 May 2010 18:51:57 -0700 (PDT), John_H <newsgroup@johnhandwork.com> wrote: >On May 22, 7:50 pm, John_H <newsgr...@johnhandwork.com> wrote: >> >> Anyone know of the last Webpack I could get that doesn't transmit >> things like my constraints, devices, and authorization codes back to >> Xilinx? > >After some searching and poking around, it appears ISE 12.1 is the >first to force Webtalk onto Webpack users. I finally found where to >get Webpack 11.5 which - according to Xilinx info - allows Webtalk to >be disabled on install. > >I'll see if I hit any "gotchas" along the way. I wonder what that means for running 12.1 on a machine without network access... - Brian (posting from the stone age)Article: 147769
On May 23, 6:14=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > > >I'll see if I hit any "gotchas" along the way. > > I wonder what that means for running 12.1 on a machine without network > access... > > - Brian (posting from the stone age) The Webtalk FAQ suggests that the html file with all the info will simply be saved for the next time a connection is present. Having a machine disconnected from the internet won't keep the designer from using the product. As far as "gotchas" it seems 11.1 won't even install on my 64-bit Vista machine.Article: 147770
On Sun, 23 May 2010 04:53:50 -0700 (PDT), John_H <newsgroup@johnhandwork.com> wrote: >On May 23, 6:14 am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> >> >I'll see if I hit any "gotchas" along the way. >> >> I wonder what that means for running 12.1 on a machine without network >> access... >> >> - Brian (posting from the stone age) > >The Webtalk FAQ suggests that the html file with all the info will >simply be saved for the next time a connection is present. Having a >machine disconnected from the internet won't keep the designer from >using the product. > >As far as "gotchas" it seems 11.1 won't even install on my 64-bit >Vista machine. 10.1 (and 11.1?) Webpack were only supposed to install on 32-bit machines. However, I tried it on OpenSuse 11 64-bit because the Suse Installer claimed it could install 32-bit compatibility libs. I only needed to comment out the "exit" in the 32-bit test in the setup script, and it installed and worked fine. Problems with 64-bit Vista may be a bit more deep seated though. Vista sounded like one big "gotcha" for a lot of people. - Brian (for stone age, read Win2000sp4)Article: 147771
John_H <newsgroup@johnhandwork.com> wrote: > Call me a sadist, but I tend to cruise through the license agreements > and EULAs before installing software to make sure I'm not being > victimized by using someone's application. I wanted to bring my S3E > starter kit back up to prototype Xilinx-based algorithms while > employed by a particularly Altera-friendly group. Loading ISE 12.1, I > not only find lawyer-speak that's longer than Facebook privacy policy > but see that: > "Webtalk" is a required component to run Webpack. > A quote from the second page of legalese: "Please note that WebTalk > will collect and transmit certain data that may contain (or be > correlated to reveal, primarily via the Authorization Codes data) > personally identifiable information. By agreeing to this Agreement, > you hereby give your consent (on behalf of Licensee and Users) for > Xilinx to use and disclose this information anywhere in the world for > the purposes and as described in this Agreement." > Crud. > Anyone know of the last Webpack I could get that doesn't transmit > things like my constraints, devices, and authorization codes back to > Xilinx? I just want to prototype some stuff and do NOT like my > computer to leak information out into the world beyond my control. At > the moment my form of control is to not install ISE. To not use > Xilinx. > Hey - at least it's not like Cadence who says that anything I send > them - designs, etc - effectively becomes public domain. But it > leaves a seriously bad taste in my mouth. http://lekernel.net/blog/?p=1023 -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 147772
On Sun, 23 May 2010 11:07:37 +0100, Brian Drummond wrote: > Given such a slow clock they look OK. Always good to know :) I'm toying with the idea of running the SDRAM controller faster than the CPU core (the limiter is the CPU -- it manages about 60MHz on a Cyclone2 IIRC; Xst reckons about 47MHz for the entire SoC on a Spartan3A XC3S700A-4C). > But seeing that has prompted some memories (it's a few years since I set > up constraints for SDR SDRAM). Yeah, it seems a lot of folk have moved onto DDR or DDR2. SDR-SDRAM seems to have the edge in ease-of-use, but loses out on raw speed. But that said, neither of them can match an SRAM clock-for-clock because of the refresh, precharge and select cycles, and the access latency. Although the caching in the sdram_wb core makes that a bit of a moot point, especially for sequential WISHBONE accesses. > Look at the I/O report near the end of the Map Report (.mrp) file. For > each I/O pin you will see a lot of information including the I/O > standard, and the registers in the IOB for that pin. For an output pin > (e.g. address) I want to see OFF or OUTFF in that list. For an I/O pin > (data) I want to see IFF/INFF, OFF/OUTFF and ENBFF which tristates the > pin. (Signal names seem to have changed with tool versions) Oh, that explains a lot! The "broken" version shows blanks under "Reg(s)" for all the SDRAM pins. The "working" version shows a mix of "OFF1", "IFF1" and blank (only SDRAM_CLK and SDRAM_CKE are blank, which is fair enough -- CLK comes from the DCM, CKE is grounded). Thanks, I'd looked at the Map report, but previously didn't really know what I was looking for, which explains why I didn't pick up on the FFs not being pushed into the IOBs... It seems I set "Pack I/O Registers into IOBs" to "Yes" on the working version (which causes A LOT of warnings), while it's set to "Auto" in the "broken" version. Can I force FFs in the IOBs in the UCF constraints, or do I need to do that with a "// synthesis IOB=FORCE" constraint in the Verilog source? > At 25MHz, feel free to ignore all the above, but it may help to see some > of what's going on beneath the hood. Well, I'm trying it out at 25MHz because I figure the lower my master clock is, the easier it's going to be to make the thing work. Then once it's working, I can look into making it work on a faster clock. Ideally I'd like to get it going at 50MHz or so -- a lot of processing is going to happen in the FPGA (using hardware implementations of the algorithms I'm using) but the CPU (a hacked up version of the LatticeMico32) will be doing a lot of the integer work, framebuffer updating, and so on. Plan #2 is to rig up an LCD controller that can act as a WISHBONE master, then wire that up to one of the spare master ports on the CONMAX bus arbiter. Then I can use any area of main RAM as the framebuffer, and do away with the messy business of having a separate framebuffer RAM. If any of you guys want to see this code, let me know and I'll stick it online. It's pretty ropey code, but it might do as an example to show how to make the LM32 work on non-Lattice hardware (and how to make the toolchain behave itself). On a final note: the ISSI datasheet for the RAM chip appears to be outright WRONG. It specifies 4096 refresh cycles per 64ms, but if the refresh rate is that low I get data readback errors. If I use the refresh rate for the Industrial-graded chip (4096 per 32ms), or even 4096 cycles per 50us, then it works fine... Yes, I'm using a "Commercial" grade part, not the "Industrial" part. Unless mine has been mismarked.... -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 147773
... because it certainly seems like they don't. A couple of minutes ago, I made some changes to my project which made the synthesizer fall flat on its face: INTERNAL_ERROR:Xst:cmain.c:3464:1.56: Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. OK, seems like a fair request. This project (or most of it) is probably going open-source at the end of its development cycle, so giving up a chunk of unfinished code really isn't a problem. So I go to the aforementioned URL, and try to register for Webcase access. And I'm met with this: WebCase Access Request Denied Your request for access to WebCase was denied. No explanation, just "access denied". So... do Xilinx really want to fix bugs, or is this a subtle way of saying "we don't care about making our software any better than it already is"? Hmmm. -- Phil. usenet10@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "10" with the last two digits of the current yearArticle: 147774
In the Virtex 4 FPGA, slices within a CLB are interconnected with each other. However, in Virtex 5 and Virtex 6, there is no direct connection between slices of a CLB. Why was this change made? Thanks --------------------------------------- Posted through http://www.FPGARelated.com
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