Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
To those of you who responded, I appreciate your help. I am going to look into the suggestion posted my Alex Beynon ... (Thank you Alex) I guess I didn't make it clear in my original note that we are NOT interested in locking the pins down - As Rick Collins wrote: > But I would assume that for some reason, the interconnection between his Xilinx > chip and the rest of the board is via the pin numbers which need to be redone each > time he lets his chip pick the pins for an optimum route. Yes, we want the FPGA tool (not only Xilinx here) to optimize on each iteration. > I don't know the Mentor system, but I would expect that you can connect > the Xilinx part to the rest of the board without reference to the pin numbers. To my knowledge, you cannot connect them without reference to the pin numbers. > If not, there should be a file somewhere that can be modified > to rewire the board. If you wrote a program to read the pin data from > the Xilinx map? report it could automatically fix the board wiring file. > But then I guess that is the point, has anyone already written such a > program? That is one possible solution, but I haven't seen one yet. ----- And Austin Franklin wrote: > Though there has been advice in the past (bad advice I might add) to not > lock your I/Os, I (and many others) STRONGLY recommend locking the I/O > pins, intelligently that is ;-) I have never heard this before and it would appear to me that the so called "intelligent" pin placement would be little more than a good guess. For our applications this would be too restrictive. You didn't present the argument which supports your "STRONG" recommendation for locking the I/O - but if this makes sense I would be interested in hearing it. ----- Alex Beynon wrote: > Mark, > > There is a utility available from Mentor called SmartCircuitMapper. It is an > AMPLE routine which updates the pin names of an FPGA automatically. I know > for the Altera devices I used it looked at the .acf file to generate a pin > location table from which it could regenerate the pin names. > > When placing the device on a schematic, attach stubs labelled "" to the > symbol and label the on/off page and in/out ports with the signal names. > When you run the script once selecting the device it will update all the pin > names. These'll appear on the schematic and form links to the labelled > ports. The limitation is that pin names on your Xilinx must match those on > your Mentor schematic. > > It works very well and I have put several boards through production > following full simulation, I don't advise you locking any pins - it can make > fitting very difficult, even for Xilinx and its pin lock feature. > > You may be able to find it on the web otherwise give 'em a call. > > Best 'o luck > > Alex > Altera FAE > Ambar Cascom (UK) Thanks again, Mark MazzaArticle: 11301
"Mark Purcell" <map@NOSPAM_transtech-DSP.com> writes:
>Try using the STD_LOGIC_UNSIGNED library, this has '+' function defined for
>std_logic_vectors (Also, you should remove the quotes from the "1" I
>think...)
Actually, the quotes stay. ("1" is can be a STD_LOGIC_VECTOR of
length 1, '1' is just a STD_LOGIC or bit)... The operator will
automatically extend the shorter vector).
Cheers,
Jake
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 11302Does anyone know of a portable way to converting a std_logic_vector to an integer value (such as the v1d2int function in Viewlogic) so that it may be used in a comparison? A little off-topic I know, but I'm trying to evaluate some FPGA synthesis tools with a large VHDL file. Thanks in advance, Mark Purcell Remove NOSPAM_ from email address.Article: 11303
Greetings Please find Verilog FAQ : Version 7 athttp://www.comit.com/~rajesh/verilog/faq/index.htmlThis version introduced following changes. - Thorough change in look and feel of web pages. - Breakup of one single FAQ page into logical three pages. - Reorganization of information in three sections. - "What's New" page is added to indicate version history. - Verilog parser contributed by Coy Toavs added. - Link to Veripool (public domain Verilog resources) added. - Examples of simple Verilog models added in technical section. - Links to various companies providing Verilog models added in Tools and services section. Your suggestions, comments are most welcome. Rajesh Bawankule (rajesh@comit.com) -------------------------------------------------------------------- Posted using Reference.COM http://WWW.Reference.COM FREE Usenet and Mailing list archive, directory and clipping service --------------------------------------------------------------------Article: 11304
Greetings Please find Verilog FAQ : Version 7 athttp://www.comit.com/~rajesh/verilog/faq/index.htmlThis version introduced following changes. - Thorough change in look and feel of web pages. - Breakup of one single FAQ page into logical three pages. - Reorganization of information in three sections. - "What's New" page is added to indicate version history. - Verilog parser contributed by Coy Toavs added. - Link to Veripool (public domain Verilog resources) added. - Examples of simple Verilog models added in technical section. - Links to various companies providing Verilog models added in Tools and services section. Your suggestions, comments are most welcome. Rajesh Bawankule (rajesh@comit.com) -------------------------------------------------------------------- Posted using Reference.COM http://WWW.Reference.COM FREE Usenet and Mailing list archive, directory and clipping service --------------------------------------------------------------------Article: 11305
Hello... (Please excuse my English...) I'm developing high speed analog-to-digital converter board using Rambus DRAM(RDRAM) as data storage device. I'm planning to use fast CPLD or FPGA for RDRAM controller. One problem is that the device used as RDRAM controller must operates on both rising and falling edge of clock signal(dual-edge clocking or bi-phase clocking), because RDRAM operates so. Mach5 devices from Vantis support dual-edge clocking but their maximum operating frequency is 125MHz(I need at least 200MHz). Please help me to find out adequate device for RDRAM control, high speed CPLD or FPGA supporting dual-edge clocking, or ASIC chips already made for RDRAM control, any device will do... Thanks in advance... Be a nice day... - limelite -Article: 11306
Rick: I just got off the phone with the Xilinx rep who sent me the original response. The whole business about the attribute Xilinx_GSR is as follows. When using the Metamor compiler, you have to place the attribute on your reset signal if you DON'T put a STARTUP block in your top level schematic. Putting the STARTUP block in your schematic tells the PAR and MAP tools that you're using a global resource, and the attribute is no longer necessary. As for me, what I was trying to say was that when I power up, some of my flipflops go to 0 and some go to 1. The ones that go to 1 are simply because they drive active-low logic that lives off-chip. I believe that GSR stands for "Global Set/Reset" so those ffs that go to 1 upon reset should still use the global resource. In any event, the Metamor compiler is "going away" and M1.5's preferred synthesis tool will be Synopsys. Which means, quick, make sure all of your code is VHDL'87 compliant. But that's another thread. -andy -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories apeters@noao.edu.NOSPAM Rickman <spamgoeshere4@yahoo.com> wrote in article <35C26EBD.75B0759E@yahoo.com>... > Andy Peters wrote: > > > > All of my code has an async reset for all FFs. Some FFs are > > initialized to 0 and some go to 1, so having the reset code makes > > that happen. > > I'm not clear what you mean by this. Are you saying that in ADDITION to > the GSR, you have an async control to each of the FFs in your design? I > realize that you can control the async condition to be a '0' or a '1'. > My point was that even if you do nothing in your design, the GSR is set > to clear all FFs to a '0' at power on. > > When I wanted to control the power on state of all of the FFs, I found > that you needed some fairly special code which is how I got into all > this in the first place. > > > > I didn't realize that the attribute even existed until I read the app > > note. That's what got me started on all of this: I assumed that the > > GSR was mapping properly, and reading about this attribute made me > > question whether that was happening or not. I just wish the app and > > tech notes were consistent. And regularly updated. > > Yes, consistency is not a strong point of Xilinx. They are a company > with somewhat loose reigns. It would be nice if someone in control TOOK > control of the documentation and made it more concise, clear and put > everything on a topic in ONE PLACE! But then their products move forward > at a pretty good clip. I am sure that it is a full time job (or a lot of > them) trying to keep up with the documentation. > > You might also remember that the fact that it is not real easy keeps the > weinies out! ;-) > > > -- > > Rick Collins > > rickman@XYwriteme.com > > remove the XY to email me. >Article: 11307
JUST SAY NO!!! Don't do it!!!. The demon of async wierdness show his ugly head!!! Just my opinion but async style design while at time doing some neat circuit tricks much more often leads to bad uglyness. Async stuff should only be used when it is absolutly totally completly 100% impossible to get the desired function in a syncronous manner. That being said I have done some async stuff, but garanteed fixed delay in an FPGA no way! The only thing you can hope for is to garantee what signal gets there first. Minimum delays are not something FPGA companies are in a big hurry to spec. So even here you take big risks. Have FUN!!!! Nick Eddie Ng wrote: > Dear All, > I'm using Altera FLEX 10K series FPGA right now and I need to > implement an delay element that would do ideally pure delay or > not-too-bad inertial delay. Much like a series of even-numbered > inverters in series to introduce propagation delay but with accurate > delay time, preferrably "programmable" or "parameterizable". > I'm using it to implement an asynchronous micropipeline structure in > which delay is added on the control signals to match/exceed the delay on > the bundled data lines to meet the bundled contrains. > Thanks for any ideas and help. > > Eddie > -- > =========================== > Eddie Ng > ngeddie@ecf.toronto.edu > > Class 9T8+PEY > Electrical Option, > Engineering Science > University of Toronto > ===========================Article: 11308
Well now, becuase a 4K does not have any 2-NAND structures in it's basic
architecture to count as a gate, we first must define what a gate is in an
FPGA. Marketing departments have made great strides in counting gates. Of
course they change their methods every time they need to one up some other FPGA
in gate count. So while they have a predictable method of counting gates (Count
them in such a way as to insure ours is bigger) it is not a method that is
useful as a standard metric.
So I ask you What do you mean by "gate"?
Have FUN!!!
Nick
satish@my-dejanews.com wrote:
> Hello Sir
> I am having a simple C code
> # include <stdio.h>
> main()
> {
> unsigned char a=9,b=23,c;
>
> c= a+b; } The same can be converted into VHDL by declaring the bit vector
> of size 8 bits to each variable. Now my problem is how to caluclate the
> number of gates it is going to take for execution in Xlinx XC4004EX series.
> Even let it be at any series, I want to have the number of gates required to
> execute the above simple program Let any body help me Thanks in advance
> Please reply to my email address:satish_me@hotmail.com
>
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
Article: 11309
I've recently installed v5.1 after using v5.0 from the starter kit. While
things are working fine, I keep getting the following warning:
47501 Warning: Port name [!XRESET] is an invalid VHDL identifier.
It is renamed to [GXRESET].
I have the global reset turned off and, with 1016 devices, "Y1_AS_RESET"
is also off. I've downloaded the documentation but I've been unable to find
anything on this other than comments about GXRESET and !XRESET. I'm using
ABEL and Synario's schematic editor for these designs. I'm not using VHDL. I
would like to find the cause of the warning and/or turn it off if it's not
relevant. Thanks,
- Tom
Article: 11310Nick Hartl <"nhartl[no spm]"@earthlink.net> > wrote in message = <35C67A4C.9D020414@earthlink.net>... >JUST SAY NO!!! Don't do it!!!. The demon of async wierdness show his = ugly >head!!! Seconded >Just my opinion but async style design while at time doing some neat = circuit >tricks much more often leads to bad uglyness. Async stuff should only = be >used when it is absolutly totally completly 100% impossible to get the >desired function in a syncronous manner. Nod. >That being said I have done some async stuff, but garanteed fixed delay = in >an FPGA no way! The only thing you can hope for is to garantee what = signal >gets there first. Minimum delays are not something FPGA companies are = in a >big hurry to spec. So even here you take big risks. And just when you thought your design was working safely, the vendor = does a die-shrink. Andy McC Cambridge, UKArticle: 11311
"Mark Purcell" <map@NOSPAM_transtech-DSP.com> wrote:
>Does anyone know of a portable way to converting a std_logic_vector to
>an integer value (such as the v1d2int function in Viewlogic) so that it may
>
>be used in a comparison? A little off-topic I know, but I'm trying to
>evaluate some FPGA synthesis tools with a large VHDL file.
>
Using ieee's numeric_std library:
int_sig <= to_integer(unsigned(slv_sig))
--
Dave Farrance
Article: 11312Simon, I understand, thanks. Two PCI interfaces, do 'usually' require two PCI interfaces ;-) Have you considered using any of the off the shelf PCI interfaces? They are vastly cheaper, and much faster to implement... I have done about 12 PCI interfaces in FPGAs, but these days, the ones available are so good, so cheap and so much more functional....I have been opting to use them for at least a year now. What happens to PCI interfaces in FPGAs, is the implementer usually forgest just how difficult the back end interface is. The front end PCI interface is only about %25 of the work....the back end is about %25, the placing and routing is about another %25 and there is always %25 somewhere you forget to allow for (re-doing logic to make timing or something unforseen). My point is, buying a 'core' is not the panacea a lot of people believe it is. Austin Simon Ramirez <s_ramirez@email.msn.com> wrote in article <ubOzCcov9GA.156@upnetnews03>... > Austin, > This one is an easy one. It is because my board is a PCI target in the > system; therefore, I have to implement a PCI target agent in order to > communicate on the PCI bus with the system CPU board. > Then I have an on-board component that has a PCI interface; however, it > is downstream in the flow, and a DSP communicates with it. Since the > component has a PCI interface, the only way to communicate with it is to > implement a PCI Initiator agent. This PCI bus is completely internal to the > board and is totally independent to the external PCI bus. > -Simon > > > Austin Franklin wrote in message <01bdbe29$45d2c760$31cab7c7@drt3>... > >> I am doing a board level design that uses four FPGAs, two of which > >> implement PCI interfaces. > > > >I am curious why you would require two FPGAs to implement a PCI interface? > > > >Austin Franklin > >darkroom@ix.netcom.com > > > > >Article: 11313
Tony, There is an actual equation for the placer score but I don't remember it. If you have timing constraints, that is part of the score. The type and "cost" of resources used is another part if I remember correctly. As a Xilinx FAE I kinda ignore this score but I do watch the router score. This number correlates to the time constraints. It is the total number of picoseconds that are not meeting your constraints. If the number is 10000 then there is one path that is missing the timespec by 10ns or there are 10 paths that are missing by 1 ns or any other combination. I tell my users that if you have a large timing score after 2-3 routes then stop par. CNTL-C if you are using command line...or wait if you are using the GUI. For this reason I always limit the router iterations when I first run a design so it will stop soon if the timing is way off. After par stops, use the timing analyzer or trce to determine what paths are failing. At that point you can re-do your timing constraints if it is a false or multi-cycle path or change your design. Adding pipeline stages or changing your code can help alot! That was a long answer for a quick question but hopefully it will help somebody! Kate Xilinx FAE in RaleighArticle: 11314
Thanks, I'll have a good look there. Regards, Mark. Remove NOSPAM_ from email address Richard Schwarz <aps@associatedpro.com> wrote in article <35C79591.6F170CD7@associatedpro.com>... > Mark , > > Check at http://www.associatedpro.com under SUPPORT and then TECH SOLUTIONS. > There are a bunch of technical solutions listed there mostly for VHDL and > FPGAs. I know there is code there to do what you want. >Article: 11315
>So I ask you What do you mean by "gate"? For a discussion on the topic of gatecounting in FPGAs (with greatly-appreciated input from Ray Andraka and a few others who frequently post to this newsgroup), please see my article 'Counting on gatecounting? Don't count on it' in the August 3, 1998 issue of EDN Magazine (http://www.ednmag.com). Feedback always appreciated! Brian Dipert Technical Editor: Graphics, Memory and Programmable Logic EDN Magazine: The Design Magazine Of The Electronics Industry 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** edndipert@NOSPAM.worldnet.att.net Visit me at <http://members.aol.com/bdipert>Article: 11316
There are plenty of very good reasons to prototype microcontrollers in FPGAs. And even a few where the production makes sense (such as providing very special functionality in a very small package in low volumes). You can always move to ASIC in high volumes in the sub $5 area including 4-8K of RAM/ROM! However, I recommend using VAutomations V8-microRISC CPU as it doesn't have the intellectual property issues of being software compatible with a leading uC company which has a BIG legal staff. http://www.microchip.com/0/Company/Editorial/PressReleasefiles/28.htm Wade D. Peterson wrote: > > "Austin Franklin" <darkroo5m@ix.netcom.com> wrote: > > >Wade D. Peterson <peter299@maroon.tc.umn.edu> wrote in article > ><6p8nqs$2ij$1@news1.tc.umn.edu>... > >> Silicore Corporation now has a VHDL 8-bit RISC uC core for FPGA > >> available. The processor is compatible with the industry standard > >> 'PIC' processors. For more information see <www.silicore.net>. > > >$10,000 for a PIC processor that takes up 80% of an OR2CA15-4 FPGA? It > >would seem more prudent to buy a far less expensive exteral PIC processor > >and a smaller/cheaper FPGA to do the same job. > > >Does anyone else think this is a real step backwards? > > >Austin Franklin > >darkroom@ix.netcom.com > > I think I would agree with your general observation. However, it does > make sense in specialized applications. The product was originally > designed for sensor electronics, with very small board sizes. For > example, the original design was done to measure pressure inside of > Pratt & Whitney jet aircraft engines. The printed circuit board is > about the size of a large US Postage stamp, and there wasn't enough > room in their for another package. > > If you have plenty of board space, then I think you're right. > However, in many sensor, medical and military applications there just > isn't enough room. > > In another application, we're looking at military electronics. Full > mil-spec parts are getting very hard to find, are expensive, and are > difficult to insure deliveries over a 10-12 year product life cycle. > However, the FPGA microcontroller solves a lot of these problems. > It's quick and easy to do, it's fully mil-spec complient, and it's > portable so that the design can be upgraded as technology advances. > > Also, the FPGA design runs faster than the original PIC parts. The > evaluation kit shown on our web page runs at the same speed as the > fastest PIC processor. That's on a medium speed FPGA. The design > simulates just fine at twice the speed using more state-of-the-art > parts. > > Wade Peterson, Silicore Corporation > www.silicore.net e-mail: peter299@maroon.tc.umn.edu -- Eric Ryherd eric@vautomation.com VAutomation Inc. Synthesizable VHDL and Verilog Cores 20 Trafalgar Sq. #443 Microprocessors and Serial Communications Nashua, NH 03063 8086 80186 V8-uRISC 6502 Z80 USB 1394 HDLC Ethernet (603)882-2282 FAX:(603)882-1587 http://www.vautomation.comArticle: 11317
Wade D. Peterson wrote: - ->Does somebody know the prices (not exact) of xilinx ->FPGA and CPLD. (small qantities (10..20)) - - That's always a tough one. If you have a Digi-key catalog around, - they've got a whole bunch of Xilinx numbers and prices. for a more complete listing check out www.marshall.comArticle: 11318
While you are at it, your best bet would be to go to www.insight-electronics.com Regards, tom --- Tom Curran Memec Design Services -- Boston url: www.memecdesign.com email: tom_curran@memecdesign_dot_comArticle: 11319
Andy Peters wrote: > Paul Oh <paul@moray.cs.columbia.edu> wrote in article > <Pine.GSO.3.96.980727124610.6724A-100000@moray.cs.columbia.edu>... > > > I am newbie to FPGA. I am looking into programming my own silicon. > Can > > any one give pointers (books, websites) into developing motion > control > > IC's? > > > > Specifially: PID (proportional-integral-derivative) control > > Trapezoidal motion profiles > > IMHO: > > If you're serious about PID loops, etc, forget the FPGA and use a > microcontroller or one of the new fast cheap DSPs. You'll be glad > you did. > > If you're serious about motion control, forget rolling your own and > buy an off-the-shelf solution, like CompuMotor or something like > that. You'll be glad you did. > > > PS: I have *never* programmed FPGA's before (I am a mechie). I > have a > > high-level understanding of the design process: Essentially you > burn an > > FPGA just like an EPROM right using schematic CAD or C-like > programming > > languages right? I intend to use Xilinx's development > > board/tools. I do have a good grasp on logic, digital design, > control > > systems, programming and embedded micros though. > Motor controls are not extraordinarily difficult to implement in FPGAs. However, you should have a background in motion control before attempting to roll your own, as there are many pitfalls for the neophyte. If you intend to use an FPGA only for the motion control, and your control algorithm is one that is supported by off the shelf chips, you'd be better off using the canned solution. However, if you intend to integrate custom logic in with the controller, or have an algorithm not supported by the off-the-shelf solution, the FPGA may be a good idea. As for the FPGA design, the design is captured either as a schematic or in one of several textual hardware description languages. If the desired clock rates are low, you can get away with sloppy design practices using either entry method. As your required performance and/or density increases, good design technique, knowledge of the FPGA architecture and the idiosyncracies of the synthesis engine (if a hardware description language is used) become more important for a successful design. The hardware description languages (predominantly VHDL, Verilog and Abel) used for FPGAs are rather different than C, and will probably add another steep learning curve to your task. The captured design is translated, mapped, placed and routed by the FPGA tools. Translation converts the entered design into a database understandable by the tools. Mapping breaks the design into logic units consistent with the device architecture, and usually includes some logic optimization. The place and route assigns the mapped logic to locations in the FPGA then turns on switches in the routing matrix to make the connections between logic blocks. If the designer understands the device architecture, he can bias the entered design to take advantage of device features. This combined with pre-placing logic blocks (floorplanning) can result in substantially better results in terms of both performance and area (number of cells used). The resulting placement and routing is converted into a bitstream that is loaded into the device. In that respect, the design flow is more like compiling a higher level language into machine code. That machine code (or in this case the bit stream) is what gets loaded into the eprom or FPGA. > As for designing FPGAs, check out the web sites of Xilinx or Altera > or Actel or any of the other FPGA vendors. And be prepared to climb > a somewhat steep learning curve. > > -andy > > -- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatories > apeters@noao.edu.NOSPAM -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11320
Ray Andraka <no_spam_randraka@ids.net> wrote in article <35C77D65.E2549B2E@ids.net>... > Motor controls are not extraordinarily difficult to implement in FPGAs. > However, you should have a background in motion control before attempting > to roll your own, as there are many pitfalls for the neophyte. If you > intend to use an FPGA only for the motion control, and your control > algorithm is one that is supported by off the shelf chips, you'd be > better off using the canned solution. However, if you intend to > integrate custom logic in with the controller, or have an algorithm not > supported by the off-the-shelf solution, the FPGA may be a good idea. But motors also require amplifiers and drivers and other thing beyond the FPGA, which I agree is the relatively easy part. The other issues regarding motors includes acceleration/deceleration curves, increasing motor speed and going through resonances (which could cause the motor to stall), dealing with stalling and overtorquing, microstepping, power control so you can shut off the high voltage and maintain position and not waste power, and so forth. I thought controlling motors was *really* easy, until the local mechanical engineer disabused me of that notion. -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories apeters@noao.edu.NOSPAMArticle: 11321
On Mon, 27 Jul 1998 12:52:22 -0400, Paul Oh <paul@moray.cs.columbia.edu> wrote: Check out National Semiconductor's LM628/629 motion controller ICs. > >Hello to all in comp.arch.fpga > >I am newbie to FPGA. I am looking into programming my own silicon. Can >any one give pointers (books, websites) into developing motion control >IC's? > >Specifially: PID (proportional-integral-derivative) control >Trapezoidal motion profiles > >Thanks very much. > >PS: I have *never* programmed FPGA's before (I am a mechie). I have a >high-level understanding of the design process: Essentially you burn an >FPGA just like an EPROM right using schematic CAD or C-like programming >languages right? I intend to use Xilinx's development >board/tools. I do have a good grasp on logic, digital design, control >systems, programming and embedded micros though. > > >---------------------------------------------------------------------------- >Paul Oh >PhD Candidate >Columbia University >Dept of Mechanical Engineering >Center for Research in Intelligent Systems >http://www.cs.columbia.edu/~paul >---------------------------------------------------------------------------- > > > Steven J. Ackerman, Consultant ACS, Sarasota, FL sja@gte.net http://www.acscontrol.comArticle: 11322
This is a multi-part message in MIME format.
--------------47A3A813B9786DAA9C8F7D05
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Mark ,
Check at http://www.associatedpro.com under SUPPORT and then TECH SOLUTIONS.
There are a bunch of technical solutions listed there mostly for VHDL and
FPGAs. I know there is code there to do what you want.
Mark Purcell wrote:
> Does anyone know of a portable way to converting a std_logic_vector to
> an integer value (such as the v1d2int function in Viewlogic) so that it may
>
> be used in a comparison? A little off-topic I know, but I'm trying to
> evaluate some FPGA synthesis tools with a large VHDL file.
>
> Thanks in advance,
>
> Mark Purcell
> Remove NOSPAM_ from email address.
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
--------------47A3A813B9786DAA9C8F7D05
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Richard Schwarz
Content-Disposition: attachment; filename="vcard.vcf"
begin: vcard
fn: Richard Schwarz
n: Schwarz;Richard
org: Associated Professional Systems
adr: 3003 Latrobe Court;;;Abingdon;MD;21009;USA
email;internet: aps@associatedpro.com
title: President
tel;work: 410.569.5897
tel;fax: 410.661.2760
tel;home: 410.515.3883
x-mozilla-cpt: ;0
x-mozilla-html: FALSE
version: 2.1
end: vcard
--------------47A3A813B9786DAA9C8F7D05--
Article: 11323
"Austin Franklin" <dark9room@ix.netcom.com> writes:
> > I am doing a board level design that uses four FPGAs, two of which
> > implement PCI interfaces.
^ He used a plural !
>
> I am curious why you would require two FPGAs to implement a PCI interface?
I think he means 2 FPGAs which implement a PCI I/F *each* so that both of
them can sit on the PCI bus and do their stuff.
Regards,
Zoltan
--
+------------------------------------------------------------------+
| To reach me write to zoltan in the domain of: bendor com au |
+--------------------------------+---------------------------------+
| Zoltan Kocsi | I don't believe in miracles |
| Bendor Research Pty. Ltd. | but I rely on them. |
+--------------------------------+---------------------------------+
Article: 11324Mark wrote: ... lots snipped ... > As Rick Collins wrote: > > I don't know the Mentor system, but I would expect that you can connect > > the Xilinx part to the rest of the board without reference to the pin > numbers. > To my knowledge, you cannot connect them without reference to the pin numbers. When entering a design for an FPGA (in other design systems), the components are interconnected by pins, but that does not use numbers. Pins on a symbol are connected to the underlying schematic by pin names. So I would think that you "should" be able to do board level design without having pin numbers. That is not to say that you can do that with Mentor. Oh well. > And Austin Franklin wrote: > > Though there has been advice in the past (bad advice I might add) to not > > lock your I/Os, I (and many others) STRONGLY recommend locking the I/O > > pins, intelligently that is ;-) > I have never heard this before and it would appear to me that the so called > "intelligent" pin placement would be little more than a good guess. For our > applications this would be too restrictive. You didn't present the argument > which supports your "STRONG" recommendation for locking the I/O - but if > this makes sense I would be interested in hearing it. I would agree with Austin to a point. In my current design I understood the internal architechture enough to be able to visualize a good layout inside the chip. I could then pick a pretty good placement for the pins. The placer still doesn't completely understand what I wanted to do, but it was good enough. If not, I would have then had to start placing the internals of the design. I wasn't looking forward to that. -- Rick Collins rickman@XYwriteme.com remove the XY to email me.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z